ASM2P2310A November 2006 rev 0.3 2.5-V TO 3.3-V High-Performance Clock Buffer Features Product Description The ASM2P2310A is a high-performance, low-skew clock • High-Performance 1:10 Clock Driver for General Purpose buffer that operates up to 200MHz. Two banks of five applications. Operates up to 200 MHz at 3.3V Supply outputs each provide low-skew copies of CLK. After power Voltage up, the default state of the outputs is low regardless of the • Pin-to-Pin Skew < 100 pS at 3.3V Supply Voltage state of the control pins. For normal operation, the outputs • Supply Range : 2.3V to 3.6V of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low • Operating Temperature Range : -40°C to 85°C and a negative clock edge is detected on the CLK input. • Output Enable Glitch Suppression The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into • Distributes One Clock Input to Two Banks of Five the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK Outputs input. The device operates in a 2.5V and 3.3V environment. • 25Ω On Chip Series Damping Resistors The built-in output enable glitch suppression ensures a • Packaged in 24 Pin TSSOP Package synchronized output enable sequence to distribute full period clock signals. The ASM2P2310A is characterized for operation from -40°C to 85°C. Block Diagram CLK 24 3 25Ω 4 25Ω 5 25Ω 8 25Ω 9 1G 11 25Ω LOGIC CONTROL 21 1Y0 25Ω 20 1Y1 25Ω 17 1Y2 25Ω 16 1Y3 25Ω 12 1Y4 25Ω 2G 13 LOGIC CONTROL PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. 2Y0 2Y1 2Y2 2Y3 2Y4 ASM2P2310A November 2006 rev 0.3 Pin Configuration GND 1 24 CLK VDD 2 23 VDD 1Y0 3 22 VDD 1Y1 4 21 2Y0 1Y2 5 20 GND 6 ASM2P2310A 19 2Y1 GND GND 7 18 GND 1Y3 8 17 2Y2 1Y4 9 16 2Y3 VDD 10 15 VDD 1G 11 14 VDD 2Y4 12 13 2G Pin Description Pin # Pin Name Type Description 1 GND P Ground Pin 2 VDD P DC Power supply, 2.3 V – 3.6V 3 1Y0 O Buffered Output Clock 4 1Y1 O Buffered Output Clock 5 1Y2 O Buffered Output Clock 6 GND P Ground Pin 7 GND P Ground Pin 8 1Y3 O Buffered Output Clock 9 1Y4 O Buffered Output Clock 10 VDD P 11 1G I 12 2Y4 O 13 2G I 14 VDD P DC power supply, 2.3V – 3.6V Output enable control for 1Y[0:4] outputs. meaning the 1Y[0:4] clock outputs follow the high. Buffered Output Clock Output enable control for 2Y[0:4] outputs. meaning the 2Y[0:4] clock outputs follow the high. DC power supply, 2.3V – 3.6V 15 VDD P DC power supply, 2.3V – 3.6V 16 2Y3 O Buffered Output Clock 17 2Y2 O Buffered Output Clock 18 GND P Ground Pin 19 GND P Ground Pin 20 2Y1 O Buffered Output Clock 21 2Y0 O Buffered Output Clock 22 VDD P DC power supply, 2.3V – 3.6V 23 VDD P DC power supply, 2.3V – 3.6V 24 CLK I Input reference frequency This output enable is active-high, input clock (CLK) if this pin is logic This output enable is active-high, input clock (CLK) if this pin is logic 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 2 of 11 ASM2P2310A November 2006 rev 0.3 Function Table Input 2G 1G L L Output CLK 1Y[0:4] 2Y[0:4] ↓ L L 1 H L ↓ CLK L L H ↓ L CLK1 H H ↓ CLK1 CLK1 Note: 1 After detecting one negative edge on the CLK input, the output follows the input CLK if the control pin is held high. Detailed Description Output Enable Glitch Suppression Circuit The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the input clock) (see Figure 1). The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for predictable operation. CLK Gn Yn tsu(en) th(en) a) Enable Mode CLK Gn Yn tsu(dis) th(dis) b) Disable Mode Figure 1. Enable and Disable Mode Relative to CLK↓ 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 3 of 11 ASM2P2310A November 2006 rev 0.3 Absolute Maximum Ratings Parameter Rating -0.5V to 4.6V Supply Voltage range, VDD Input Voltage range, VI 1,2 -0.5 V to VDD + 0.5 V Output Voltage range, VO1,2 Continuous total output current, IO (VO = 0 to VDD) Package thermal impedance, θJA3: PW package -0.5 V to VDD + 0.5 V ±50 mA 120°C/W -65°C to 150°C Storage temperature range Tstg 2KV Static Discharge Voltage , tDV (As per JEDEC STD22- A114-B) Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Notes : 1 The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2 This value is limited to 4.6 V maximum. 3 The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions1 Parameter Supply voltage, VDD Low-level input voltage, VIL High-level input voltage, VIH Low-level output current, IOL Typ 2.3 2.5 3.3 Max 3.6 VDD = 3V to 3.6V 0.8 VDD = 2.3V to 2.7V 0.7 VDD = 3V to 3.6V VDD = 2.3V to 2.7V 2 VDD VDD = 3V to 3.6V 12 VDD = 2.3 V to 2.7V 6 VDD = 3V to 3.6V 12 VDD = 2.3V to 2.7V 6 Operating free-air temperature, TA -40 Unit V V V 1.7 0 Input voltage, VI High-level output current, IOH Min 85 V mA mA °C Note:1 Unused inputs must be held high or low to prevent them from floating. 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 4 of 11 ASM2P2310A November 2006 rev 0.3 Electrical Characteristics Over recommended operating free-air temperature range (unless otherwise noted) Symbol Parameter Test Conditions VIK Input voltage II Input current VI = 0V or VDD Static device current CLK = 0V or VDD, IDD2 VDD = 3V, Min Typ1 II = -18 mA CI Input capacitance VDD = 2.3V to 3.6V, CO Output capacitance VDD = 2.3V to 3.6V, IO = 0 mA Max Unit -1.2 V ±5 µA 80 µA VI = 0V or VDD 2.5 pF VI = 0V or VDD 2.8 pF Note: 1 All typical values are at respective nominal VDD. 2 For ICC over frequency, see Figure 6. VDD = 3.3 V ±0.3 V Symbol Parameter Test Conditions VDD = Min to Max, VOH High-level output voltage VDD = 3 V IOH = -12 mA VDD - 0.2 2.1 IOH = -6 mA 2.4 VDD = Min to Max, VOL IOH IOL Low-level output voltage VDD = 3V High-level output current Low-level output current IOH = -100 µA Min Typ1 Max V IOL = -100 µA 0.2 IOL = 12mA 0.8 IOL = 6 mA 0.55 VDD = 3V, VO = 1V VDD = 3.3V, VO = 1.65V VDD = 3.6V, VO = 3.135V VDD = 3V, VO = 1.95V VDD = 3.3V, VO = 1.65V VDD = 3.6V, VO = 0.4V Unit V -28 -36 -14 mA 28 36 mA 14 Note: 1 All typical values are at respective nominal VDD. VDD = 2.5 V ±0.2 V Symbol Parameter VOH High-level output voltage VOL Low-level output voltage IOH High-level output current IOL Test Conditions Low-level output current VDD = Min to Max, IOH = -100 µA VDD = 2.3V IOH = -6 mA VDD = Min to Max, Typ1 IOL = 6 mA VDD = 2.3V, VO = 1V VDD = 2.5V, VO = 1.25V VDD = 2.7V, VO = 2.375V VDD = 2.3V, VO = 1.2V VDD = 2.5V, VO = 1.25V Max VDD - 0.2 Unit V 1.8 0.2 IOL = 100 µA VDD = 2.3V VDD = 2.7V, Min 0.55 V -17 mA -25 -10 17 VO = 0.3V mA 25 10 Note: 1 All typical values are at respective nominal VDD. 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 5 of 11 ASM2P2310A November 2006 rev 0.3 Timing Requirements Over recommended ranges of supply voltage and operating free-air temperature Symbol fclk Parameter Clock frequency Test Conditions Min Typ Max VDD = 3 V to 3.6V 0 200 VDD = 2.3 V to 2.7V 0 170 Unit MHz Switching Characteristics Over recommended operating free-air temperature range (unless otherwise noted) VDD = 3.3 V ±0.3 V (See Figure 2) Symbol Parameter tPLH CLK to Yn tPHL Test Conditions f = 0 MHz to 200 MHz For circuit load, see Figure 2. Min Typ 1.3 Max Unit 2.8 nS tsk(o) Output skew (Ym to Yn)1(see Figure 4) 100 pS tsk(p) Pulse skew (see Figure 5) 250 pS 500 pS tsk(pp) Part-to-part skew tr Rise time (see Figure 3) VO = 0.4V to 2V 0.7 2 V/nS tf Fall time (see Figure 3) VO = 2 V to 0.4V 0.7 2 V/nS tsu(en) Enable setup time,G_high before CLK↓ 0.1 nS tsu(dis) Disable setup time, G_low before CLK↓ 0.1 nS th(en) Enable hold time, G_high after CLK ↓ 0.4 nS th(dis) Disable hold time, G_low after CLK ↓ 0.4 nS Note: 1 The tsk(o) specification is only valid for equal loading of all outputs VDD = 2.5 V ±0.2 V (See Figure 2) Symbol Parameter Test Conditions f = 0MHz to 170MHz For circuit load, see Figure 2. tPLH CLK to Yn tPHL Min 1.5 Typ Max Unit 3.5 nS tsk(o) 1 Output skew (Ym to Yn) (see Figure 4) 170 pS tsk(p) Pulse skew (see Figure 5) 400 pS tsk(pp) Part-to-part skew tr Rise time (see Figure 3) tf Fall time (see Figure 3) 600 pS VO = 0.4V to 1.7V 0.5 1.4 V/nS VO = 1.7V to 0.4V 0.5 1.4 V/nS tsu(en Enable setup time,G_high before CLK↓ 0.1 nS tsu(dis) Disable setup time, G_low before CLK↓ 0.1 nS th(en) Enable hold time, G_high after CLK ↓ 0.4 nS th(dis) Disable hold time, G_low after CLK ↓ 0.4 nS Note: 1 The tsk(o) specification is only valid for equal loading of all outputs. 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 6 of 11 ASM2P2310A November 2006 rev 0.3 Parameter Measurement Information From Output Under Test CL = 25 pF on Yn 500Ω A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50Ω, tr < 1.2 ns, tf < 1.2 ns. Figure 2. Test Load Circuit VDD 50% VDD CLK 0V tPLH tPHL VOH 1.7V or 2V Yn 50% VDD 0.4V tr 0.4V VOL tf Figure 3. Voltage Waveforms Propagation Delay Times VDD CLK 0V VOH 50% VDD Any Y VOL VOH 50% VDD Any Y VOL tSK(O) tSK(O) Figure 4. Output Skew 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 7 of 11 ASM2P2310A November 2006 rev 0.3 VDD 50% VDD CLK 0V tPLH tPHL VOH 50% VDD Yn VOL NOTE: tsk(p) = | tPLH − tPHL | Figure 5. Pulse Skew SUPPLY CURRENT vs FREQUENCY f – Frequency – MHz Figure 6. 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 8 of 11 ASM2P2310A November 2006 rev 0.3 Package Information 24L TSSOP (173 mil) Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.043 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.031 0.041 0.80 1.05 D 0.3031 0.311 7.70 7.90 L 0.020 0.030 0.50 0.75 E 0.252 BSC 6.40 BSC E1 0.169 0.177 4.30 4.50 R 0.004 …. 0.09 ….. R1 0.004 …. 0.09 ….. b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 L1 0.039 REF 1.0 REF e 0.026 BSC 0.65 BSC a 0° 8° 0° 8° 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 9 of 11 ASM2P2310A November 2006 rev 0.3 Ordering Information Part Number Marking Package Type Temperature ASM2P2310AF-24TR 2P2310AF 24-Pin TSSOP, TAPE & REEL, Pb Free Commercial ASM2P2310AF-24TT 2P2310AF 24-Pin TSSOP, TUBE, Pb Free Commercial ASM2P2310AG-24TR 2P2310AG 24-Pin TSSOP, TAPE & REEL, Green Commercial ASM2P2310AG-24TT 2P2310AG 24-Pin TSSOP, TUBE, Green Commercial ASM2I2310AF-24TR 2I2310AF 24-Pin TSSOP, TAPE & REEL, Pb Free Industrial ASM2I2310AF-24TT 2I2310AF 24-Pin TSSOP, TUBE, Pb Free Industrial ASM2I2310AG-24TR 2I2310AG 24-Pin TSSOP, TAPE & REEL, Green Industrial ASM2I2310AG-24TT 2I2310AG 24-Pin TSSOP, TUBE, Green Industrial Device Ordering Information A S M 2 P 2 3 1 0 A F - 2 4 T R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent Nos 5,488,627 and 5,631,920. 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 10 of 11 ASM2P2310A November 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: ASM2P2310A Document Version: v0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5-V TO 3.3-V High-Performance Clock Buffer Notice: The information in this document is subject to change without notice. 11 of 11