QIMONDA HYB18H1G321AF

October 2007
HYB18H1G321AF–10/11/14
GDDR3 Graphics RAM
1-Gbit GDDR3 Graphics RAM
RoHS compliant
Internet Data Sheet
Rev. 0.92
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
HYB18H1G321AF–10/11/14
Revision History: 2007-10, Rev. 0.92
Page
Subjects (major changes since last revision)
All
tWR changed from 14 to 13
tRP at Speed Bin -10 is changed from 13 to 14
IDD Values were added.
39
36
Previous Revision: Rev. 0.91, 2007-08-08
All
Typo changes.
Previous Revision: Rev. 0.80, 2007-07-10
All
Adapted internet editition
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qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
06122007-MW7D-3G3M
2
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
1
Overview
This chapter lists all main features of the product family HYB18H1G321AF–10/11/14 and the ordering information.
1.1
Features
• 1.8 V VDDQ IO voltage
• 1.8 V VDD core voltage
• Monolithic 1Gbit GDDR3 with an internally programmable
organization of either two separate 512MBit memories
(2048 K x 32 I/O x 8 banks) with separate Chip Select, or
one 1Gb memory (4096 K x 32 I/O x 8 banks)
• Two CS: 4096 rows and 512 columns (128 burst start
locations) per bank
– One CS: 8192 rows and 512 columns (128 burst start
locations) per bank
• Differential clock inputs (CLK and CLK)
• CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
• Write latencies of 3, 4, 5, 6, 7
• Burst sequence with length of 4, 8
• 4n pre fetch
• Short RAS to CAS timing for Writes
• tRAS Lockout support
• tWR programmable for Writes with Auto-Precharge
• Data mask for write commands
• Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data
• Single ended WRITE strobe (WDQS) per byte. WDQS
center-aligned with WRITE data
• DLL aligns RDQS and DQ transitions with Clock
• Programmable IO interface including on chip termination
(ODT)
• Autoprecharge option with concurrent auto precharge
support
• 8k Refresh (32ms)
• Autorefresh and Self Refresh
• PG-TFBGA-136 package
• Calibrated output drive. Active termination support
• RoHS Compliant Product 1)
TABLE 1
Ordering Information
Part Number1)
Organization
Clock (MHz)
Package
HYB18H1G321AF–10/11/14
×32
1000 @CL12
PG-TFBGA-136
700 @CL11
900 @CL11
1) HYB: designator for memory components
18H: VDDQ = 1.8V
1G: 1 Gbit
32: x32 organization
A: Product Revision
F: Lead and Halogen-Free
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 0.92, 2007-10
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Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
1.2
Description
The Qimonda 1-Gbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive
applications like PC graphics systems. The chip is programmable into two different configurations. In the default mode the
architecture is organized as two 512 Mbit memories of 8 banks, each (two CS mode). In an alternate configuration, it behaves
as a conventional, 8-bank 1 Gbit DRAM (one CS mode). Note that at 1000 MHz speed grade only one CS mode is supported.
HYB18H1G321AF–10/11/14 uses a double data rate interface and a 4n-pre fetch architecture. The GDDR3 interface transfers
two 32 bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4n-pre fetch a single write or read access
consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, onehalf-clock-cycle data transfers at the I/O pins.
Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively
in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized
per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are centeraligned with data for write commands.
The HYB18H1G321AF–10/11/14 operates from a differential clock (CLK and CLK). Commands (addresses and control
signals) are registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is
referenced to both edges of RDQS.
In this document references to “the positive edge of CLK” imply the crossing of the positive edge of CLK and the negative edge
of CLK. Similarly, the “negative edge of CLK” refers to the crossing of the negative edge of CLK and the positive edge of CLK.
References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar
fashion.
Read and write accesses to the HYB18H1G321AF–10/11/14 are burst oriented. The burst length is fixed to 4 and 8 and the
two least significant bits of the burst address are “Don’t Care” and internally set to LOW. Accesses begin with the registration
of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank and the column location for the burst access. In two CS mode,
each of the 2 x 8 banks consists of 4096 row locations and 512 column locations. In one CS mode, the number of row locations
doubles to 8192 rows while the number of column location remains unchanged at 512 columns. An AUTO PRECHARGE
function can be combined with READ and WRITE to provide a self-timed row precharge that is initiated at the end of the burst
access. The pipe lined, multibank architecture of the HYB18H1G321AF–10/11/14 allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge and activation time.
The “On Die Termination” interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The
termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register.
The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (auto calibration) or
to 35, 40 or 45 Ohms.
Auto Refresh and Power Down with Self Refresh operations are supported.
An industrial standard PG-TFBGA-136 package is used which enables ultra high speed data transfer rates and a simple
upgrade path from former DDR Graphics SDRAM products.
Rev. 0.92, 2007-10
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Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
2
Configuration
FIGURE 1
Ballout 1Gbit GDDR3 Graphics RAM in 1-CS mode in non Merged Mode(Top View; MF = Low)
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Rev. 0.92, 2007-10
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Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 2
Ballout 1Gbit GDDR3 Graphics RAM in 2-CS mode in non Merged Mode(Top View; MF = Low)
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Rev. 0.92, 2007-10
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Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 3
Ballout 1Gbit GDDR3 Graphics RAM in Merged Mode
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Rev. 0.92, 2007-10
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Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
2.1
Ball Definition and Description
TABLE 2
Ball Description
Ball
Type
Detailed Function
CLK, CLK
Input
Clock:
CLK and CLK are differential clock inputs. Address and command inputs are latched on the positive
edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are referenced to CLK. CLK and CLK are not
internally terminated.
CKE
Input
Clock Enable:
CKE HIGH activates and CKE LOW deactivates the internal clock and input buffers. Taking CKE
LOW provides Power Down. If all banks are precharged, this mode is called Precharge Power Down
and Self Refresh mode is entered if a Auto Refresh command is issued. If at least one bank is open,
Active Power Down mode is entered and no Self Refresh is allowed. All input receivers except CLK,
CLK and CKE are disabled during Power Down. In Self Refresh mode the clock receivers are
disabled too. Self Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power
Down without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK.
The value of CKE is latched asynchronously by Reset during Power On to determine the value of the
termination resistor of the address and command inputs.
CKE is not allowed to go LOW during a RD, a WR or a snoop burst.
CS0
Input
Chip Select:
CS0 enables the command decoder when low and disables it when high. When the command
decoder is disabled, new commands with the exception of DTERDIS are ignored, but internal
operations continue. In 2-CS mode, CS0 is exclusively used for MRS, EMRS and SREFEN.
CS1
Input
Chip Select:
CS1 is only evaluated in 2-CS mode, and it is used as the chip-select signal for the second memory
block.
RAS, CAS,
WE
Input
Command Inputs:
Sampled at the positive edge of CLK, CAS, RAS, and WE define (together with corresponding CS)
the command to be executed.
DQ<0:31>
I/O
Data Input/Output:
The DQ signals form the 32 bit data bus. During READs the balls are outputs and during WRITEs
they are inputs. Data is transferred at both edges of RDQS.
DM<0:3>
Input
Input Data Mask:
The DM signals are input mask signals for WRITE data. Data is masked when DM is sampled HIGH
with the WRITE data. DM is sampled on both edges of WDQS. DM0 is for DQ<0:7>, DM1 is for
DQ<8:15>, DM2 is for DQ<16:23> and DM3 is for DQ<24:31>. Although DM balls are input-only,
their loading is designed to match the DQ and WDQS balls.
RDQS<0:3>
Output
Read Data Strobes:
RDQSx are unidirectional strobe signals. During READs the RDQSx are transmitted by the Graphics
SDRAM and edge-aligned with data. RDQS have preamble and postamble requirements. RDQS0 is
for DQ<0:7>, RDQS1 for DQ<8:15>, RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>.
WDQS<0:3>
Input
Write Data Strobes: WDQSx are unidirectional strobe signals. During WRITEs the WDQSx are
generated by the controller and center aligned with data. WDQS have preamble and postamble
requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for DQ<16:23> and WDQS3
for DQ<24:31>.
Rev. 0.92, 2007-10
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Ball
Type
Detailed Function
BA<0:2>
Input
Bank Address Inputs:
BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being
applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED
MODE REGISTER SET commands.
A<0:11>
Input
Address Inputs:
During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the
column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is
precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and
the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is
precharged (selected by BA<0:2>, A8 LOW) or all 8 banks are precharged (A8 HIGH). During
(EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are
sampled with the positive edge of CLK.
A<12>
Input
Address Inputs:
A12 define the MSB of the row address during an ACTIVATE in 1-CS mode.
ZQ
-
ODT Impedance Reference:
The ZQ ball is used to control the ODT impedance.
RESET
Input
Reset pin:
The RES pin is a VDDQ CMOS input. RES is not internally terminated. When RES is at LOW state the
chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High
transition of the RES signal is used to latch the CKE value to set the value of the termination resistors
of the address and command inputs. After exiting the full reset a complete initialization is required
since the full reset sets the internal settings to default.
MF
Input
Mirror function pin:
The MF pin is a VDDQ CMOS input. This pin must be hardwired on board either to a power or to a
ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow
for an easier routing on board for a back to back memory arrangement.
SEN
Input
Enables Boundary Scan Functionality:
If Boundary Scan is not used PIN should be constantly connected to GND.
VREF
Supply
Voltage Reference:
VREF is the reference voltage input.
VDD, VSS
Supply
Power Supply:
Power and Ground for the internal logic.
VDDQ, VSSQ
Supply
I/O Power Supply:
Isolated Power and Ground for the output buffers to provide improved noise immunity.
NC, RFU
-
Please do not connect No Connect and Reserved for Future Use balls.
RAR
2.2
Reserved for Alternate Rank
Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function
allows for efficient routing in a clam shell configuration.
Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default
ball configuration (see Figure 2) corresponds to MF = LOW. The CS1 and A12 balls are not mirrored.
The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that.
Table 3 shows the ball assignment as a function of the logic state applied on MF.
Rev. 0.92, 2007-10
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Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
TABLE 3
Ball Assignment with Mirror
MF Logic State
LOW
HIGH
H3
H10
Signal
RAS
F4
F9
CAS
H9
H4
WE
F9
F4
CS0
H4
H9
CKE
K4
K9
A0
H2
H11
A1
K3
K10
A2
M4
M9
A3
K9
K4
A4
H11
H2
A5
K10
K3
A6
L9
L4
A7
K11
K2
A8
M9
M4
A9
K2
K11
A10
L4
L9
A11
G4
G9
BA0
G9
G4
BA1
H10
H3
BA2
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
2.3
Truth Tables
2.3.1
Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the
chip’s multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions
are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the
assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD,
tRTW and tWTR have to be taken always into account.
TABLE 4
Function Truth Table I
Current State
Ongoing action on bank n
Possible action in parallel on bank m
ACTIVE
ACTIVATE1)
ACT, PRE, WRITE, WRITE/A, READ, READ/A2)
WRITE
3)
ACT, PRE, WRITE, WRITE/A, READ, READ/A4)
WRITE/A5)
ACT, PRE, WRITE, WRITE/A, READ6)
7)
READ
ACT, PRE, WRITE, WRITE/A, READ, READ/A8)
READ/A9)
ACT, PRE, WRITE, WRITE/A, READ, READ/A 8)
PRECHARGE10)
ACT, PRE, WRITE, WRITE/A, READ, READ/A11)
PRECHARGE ALL
10)
12)
POWER DOWN ENTRY
IDLE
-
ACTIVATE 1)
ACT
POWER DOWN ENTRY 12)
-
AUTO REFRESH13)
-
SELF REFRESH ENTRY 12)
14)
MODE REGISTER SET (MRS)
EXTENDED MRS
14)
-
EXTENDED MRS 214)
POWER DOWN
SELF REFRESH
POWER DOWN EXIT
-
15)
SELF REFRESH EXIT
-
16)
-
1) Action ACTIVATE starts with issuing the command and ends after tRCD.
2) During action ACTIVATE an ACT command on another bank is allowed considering tRRD or tRRD_RR, a PRE command on another bank is
allowed any time. WR, WR/A, RD and RD/A are always allowed.
3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge.
4) During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR or tWTR_RR is met.
5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge.
6) During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
has to be separated by at least one NOP from the ongoing command. RD is not allowed before or tWTR or tWTR_RR is met. RD/A is not
allowed during an ongoing WRITE/A action.
7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
8) During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on
another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to
meet tRTW.
9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
10) Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP.
11) During Action ACTIVE an ACT command on another banks is allowed considering tRRD or tRRD_RR. A PRE command on another bank is
allowed any time. WR, WR/A, RD and RD/A are always allowed.
12) During POWER DOWN and SELF REFRESH only the EXIT commands are allowed.
13) AUTO REFRESH starts with issuing the command and ends after tRFC.
14) Actions MODE REGISTER SET, EXTENDED MODE REGISTER SET and EXTENDED MODE REGISTER 2 SET start with issuing the
command and ends after tMRD.
15) Action POWER DOWN EXIT starts with issuing the command and ends after tXPN.
16) Action SELF REFRESH EXIT starts with issuing the command and ends after tXSC.
2.4
Function Truth Table for CKE
TABLE 5
Function Truth Table II (CKE Table)
CKE
N-1
CKE
n
CURRENT STATE
COMMAND
ACTION
L
L
Power Down
X
Stay in Power Down
Self Refresh
X
Stay in Self Refresh
Power Down
DESEL or NOP
Exit Power Down
Self Refresh
DESEL or NOP
Exit Self Refresh 5
All Banks Idle
DESEL or NOP
Entry Precharge Power Down
L
H
H
L
Bank(s) Active
DESEL or NOP
Entry Active Power Down
All Banks Idle
Auto Refresh
Entry Self Refresh
Notes
1.
2.
3.
4.
5.
CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state of the GDDR3 Graphics RAM immediately prior to clock edge n.
COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND.
All states and sequences not shown are illegal or reserved.
DESEL or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 1000 clock
cycles is required before applying any other valid command.
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
3
Boundary Scan
3.1
General Description
The 1-Gbit GDDR3 incorporates a modified boundary scan test mode. This mode doesn’t operate in accordance with IEEE
Standard 1149.1-1990. To save the current GDDR3 ball-out, this mode will scan the parallel data input and output the scanned
data through the WDQS0 pin controlled by SEN.
Note: Both pads bCS1 and A12 will be activated and could be accessed during Boundary Scan.
3.2
Disabling the scan feature
It is possible to operate the 1-Gbit GDDR3 without using the boundary scan feature. SEN (at U-4 of 136- ball package) should
be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode,
RES, MF, WDQS0 and CS will be operating at normal GDDR3 functionalities when SEN is deasserted.
TABLE 6
Boundary Scan Exit Order
BIT#
BALL
BIT#
BALL
BIT#
BALL
BIT#
BALL
BIT#
BALL
BIT#
BALL
1
D-3
13
E-10
25
K-11
37
R-10
49
L-3
61
G-4
2
C-2
14
F-10
26
K-10
38
T-11
50
M-2
62
F-4
3
C-3
15
E-11
27
K-9
39
T-10
51
M-4
63
F-2
4
B-2
16
G-10
28
M-9
40
T-3
52
K-4
64
G-3
5
B-3
17
F-11
29
M-11
41
T-2
53
K-3
65
E-2
6
A-4
18
G-9
30
L-10
42
R-3
54
K-2
66
F-3
7
B-10
19
H-9
31
N-11
43
R-2
55
L-4
67
E-3
8
B-11
20
H-10
32
M-10
44
P-3
56
J-3
9
C-10
21
H-11
33
N-10
45
P-2
57
J-2
10
C-11
22
J-11
34
P-11
46
N-3
58
H-2
11
D-10
23
J-10
35
P-10
47
M-3
59
H-3
12
D-11
24
L-9
36
R-11
48
N-2
60
H-4
Notes
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped.
2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67,
if the chip stays in scan shift mode.
3. An unconnected CS1 and A12 on the board will be read as undefined.
Rev. 0.92, 2007-10
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1-Gbit GDDR3
TABLE 7
Scan Pin Description
PACKAGE SYMBOL
BALL
NORMAL
FUNCTION
TYPE
DESCRIPTION
V-9
SSH
RES
Input
Scan Shift: Capture the data input from the pad at logic LOW and shift the
data on the chain at logic HIGH.
F-9
SCK
CS
Input
Scan Clock: Not a true clock, could be a single pulse or series of pulses.
All scan inputs will be referenced to rising edge of the scan clock
D-2
SOUT
WDQS0
Output Scan Output
V-4
SEN
SEN
Input
Scan Enable: Logic HIGH enables the device into scan mode and will be
disabled at logic LOW. Must be tied to GND when not in use.
A-9
SOE
MF
Input
Scan Output Enable: Enables (registered LOW) and disables (registered
HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor
(typically 1KΩ for normal operation. Tester needs to overdrive this pin to
guarantee the required input logic level in scan mode.
Notes
1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies both to user commands and
manufacturing commands which may exist while RES is deasserted.
2. The Scan Function can be used right after bringing up VDD / VDDQ of the device. No initialization sequence of the device is
required. After leaving the Scan Function it is required to run through the complete initialization sequence.
3. In Scan Mode all terminations for CMD/ADD and DQ, DM, RDQS and WDQS are switched off.
4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE’s should be provided to
top and bottom devices to access the scanned output. When either of the devices is in scan mode, SOE for the other device
which is not in a scan will be disabled.
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1-Gbit GDDR3
4
Functional Description
4.1
Mode Register Set Command (MRS)
The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
up to operate the SGRAM. During a ModeRegister Set
command the address inputs are sampled and stored in the
Mode Register. The Mode Register content can only be set or
changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of tMRD
must be met.
To apply an MRS command, CS0 has to be used.
The Mode Register Bitmap is supported in two configurations.
The first configuration is intended to support the Mid-RangeSpeed application. The second configuration supports higher
clock cycles for CAS latency and is therefore prepared to
support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
FIGURE 4
Mode Register Set Command
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
COD
BA0
0
BA1, BA2
0
COD: Code to be loaded into
the register
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Don't Care
15
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 5
Mode Register Bitmap for Mid-Range-Speed Application
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Rev. 0.92, 2007-10
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16
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 6
Mode Register Bitmap for High-Speed Application
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FIGURE 7
Mode Register Set Timing
CLK#
CLK
Com.
PA
NOP
MRS
t RP
NOP
NOP
A.C.
NOP
t MRD
tMRDR
MRS: MRS command
PA: PREALL command
A.C.: Any other command as READ
RD: READ command
Don't Care
Rev. 0.92, 2007-10
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RD
17
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
4.1.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length of 4 and 8. This value must be
programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column locations
that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses
for that burst take place within this block if a boundary is reached. The starting location within this block is determined by the
two least significant bits A0 and A1 which are set internally to the fixed value of zero each.Reserved states should not be used,
as unknown operation or incompatibility with future versions may result.
4.1.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3).
This device does not support the burst interleave mode.
TABLE 8
Burst Definition
Burst Length
Starting Column Address
Order of Accesses within a Burst
(Type = sequential)
A2 A1 A0
4
—
X
X
0-1-2-3
8
0
X
X
0-1-2-3-4-5-6-7
1
X
X
4-5-6-7-0-1-2-3
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
4.1.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit
of output data.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident
with clock edge n+m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
4.1.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the
first bit of input data.
4.1.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and
A8-A11 set to the desired value.
Rev. 0.92, 2007-10
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Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
4.1.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and
A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and
bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of
operations once the DLL reset is completed.
Rev. 0.92, 2007-10
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1-Gbit GDDR3
4.2
Extended Mode Register Set Command (EMRS1)
The Extended Mode Register is used to control multiple
operation modes of the device. The most important one is the
organization as a 1-CS or a 2-CS device. Furthermore, it is
used to set the output driver impedance value, the termination
impedance value, the Write Recovery time value for Write
with Autoprecharge. It is used as well to enable/disable the
DLL, to issue the Vendor ID. There is no default value for the
Extended Mode Register. Therefore it must be written after
power up to operate the GDDR3 Graphics RAM.The
Extended Mode Register can be programmed by performing
a normal Mode Register Set operation and setting the BA0 bit
to HIGH. All other bits of the EMR register are reserved and
should be set to LOW.The Extended Mode Register must be
loaded when all banks are idle and no burst are in progress.
The controller must wait the specified time tMRD before
initiating any subsequent operation (Figure 10). The timing of
the EMRS command operation is equivalent to the timing of
the MRS command operation.
To apply an EMRS command, CS0 has to be used.
FIGURE 8
Extended Mode Register Set Command
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
COD
BA0
1
BA1
0
BA2
Mode
COD: Code to be loaded into
the register
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Don't Care
20
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 9
Extended Mode Register Bitmap for Mid-Range-Speed Application
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There are two bitmaps for the Extended Mode Register. One bitmap shown in Figure 9 is supposed to support Mid-RangeSpeed applications. The other bitmap shown in Figure 10 is more focused on the high-range-speed application. Both bitmaps
distinguish different numbers in supported Write Recovery clock cycles. The mid-range bit map provides WR cycles from 4 to
11.The high-speed bitmap supports WR from 7 to 13.
Rev. 0.92, 2007-10
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 10
Extended Mode Register Bitmap for High-Speed Application
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Notes
option implemented in the device) or no action is taken by
the device (if option not implemented).
5. WR (write recovery time for auto precharge) in clock
cycles is calculated by dividing tWR (in ns) and rounding up
to the next integer (WR[cycles] = tWR[ns] / tCK[ns]). The
mode register must be programmed to this value.
1. These settings are for debugging purposes only.
2. Default termination values at Power Up.
3. The ODT disable function disables all terminators on the
device.
4. If the user activates bits in the extended mode register in
an optional field, either the optional field is activated (if
FIGURE 11
Extended Mode Register Set Timing
CLK#
CLK
Command
PA
NOP
EMRS
NOP
t RP
A.C.
t MRD
A.C.:
Any command
Don't Care
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
NOP
22
EMRS: Extended MRS command
PA:
PREALL command
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
4.2.1
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to
normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is enabled automatically).
Anytime the DLL is enabled, 1000 cycles must occur before a READ command can be issued.
4.2.2
WR
The WR parameter is programmed using the register bits A4, A5 and A7. This integer parameter defines as a number of clock
cycles the Write Recovery time in a Write with Autoprecharge operation.
The following inequality has to be complied with: WR * tCK ≥ tWR, where tCK is the clock cycle time. The high-speed bitmap
supports WR from 7 to 13. The mid-range bitmap provides WR cycles from 4 to 11.
4.2.3
Termination Rtt
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and
ZQ / 2 termination values. The termination may also be disabled for testing and other purposes. Data -, address - and command
- termination are disabled in parallel. The Termination Rtt are controlled independently from the Output Driver Impedance
values.
4.2.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance. When the
auto calibration is used, the output driver impedance is set nominally to ZQ / 6.
If the Output Driver Impedance is changed to 35, 40 or 45 Ohms the user needs to issue 16 AREF commands separated by
tRFC consecutively to make the change effective. The user must be aware that the Command bus needs to be stable for a time
of tKO after each AREF.
4.2.5
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits
A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the
Qimonda vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after tRIDon
following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a new EMRS
command is issued with A10 set back to 0. After tRIDoff following the second EMRS command, the data bus is driven back to
HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this requirement will
result in unspecified operation.
TABLE 9
Revision ID and Vendor Code
Revision Identification
Qimonda Vendor Code
DQ[7:4]
DQ[3:0]
0011
0010
Note: Please refer to Revision Release Note for Revision ID value.
Rev. 0.92, 2007-10
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 12
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
0
1
2
3
4
5
6
7
8
9
10
Com.
EMRS
N/D
N/D
N/D
N/D
N/D
EMRS
N/D
N/D
N/D
N/D
A[9:0],
A11
Add
CLK#
CLK
Add
A10
t
t
RIDon
RIDoff
RDQS
DQ[7:0]
Vendor Code and Revision ID
EMRS: Extended Mode Register Set Command
Add:
Address
N/D:
NOP or Deselect
Don't Care
4.2.6
Address command termination
The address and command termination is used to set the value of the internal termination resistors. The GDDR3 DRAM
supports ZQ / 4, ZQ / 2 and ZQ termination values. The mode register programming overwrites the programming during the
chip initialization.
4.2.7
Operation mode
The GDDR3 DRAM can be internally configured as two 512Mbit (2-CS mode) or one 1Gbit device (1-CS mode). The pins CS1
and A12 are only active in two, resp. 1-CS mode and act either as the chip select for the second rank, or the row-address for
the upper 4k-row-address range. If bit A2 from EMRS2 (“Merged Mode”) is set to 1 then the 2 operations mode will be inverted.
Note also that at 1000 MHz speed grade only 1-CS mode is supported.
TABLE 10
Operation Mode Function of defined Merged Mode
Operation Mode
Merged Mode = 0
Merged Mode = 1
0
one-CS
two-CS
1
two-CS
one-CS
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HYB18H1G321AF–10/11/14
1-Gbit GDDR3
4.3
Extended Mode Register 2 Set Command (EMRS2)
The Extended Mode Register 2 must be written after power
up to operate the GDDR3 Graphics RAM. The Extended
Mode Register 2 can be programmed by performing a normal
Mode Register Set operation and setting the BA1 bit to HIGH
and BA0, BA2 bits to LOW. All bits defined as RFU in the
bitmap are reserved and must be set to LOW. The Extended
Mode Register 2 must be loaded when all banks are idle and
no burst are in progress. The controller must wait the
specified time tMRD before initiating any subsequent
operation. The timing of the EMRS2 command operation is
equivalent to the timing of the MRS command operation.
FIGURE 13
Extended Mode Register 2 Set Command
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
COD
BA1
1
BA0,2
0
COD: Code to be loaded into
the register
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Don't Care
25
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 14
Extended Mode Register 2 Bitmap
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App Mode
The GDDR3 Graphics RAM provides two bitmaps for the Mode Register and the Extended Mode Register respectively. The
Bitmaps are shown in the MRS and EMRS chapters.
The Bit0 of the Extended Mode Regsiter 2 defines which one of the two bitmaps is active. There Bit0 set to LOW enables the
mid-range bitmap and Bit0 set to HIGH enables the High-Speed bitmap.
4.3.2
OCD Pull Down Offset
The 1G GDDR3 add the ability to add an offset to the Output impedance driver set using the bit A[1:0] of the EMRS. A range
from -3 to +3 can be chosen using A[11:9]. Each steps correspond to an approximate change of 1 Ohms. The offset will be
applied also on Autocal value if selected.
4.3.3
OCD Termination Pull Up Offset
The 1G GDDR3 add the ability to add an offset to the OCD Termination set using the bit A[3:2] of the EMRS. A range from -3
to +3 can be chosen using A[8:6]. Each steps correspond to an approximate change of 1.5 Ohms.
Rev. 0.92, 2007-10
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1-Gbit GDDR3
4.3.4
Merged Mode
"Merged Mode" as been added to the EMRS2 in order to merge the node A12/CS1 to a single ball (J-3) of the chip. Default
setting has both pins are using two different balls (J-2 and J-3).
4.3.5
Self Refresh
Self Refresh is used to control the timing of the refresh operation when the memory is in Self Refresh. When bit A1 is set to 0
then the refresh timing is controlled by the embedded Temperature Sensor. In this mode of operation if the temperature is
higher than 100°C then the refresh will happen every 8ms. If the temperature is below 100°C then the refresh will happen every
32 ms. If the A1 is set to 1 then the refresh timing will be independent from the temperature and fixed to 8 ms.
Rev. 0.92, 2007-10
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1-Gbit GDDR3
5
Electrical Characteristics
5.1
Absolute Maximum Ratings and Operation Conditions
TABLE 11
Absolute Maximum Ratings
Parameter
Symbol
VDD
VDDQ
VIN
VOUT
TSTG
TJ
IOUT
Power Supply Voltage
Power Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Storage Temperature
Junction Temperature
Short Circuit Output Current
Rating
Unit
Min.
Max.
-0.5
2.5
V
-0.5
2.5
V
-0.5
2.5
V
-0.5
2.5
V
-55
+150
°C
—
+125
°C
—
50
mA
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
5.2
DC Operation Conditions
5.2.1
Recommended Power & DC Operation Conditions
TABLE 12
Power & DC Operation Conditions (0 °C ≤ Tc ≤ 95 °C)
Parameter
Power Supply Voltage
Power Supply Voltage for I/O Buffer
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Symbol
Limit Values
VDD, VDDA
VDDQ
28
Unit
Min.
Typ.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
Note
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Parameter
Symbol
Reference Voltage
Output Low Voltage
Input leakage current
CLK Input leakage current
Limit Values
VREF
VOL(DC)
IIL
IILC
IOL
Unit
Note
1)
Min.
Typ.
Max.
0.69*VDDQ
—
0.71*VDDQ
V
—
—
0.8
V
–5.0
—
+5.0
μΑ
–5.0
—
+5.0
μΑ
2)
2)
Output leakage current
–5.0
—
+5.0
μΑ
1) VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise
on VREF may not exceed ±2% VREF (DC). Thus, from 70% of VDDQ, VREF is allowed ± 19mV for DC error and an additional ± 27mV for AC
noise.
2) IIL and IOL are measured with ODT disabled.
5.3
DC & AC Logic Input Levels
TABLE 13
DC & AC Logic Input Levels (0 °C ≤ Tc ≤ 95 °C)
Parameter
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logic low, DC, RESET pin
Input Logic High, DC, MF pin
Input Logic Low,DC, MF pin
Symbol
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
VIHR(DC)
VILR(DC)
VIHMF(DC)
VILMF(DC)
Limit Values
Unit
Note
Min.
Max.
VREF + 0.15
—
V
1)
—
VREF -0.15
V
1)
VREF + 0.25
—
V
2)3)
—
V
2)3)
VDD
VREF - 0.25
VDDQ + 0.3
0.35 × VDDQ
VDD + 0.3
–0.3
0
V
0.65 × VDDQ
-0.3
V
V
V
4)
1) The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to
maintain a valid level.
2) Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between
VIL(DC) and VIH(DC).
3) VIH overshoot: VIH(max) = VDDQ+0.5V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL
undershoot: VIL(min) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
4) The MF pin must be hard-wired on board to either VDD or VSS.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
29
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.4
Differential Clock DC and AC Levels
TABLE 14
Differential Clock DC and AC Input conditions (0 °C ≤ Tc ≤ 95 °C)
Parameter
Symbol
Limit Values
VMP(DC)
Clock Input Voltage Level, CLK and CLK
VIN(DC)
Clock DC Input Differential Voltage, CLK and CLK VID(DC)
Clock AC Input Differential Voltage, CLK and CLK VID(AC)
AC Differential Crossing Point Input Voltage
VIX(AC)
Clock Input Mid-Point Voltage, CLK and CLK
Unit
Note
Min.
Max.
0.7 × VDDQ – 0.10
0.7 × VDDQ + 0.10
V
1)
0.42
VDDQ + 0.3
VDDQ
VDDQ + 0.5
0.7 × VDDQ + 0.15
V
1)
V
1)
V
1)2)
V
1)3)
0.3
0.5
0.7 × VDDQ – 0.15
1) All voltages referenced to VSS.
2) VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3) The value of VIX is expected to equal 0.7 × VDDQ of the transmitting device and must track variations in the DC level of the same.
5.5
Output Test Conditions
FIGURE 15
Output Test Circuit
VDDQ
60 Ohm
DQ
DQS
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Test point
30
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.6
Pin Capacitances
TABLE 15
Pin Capacitances (VDDQ = 1.8 V, TA = 25°C, f = 1 MHz)
Parameter
Symbol
Min.
Max.
Unit
Input capacitance:
A0-A11,A12, , BA0-2, CKE, CS, CAS, RAS, WE, CKE,
RES,CLK,CLK
CI,CCK
1.0
2.5
pF
Input capacitance:
DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0-DM3
CIO
2.0
3.0
pF
5.7
Driver current characteristics
5.7.1
Driver IV characteristics at 40 Ohms
Note
Figure 16 represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature best and
worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two bounding curves. The value
of the external ZQ resistor is 240 Ω, setting the nominal driver output impedance to 40 Ω.
FIGURE 16
40 Ohm Driver Pull-Down and Pull-Up Characteristics
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3XOO'RZQ&KDUDFWHUVWLFV
,RXWP$
,RXWP$
9''49RXW9
9RXW9
Table 16 lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down and Pull-Up
IV characteristics.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
31
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
TABLE 16
Programmed Driver IV Characteristics at 40 Ohm
Voltage (V)
Pull-Down Current (mA)
Pull-Up Current (mA)
Minimum
Maximum
Minimum
Maximum
0.1
2.32
3.04
-2.44
-3.27
0.2
4.56
5.98
-4.79
-6.42
0.3
6.69
8.82
-7.03
-9.45
0.4
8.74
11.56
-9.18
-12.37
0.5
10.70
14.19
-11.23
-15.17
0.6
12.56
16.72
-13.17
-17.83
0.7
14.34
19.14
-15.01
-20.37
0.8
16.01
21.44
-16.74
-22.78
0.9
17.61
23.61
-18.37
-25.04
1.0
19.11
26.10
-19.90
-27.17
1.1
20.53
28.45
.21.34
-29.17
1.2
21.92
30.45
-22.72
-31.25
1.3
23.29
32.73
-24.07
-33.00
1.4
24.65
34.95
-25.40
-35.00
1.5
26.00
37.10
-26.73
-37.00
1.6
27.35
39.15
-28.06
-39.14
1.7
28.70
41.01
-29.37
-41.25
1.8
30.08
42.53
-30.66
-43.29
1.9
—
43.71
—
-45.23
2.0
—
44.89
—
-47.07
5.7.2
Termination IV Characteristic at 60 Ohms
Figure 17 represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best and worst case
conditions. The actual DQ termination Pull-Up current must lie between these two bounding curves. The value of the external
ZQ resistor is 240 Ω, setting the nominal DQ termination impedance to 60 Ω. (Extended Mode Register programmed to ZQ/4).
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
32
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 17
60 Ohm Active Termination Characteristic
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,RXWP$
9''49RXW9
Table 17 lists the numerical values of the minimum and maximum allowed values of the output driver termination IV
characteristic.
TABLE 17
Programmed Terminator Characteristics at 60 Ohm
Voltage (V)
Terminator Pull-Up Current (mA)
Minimum
Maximum
0.1
-1.63
-2.18
0.2
-3.19
0.3
0.4
Voltage (V)
Terminator Pull-Up Current (mA)
Minimum
Maximum
1.1
-14.23
-19.45
-4.28
1.2
-15.14
-20.83
-4.69
-6.30
1.3
-16.04
-22.00
-6.12
-8.25
1.4
-16.94
-23.33
0.5
-7.49
-10.11
1.5
-17.82
-24.67
0.6
-8.78
-11.89
1.6
-18.70
-26.09
0.7
-10.01
-13.58
1.7
-19.58
-27.50
0.8
-11.16
-15.19
1.8
-20.44
-28.86
0.9
-12.25
-16.69
1.9
—
-30.15
1.0
-13.27
-18.11
2.0
—
-31.38
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
33
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.8
Termination IV Characteristic at 120 Ohms
Figure 18 represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best
and worst case conditions. The actual termination Pull-Up current must lie between these two bounding curves. The value of
the external ZQ resistor is 240 Ω, setting the nominal termination impedance to 120 Ω. (Extended Mode Register programmed
to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during Power-Up for ADD/CMD terminations).
FIGURE 18
120 Ohm Active Termination Characteristic
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,RXWP$
9''49RXW9
Table 18 lists the numerical values of the minimum and maximum allowed values of the termination IV characteristic.
TABLE 18
Programmed Terminator Characteristics of 120 Ohm
Voltage (V)
Terminator Pull-Up Current (mA)
Minimum
Voltage (V)
Maximum
Terminator Pull-Up Current (mA)
Minimum
Maximum
0.1
-0.81
-1.09
1.1
-7.11
-9.72
0.2
-1.60
-2.14
1.2
-7.57
-10.42
0.3
-2.34
-3.15
1.3
-8.02
-11.00
0.4
-3.06
-4.12
1.4
-8.47
-11.67
0.5
-3.74
-5.06
1.5
-8.91
-12.33
0.6
-4.39
-5.94
1.6
-9.35
-13.05
0.7
-5.00
-6.79
1.7
-9.79
-13.75
0.8
-5.58
-7.59
1.8
-10.22
-14.43
0.9
-6.12
-8.35
1.9
—
-15.08
1.0
-6.63
-9.06
2.0
—
-15.69
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
34
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.9
Termination IV Characteristic at 240 Ohms
Figure 19 represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and
worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two bounding curves. The
value of the external ZQ resistor is 240 Ω, setting the nominal termination impedance to 240 Ω. (CKE = 1at the RES transition
during Power-Up for ADD/CMD terminations).
FIGURE 19
240 Ohm Active Termination Characteristic
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,RXWP$
9''49RXW9
Table 19 lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV
characteristic.
TABLE 19
Programmed Terminator Characteristics at 240 Ohm
Voltage (V)
Terminator Pull-Up Current (mA)
Minimum
Maximum
0.1
-0.41
-0.55
0.2
-0.80
-1.07
0.3
-1.17
0.4
0.5
Voltage (V)
Terminator Pull-Up Current (mA)
Minimum
Maximum
1.1
-3.56
-4.86
1.2
-3.79
-5.21
-1.58
1.3
-4.01
-5.50
-1.53
-2.06
1.4
-4.23
-5.83
-1.87
-2.53
1.5
-4.46
-6.17
0.6
-2.20
-2.97
1.6
-4.68
-6.52
0.7
-2.50
-3.40
1.7
-4.90
-6.88
0.8
-2.79
-3.80
1.8
-5.11
-7.21
0.9
-3.06
-4.17
1.9
—
-7.54
1.0
-3.32
-4.53
2.0
—
-7.85
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
35
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.10
Operating Currents
5.10.1
Operating Current Ratings for HYB18H1G321AF–
10/11/14
TABLE 20
Operating Current Ratings ( 0 °C ≤ Tc ≤ 95 °C)
Parameter
Symbol
Operating Current
Operating Current
Precharge Power-Down Standby Current
Precharge Floating Standby Current
Precharge Quiet Standby Current
Active Power-Down Standby Current
Active Standby Current
Operating Current Burst Read
Operating Current Burst Write
Auto-Refresh Current (tRC=min(tRFC))
Auto-Refresh Current at tREFI
Self Refresh Current
Operating Current
1-CS
2-CS
1)
2)
3)
4)
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
Limit Values
Note
-10
–11
–14
Typ.
Typ.
Typ.
375
350
300
mA
1) 2) 3)
390
370
310
mA
1)2)3)
240
220
180
mA
1)2)3)
300
275
230
μA
1)2)3)
275
250
215
μA
1)2)3)
240
220
180
μA
1)2)3)
380
360
310
mA
1)2)3)
510
470
395
mA
1)2)3)
540
495
415
mA
1)2)3)
570
550
450
mA
1)2)3)
300
280
235
mA
1)2)3)
10
10
10
mA
1)2)3)4)
520
500
420
mA
1)2)3)
NA
690
560
mA
1)2)3)
IDD specifications are tested after the device is properly initialized.
Input slew rate = 3V/ns.
Measured with Output open and On Die termination off.
Enables on-chip refresh and address counter.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Unit
36
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.11
Operating Current Measurement Conditions
TABLE 21
Operating Current Measurement Conditions
Symbol Parameter/Condition
IDD0
Operating Current - One bank, Activate - Precharge
tCK=min(tCK), tRC=min(tRC)
Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between valid
commands.
IDD1
Operating Current - One bank, Activate - Read - Precharge
One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are SWITCHING;
CS = HIGH between valid commands. Iout=0 mA
IDD2P
Precharge Power-Down Standby Current
All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE (HIGH).
IDD2F
Precharge Floating Standby Current
All banks idle; CS is HIGH, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING; Data bus input
are STABLE (HIGH).
IDD2Q
Precharge Quiet Standby Current
CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE (HIGH), Data
bus inputs are STABLE (HIGH).
IDD3P
Active Power-Down Standby Current
One bank active, CKE is LOW, Address and control inputs are STABLE (HIGH); Data bus inputs are STABLE
(HIGH); standard active power-down mode.
IDD3N
Active Standby Current
One bank active, CS is HIGH, CKE is HIGH, tRAS= tRAS,max, tCK=min(tCK); Address and control inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD4R
Operating Current - Burst Read
One bank active; Continuous read bursts, CL = CL(min); tCK=min(tCK); tRAS= tRAS,max; Address and control inputs
are SWITCHING; Iout = 0 mA.
IDD4W
Operating Current - Burst Write
One bank active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING; Data bus
inputs are SWITCHING.
IDD5B
Burst Auto Refresh Current
Refresh command at tRFC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid commands; Other
command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD5D
Distributed Auto Refresh Current
tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands; Other command
and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
37
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Symbol Parameter/Condition
IDD6
Self Refresh Current
CKE ≤ max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH); Data Bus
inputs are STABLE (HIGH).
IDD7
Operating Bank Interleave Read Current
1. 1-CS Mode: All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0 mA; Address
and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING.
2: 2-CS: All banks and all ranks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); tRRD_RR =
tRRD_RR(min); Iout=0 mA; Address and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are
SWITCHING.
Notes
1. 0 °C ≤ Tc ≤ 95 °C
2. Data Bus consists of DQ, DM, WDQS.
3. Definitions for IDD:
LOW is defined as VIN = 0.4 × VDDQ; HIGH is defined as VIN = VDDQ;
TABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals,
and inputs changing 50% of each data transfer for DQ signals.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
38
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.12
AC Timings for HYB18H1G321AF–10/11/14
TABLE 22
Timing Parameters (HYB18H1G321AF–10/11/14 )
Parameter
CAS
latency
Symbo
l
Limit Values
–10
–11
Unit
Note
-14
min
max
min
max
min
max
450
1000
—
—
—
—
MHz
1)
400
900
400
900
450
700
MHz
2)
—
—
—
—
—
—
MHz
2)
0.45
0.55
0.45
0.55
0.45
0.55
3)
0.45
0.55
0.45
0.55
0.45
0.55
0.45
—
0.45
—
0.45
—
tCK
tCK
tCK
Clock and Clock Enable
System frequency
CL = 12
CL =11
CL = 9
Clock high level width
Clock low level width
Minimum clock half period
fCK12
fCK11
fCK9
tCH
tCL
tHP
3)
3)4)
Command and Address Setup and Hold Timing
tIS
0.24
—
0.27
—
0.35
—
ns
Address/Command input hold time tIH
0.24
—
0.27
—
0.35
—
ns
0.7
—
0.7
—
0.7
—
tCK
3)
6
—
6
—
6
—
5)6)
12
—
12
—
12
—
tCK
tCK
tRC
tRAS
tRRD
37
—
35
—
34
—
23
—
22
—
22
—
9
—
8
—
7
—
tCK
tCK
tCK
ACT(a) to ACT(b) Command
period (different rank)
tRRD_RR
—
—
1
—
1
—
tCK
Row Precharge Time
tRP
tRCDRD
14
—
13
—
12
—
13
—
12
—
11
—
tCK
tCK
Row to Column Delay Time for
Writes
tRCDWR
tRCDWR(Min) = max(tRCDRD(Min) - (WL + 1) × tCK;2×tCK)
Four Active Windows within Rank
tFAW
36
—
35
—
35
—
tCK
CAS(a) to CAS(b) Command
period
tCCD
BL/2
—
BL/2
—
BL/2
—
tCK
8)
Internal write to Read Command
Delay
tWTR
7
—
6
—
6
—
tCK
9)
Address/Command input setup
time
Address/Command input pulse
width
tIPW
Mode Register Set Timing
tMRD
Mode Register Set to READ timing tMRDR
Mode Register Set cycle time
5)
Row Timing
Row Cycle Time
Row Active Time
ACT(a) to ACT(b) Command
period
Row to Column Delay Time for
Reads
7)
tCK
Column Timing
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
39
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Parameter
CAS
latency
Symbo
l
Limit Values
–10
min
–11
Unit
Note
-14
max
min
max
min
max
Internal write to Read Command
Delay (different rank)
tWTR_RR —
—
BL/2 – 1
—
BL/2 – 1
—
tCK
10)
Write to Write Command Delay
(different rank)
tWTW_RR —
—
BL/2
—
BL/2
—
tCK
11)
Read to Write command delay
tRTW
tRTR_RR
12)
—
tCK
tCK
Read to Read Command Delay
(different rank)
tRTW(min) = CL + BL/2+ 2 – WL
—
—
2
—
2
11)
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS
latching transition
tDQSS
WL–0.25 WL+0.25 WL–0.25 WL+0.25 WL–0.25 WL+0.25 tCK
Data-in and Data Mask to WDQS
Setup Time
tDS
0.14
—
0.15
—
0.18
—
ns
Data-in and Data Mask to WDQS
Hold Time
tDH
0.14
—
0.15
—
0.18
—
ns
Data-in and DM input pulse width
(each input)
tDIPW
0.40
—
0.40
—
0.40
—
tCK
DQS input low pulse width
tDQSL
tDQSH
tWPRE
tWPST
tWR
0.40
—
0.40
—
0.40
—
0.40
—
0.40
—
0.40
—
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
13
—
13
—
10
—
tCK
tCK
tCK
tCK
tCK
DQS input high pulse width
DQS Write Preamble Time
DQS Write Postamble Time
Write Recovery Time
9)
Read Cycle Timing Parameters for Data and Data Strobe
tAC
tRPRE
Read Preamble
Read Postamble
tRPST
Data-out high impedance time from tHZ
– 0.21
0.21
– 0.22
0.22
– 0.25
0.25
ns
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tCK
tACmin
tACmax
tACmin
tACmax
tACmin
tACmax
ns
Data-out low impedance time from tLZ
CLK
tACmin
tACmax
tACmin
tACmax
tACmin
tACmax
ns
tDQSCK
tDQSQ
–0.21
0.21
–0.22
0.22
–0.25
0.25
ns
—
0.120
—
0.130
—
0.160
ns
tQHS
tQH
—
0.120
—
0.130
—
0.160
ns
tREF
tREFI
—
Delay from AREF to next ACT/
AREF
tRFC
52.0
—
52.0
—
59
—
ns
Self Refresh Exit time
tXSC
1000
—
1000
—
1000
—
tCK
Data Access Time from Clock
CLK
DQS edge to Clock edge skew
DQS edge to output data edge
skew
Data hold skew factor
Data output hold time from DQS
tHP – tQHS
ns
Refresh/Power Down Timing
Refresh Period (8192 cycles)
Average periodic Auto Refresh
interval
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
32
—
3.9
32
3.9
40
—
32
3.9
ms
µs
3)
13)
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Parameter
CAS
latency
Power Down Exit time
Symbo
l
Limit Values
–10
–11
Unit
Note
-14
min
max
min
max
min
max
tXPN
7
—
7
—
8
—
tCK
tATS
tATH
tKO
10
—
10
—
10
—
ns
10
—
10
—
10
—
ns
10
—
10
—
10
—
ns
tRIDon
tRIDoff
—
20
—
20
—
20
ns
—
20
—
20
—
20
ns
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
Termination update Keep Out
timing
Rev. ID EMRS to DQ on timing
REV. ID EMRS to DQ off timing
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
At 1000 MHz speed grade only 1-CS mode is supported
DLL on mode
Timing is calculated for a clock frequency of 700 MHz
tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
This value of tMRD applies only to the case where the "DLL reset"’ bit is not activated.
tMRD is defined from MRS to any other command then READ.
tRAS,max is 8×tREFi
tCCD is either for gapless consecutive reads or gapless consecutive writes.
WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
This parameter is defined for commands issued to rank m following rank n where m ≠ n. For all other type of access, standard timing
parameters do apply.
12) Please round up tRTW to the next integer of tCK.
13) This parameter is defined per byte
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
41
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
6
Package
6.1
Package Outline
FIGURE 20
Package Outline PG-TFBGA-136-059
-!8
X "
!
X -!8
-!8
#
-).
-!8
#
’ › X
’ - # ! "
’ - #
# 3%!4).' 0,!.%
,EAD FREE SOLDER BALLS GREEN SOLDER BALLS
"AD UNIT MARKING "5- LIGHT GOOD
-IDDLE OF PACKAGES EDGES
0ACKAGE ORIENTATION MARK !
3"!FIDUCIAL SOLDER BALL ATTACH
"ARE CORE AREA
3OLDER BALL DIAMETER REFERS TO POST REFLOW CONDITIONS
Note: The package is conforming with JEDEC MO-207i, VAR DR-z.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
42
&0/?0'4&"'!??
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
6.2
Package Thermal Characteristics
TABLE 23
PG-TFBGA-136 Package Thermal Resistances
Theta_jA
Theta_jB
Theta_jC
JEDEC Board
1s0p
2s0p
Air Flow
0 m/s
1 m/s
3 m/s
0 m/s
1 m/s
3 m/s
-
-
K/W
40
32
27
22
19
17
5
2
Notes
1. Theta_jA: Junction to Ambient thermal resistance. The values have been obtained by simulation using the conditions stated
in the JEDEC JESD-51 standard.
2. Theta_jB: Junction to Board thermal resistance. The value has been obtained by simulation.
3. Theta_jC: Junction to Case thermal resistance. The value has been obtained by simulation.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
43
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Ballout 1Gbit GDDR3 Graphics RAM in 1-CS mode in non Merged Mode(Top View; MF = Low) . . . . . . . . . . . 5
Ballout 1Gbit GDDR3 Graphics RAM in 2-CS mode in non Merged Mode(Top View; MF = Low) . . . . . . . . . . . 6
Ballout 1Gbit GDDR3 Graphics RAM in Merged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Mode Register Set Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mode Register Bitmap for Mid-Range-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Mode Register Bitmap for High-Speed Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Extended Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Extended Mode Register Bitmap for Mid-Range-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Extended Mode Register Bitmap for High-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timing of Vendor Code and Revision ID Generation on DQ[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Extended Mode Register 2 Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Extended Mode Register 2 Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
40 Ohm Driver Pull-Down and Pull-Up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
120 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline PG-TFBGA-136-059 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
44
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ball Assignment with Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Function Truth Table II (CKE Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Scan Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision ID and Vendor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operation Mode Function of defined Merged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power & DC Operation Conditions (0 °C ≤ Tc ≤ 95 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC & AC Logic Input Levels (0 °C ≤ Tc ≤ 95 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Differential Clock DC and AC Input conditions (0 °C ≤ Tc ≤ 95 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin Capacitances (VDDQ = 1.8 V, TA = 25°C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programmed Driver IV Characteristics at 40 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Programmed Terminator Characteristics at 60 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programmed Terminator Characteristics of 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Programmed Terminator Characteristics at 240 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating Current Ratings ( 0 °C ≤ Tc ≤ 95 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timing Parameters (HYB18H1G321AF–10/11/14 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PG-TFBGA-136 Package Thermal Resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
45
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
2.3
2.3.1
2.4
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mirror Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Function Truth Table for more than one Activated Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Function Truth Table for CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
3.1
3.2
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disabling the scan feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Set Command (MRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Set Command (EMRS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DLL enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination Rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vendor Code and Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address command termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register 2 Set Command (EMRS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
App Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Pull Down Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Termination Pull Up Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Merged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
18
18
18
18
18
19
20
23
23
23
23
23
24
24
25
26
26
26
27
27
5
5.1
5.2
5.2.1
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.8
5.9
5.10
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings and Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Clock DC and AC Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver IV characteristics at 40 Ohms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
28
28
29
30
30
31
31
31
32
34
35
36
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
46
Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
5.10.1
5.11
5.12
Operating Current Ratings for HYB18H1G321AF–10/11/14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC Timings for HYB18H1G321AF–10/11/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6
6.1
6.2
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
47
Internet Data Sheet
Edition 2007-10
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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