QIMONDA HYB18T256161BF

June 2007
HYB18T256161BF–20/25/28
256-Mbit x16 DDR2 SDRAM
DDR2 SDRAM
RoHS compliant
Internet Data Sheet
Rev. 1.20
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
HYB18T256161BF–20/25/28
Revision History: 2007-06, Rev. 1.20
Page
Subjects (major changes since last revision)
All
Typos corrected
Previous Revision: Rev. 1.0, 2006-09
All
Final Data Sheet
Previous Revision: Rev. 0.60, 2006-09
94-101
added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; set up & hold timing
references ; derating values for input /command ,data )
82-86
setup & hold timings are changed with reference to Industrial standard definition
All
removed all the occurances of RDQS as it in not used in graphics (x16)
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
11232006-QP6X-6EM0
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Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family for graphics applications and
describes its main characteristics.
1.1
Features
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Data masks (DM) for write data
• 1.8 V ± 0.1V VDD for [–20/–25/–28]
• 1.8 V ± 0.1V VDDQ for [–20/–25/–28]
• Posted CAS by programmable additive latency for better
• DRAM organizations with 16 data in/outputs
command and data bus efficiency
• Double Data Rate architecture:
• Off-Chip-Driver impedance adjustment (OCD) and On– two data transfers per clock cycle
Die-Termination (ODT) for better signal quality.
– four internal banks for concurrent operation
• Auto-Precharge operation for read and write bursts
• Programmable CAS Latency: 3, 4, 5, 6, 7
• Auto-Refresh, Self-Refresh and power saving PowerDown modes
• Programmable Burst Length: 4 and 8
• Average Refresh Period 7.8 μs at a TCASE lower than 85°C,
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
3.9 μs between 85°C and 95°C
transmitted / received with data. Edge aligned with read
• Full Strength and reduced Strength (60%) Data-Output
Drivers
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• 1K page size
• Package: P-TFBGA-84
• DQS can be disabled for single-ended data strobe
operation
• RoHS Compliant Products1)
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
TABLE 1
Ordering Information for RoHS compliant products
Product Number
Org.
Clock (MHz)
Package
HYB18T256161BF–20/25/28
×16
500/400/350
P-TFBGA-84
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
The 256-Mb DDR2 DRAM is a high-speed Double-Data-Rate-Two CMOS Synchronous DRAM device containing 268,435,456
bits and internally configured as a quad bank DRAM. The 256-Mb device is organized as 4 Mbit × 16 I/O × 4 banks chip. These
synchronous devices achieve high speed transfer rates starting at 700 Mb/sec/pin for general applications.
The device is designed to comply with all DDR2 DRAM key features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched
at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or
differential DQS-DQS pair in a source synchronous fashion.
A 15-bit address bus is used to convey row, column and bank address information in a RAS-CAS multiplexing style.
An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.
The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
The DDR2 SDRAM is available in P-TFBGA package.
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256-Mbit Double-Data-Rate-Two SDRAM
2
Configuration
2.1
Chip Configuration
The chip configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 3 and Table 4 respectively. The ball numbering for the FBGA package is depicted in Figure 1.
TABLE 2
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball Type Buffer Type
Function
J8
CK
I
SSTL
K8
CK
I
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: CK and CK are differential system clock inputs. All
address and control inputs are sampled on the
crossing of the positive edge of CK and negative
edge of CK. Output (read) data is referenced to
the crossing of CK and CK (both direction of
crossing)
K2
CKE
I
SSTL
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates
internal clock signals and device input buffers and
output drivers. Taking CKE LOW provides
Precharge Power-Down and Self-Refresh
operation (all banks idle), or Active Power-Down
(row Active in any bank). CKE is synchronous for
power down entry and exit and for self-refresh
entry. Input buffers excluding CKE are disabled
during self-refresh. CKE is used asynchronously
to detect self-refresh exit condition. Self-refresh
termination itself is synchronous. After VREF has
become stable during power-on and initialisation
sequence, it must be maintained for proper
operation of the CKE receiver. For proper selfrefresh entry and exit, VREF must be maintained to
this input. CKE must be maintained HIGH
throughout read and write accesses. Input
buffers, excluding CK, CK, ODT and CKE are
disabled during power-down
Row Address Strobe (RAS), Column Address Strobe
(CAS), Write Enable (WE)
Clock Signals
Control Signals
K7
RAS
I
SSTL
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
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Chip Select
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Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball Type Buffer Type
Function
BA0
I
SSTL
Bank Address Bus 1:0
L3
BA1
I
SSTL
L1
NC
I
SSTL
M8
A0
I
SSTL
M3
A1
I
SSTL
M7
A2
I
SSTL
N2
A3
I
SSTL
N8
A4
I
SSTL
N3
A5
I
SSTL
Address Signals
L2
N7
A6
I
SSTL
P2
A7
I
SSTL
P8
A8
I
SSTL
P3
A9
I
SSTL
M2
A10
I
SSTL
AP
I
SSTL
P7
A11
I
SSTL
R2
A12
I
SSTL
G8
DQ0
I/O
SSTL
G2
DQ1
I/O
SSTL
H7
DQ2
I/O
SSTL
H3
DQ3
I/O
SSTL
H1
DQ4
I/O
SSTL
H9
DQ5
I/O
SSTL
F1
DQ6
I/O
SSTL
F9
DQ7
I/O
SSTL
C8
DQ8
I/O
SSTL
C2
DQ9
I/O
SSTL
D7
DQ10
I/O
SSTL
D3
DQ11
I/O
SSTL
D1
DQ12
I/O
SSTL
D9
DQ13
I/O
SSTL
B1
DQ14
I/O
SSTL
B9
DQ15
I/O
SSTL
Address Signal 12:0, Address Signal
10/Autoprecharge
Data Signals
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0]
Data Strobe
B7
UDQS
I/O
SSTL
A8
UDQS
I/O
SSTL
F7
LDQS
I/O
SSTL
E8
LDQS
I/O
SSTL
Data Strobe Upper Byte
Note: UDQS corresponds to the data on DQ[15:8]
Data Strobe Lower Byte
Note: LDQS corresponds to the data on DQ[7:0]
Data Mask
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256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball Type Buffer Type
Function
B3
UDM
I
SSTL
F3
LDM
I
SSTL
Data Mask Upper/Lower Byte
Note: LDM and UDM are the input mask signals and
control the lower or upper bytes.
VDDQ
VDD
VSSQ
VSS
PWR
–
I/O Driver Power Supply
PWR
–
Power Supply
PWR
–
I/O Driver Power Supply
PWR
–
Power Supply
VREF
VDDQ
VDDL
VDD
VSSQ
VSSDL
VSS
AI
–
I/O Reference Voltage
PWR
–
I/O Driver Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
I/O Driver Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
NC
NC
–
Not Connected
ODT
I
SSTL
On-Die Termination Control
Note: ODT is applied to each DQ, UDQS, UDQS,
LDQS, LDQS, UDM and LDM signal. An EMRS(1)
control bit enables or disables the ODT
functionality.
Power Supplies
A9,C1,C3,C7,C9
A1
A7,B2,B8,D2,D8
A3,E3
Power Supplies
J2
E9, G1, G3, G7, G9
J1
E1, J9, M9, R1
E7, F2, F8, H2, H8
J7
A3, E3,J3,N1,P9
Not Connected
A2, E2, R3, R7, R8, L1
Other Balls
K9
TABLE 3
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
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256-Mbit Double-Data-Rate-Two SDRAM
TABLE 4
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
FIGURE 1
Chip Configuration, PG-TFBGA-84 (top view)
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Notes
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,
and VSSQ are isolated on the device.
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
Rev. 1.20, 2007-06
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256-Mbit Double-Data-Rate-Two SDRAM
2.2
256 Mbit DDR2 Addressing
TABLE 5
DDR2 Addressing
Configuration
16Mb x 16
Bank Address
BA[1:0]
Number of Banks
4
Auto-Precharge
A10 / AP
Row Address
A[12:0]
Column Address
A[8:0]
Number of Column Address Bits
10
1)
Number of I/Os
16
2)
Page Size [Bytes]
1024 (1K)
3)
1) Refered to as ’colbits’
2) Refered to as ’org’
3) PageSize = 2colbits × org/8 [Bytes]
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Note
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
3
Functional Description
%
$
$
%
$
$
$
$
$
$
$
$
$
$
$
$
$
3
'
:
5 '
/
/
7
0 &
/ %
7 %
/
U
H
J
D
G
G
U Z
Z Z
Z Z Z Z
TABLE 6
Mode Register Definition (BA[1:0] = 00B)
Field
Bits
Type1)
Description
BA1
14
reg. addr.
Bank Address [1]
BA1 Bank Address
0B
BA0
13
PD
12
w
Active Power-Down Mode Select
PD Fast exit
0B
1B
PD Slow exit
WR
[11:9]
w
Write Recovery2)
Note: All other bit combinations are illegal.
Bank Address [0]
0B
BA0 Bank Address
001B
010B
011B
100B
101B
WR 2
WR 3
WR 4
WR 5
WR 6
DLL
8
w
DLL Reset
DLL No
0B
1B
DLL Yes
TM
7
w
Test Mode
0B
TM Normal Mode
1B
TM Vendor specific test mode
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
011B
100B
101B
110B
111B
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11232006-QP6X-6EM0
CL 3
CL 4
CL 5
CL 6
CL 7
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256-Mbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
BT
3
w
Burst Type
0B
BT Sequential
BT Interleaved
1B
BL
[2:0]
w
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
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$
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$
$
$
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2
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3
U
R
J
U
D
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4
6
5
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5
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R
I
I
W
W
W
W
U
H
J
D
G
G
U
Z
Z
Z
Z
Z
Z
Z
TABLE 7
Extended Mode Register Definition (BA[1:0] = 01B)
1)
Field
Bits
Type
Description
BA1
14
reg. addr.
BA0
13
Qoff
12
w
Output Disable
0B
QOff Output buffers enabled
1B
QOff Output buffers disabled
A11
11
w
Address Bus [11]
A11 Address bit 11
0B
DQS
10
w
Complement Data Strobe (DQS Output)
0B
DQS Enable
DQS Disable
1B
Bank Address [1]
BA1 Bank Address
0B
Bank Address [0]
1B
BA0 Bank Address
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256-Mbit Double-Data-Rate-Two SDRAM
Type1)
Description
OCD
[9:7]
Program
w
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
w
Additive Latency
Note: All other bit combinations are illegal.
Field
Bits
[5:3]
000B
001B
010B
011B
100B
101B
110B
RTT
6,2
w
AL 0
AL 1
AL 2
AL 3
AL 4
AL 5
AL 6
Nominal Termination Resistance of ODT
Note: See Table 18 “ODT DC Electrical Characteristics” on Page 20
00B
01B
10B
11B
RTT ∞ (ODT disabled)
RTT 75 Ohm
RTT 150 Ohm
RTT 50 Ohm
DIC
1
w
Off-chip Driver Impedance Control
0B
DIC Full (Driver Size = 100%)
1B
DIC Reduced
DLL
0
w
DLL Enable
DLL Enable
0B
1B
DLL Disable
1) w = write only register bits
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256-Mbit Double-Data-Rate-Two SDRAM
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256-Mbit Double-Data-Rate-Two SDRAM
%$
%$
$
$
$
$
$
$
65)
$
$
$
$
$
$
$
3$65
UHJDGGU
TABLE 8
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B)
Field
Bits
Type1)
BA1
14
reg. addr., Bank Address [1]
BA1 Bank Address
1B
BA0
13
Bank Address [0]
0B
BA0 Bank Address
A
[12:8]
w
Address Bus
A Address bits
00000B
SRF
7
w
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
A7 disable
1B
A7 enable 2)
A
[6:3]
w
Address Bus
0000B A Address bits
Description
Partial Self Refresh for 4 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 4 Banks3)
000B PASR0 Full Array
001B PASR1 Half Array (BA[1:0]=00, 01)
010B PASR2 Quarter Array (BA[1:0]=00)
011B PASR3 Not defined
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5 Half array (BA[1:0]=10, 11)
110B PASR6 Quarter array (BA[1:0]=11)
111B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase £ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
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256-Mbit Double-Data-Rate-Two SDRAM
%
$
%
$
$
$
$
$
$
$
$
$
$
$
$
$
$
U
H
J
D
G
G
U
03%7
TABLE 9
EMR(3) Programming Extended Mode Register Definition( BA[1:0]=11B)
Field
Bits
Type1)
Description
BA1
14
reg.addr
Bank Adress
BA1 Bank Address
1B
BA0
13
A
[12:0]
Bank Adress
1B
BA0 Bank Address
w
Address Bus
0000000000000B Address bits
1) w = write only
TABLE 10
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
DQ[7:0]
X
DQ[15:8]
X
LDQS
X
LDQS
0
UDQS
X
UDQS
0
LDM
X
UDM
X
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
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EMRS(1) Address Bit A11
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256-Mbit Double-Data-Rate-Two SDRAM
TABLE 11
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
×00
0, 1, 2, 3
0, 1, 2, 3
×01
1, 2, 3, 0
1, 0, 3, 2
×1 0
2, 3, 0, 1
2, 3, 0, 1
×1 1
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
8
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Notes
2. Order of burst access for sequential addressing is “nibblebased” and therefore different from SDR or DDR
components
1. Page Size and Length is a function of I/O
organization:Page size for all 256 Mbit components is 1
KByte
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256-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
TABLE 12
Command Truth Table
Function
CKE
CS RAS
CAS WE BA0 A[12:11] A10 A[9:0]
BA1
Note1)2)3)
4)5)
Previous Current
Cycle
Cycle
(Extended) Mode Register Set H
H
L
L
L
L
BA
OP Code
Auto-Refresh
H
H
L
L
L
H
X
X
X
X
4)
Self-Refresh Entry
H
L
L
L
L
H
X
X
X
X
4)6)
Self-Refresh Exit
L
H
H
X
X
X
X
X
X
X
4)6)7)
L
H
H
H
Single Bank Precharge
H
H
L
L
H
L
BA
X
L
X
4)5)
Precharge all Banks
H
H
L
L
H
L
X
X
H
X
4)
Bank Activate
H
H
L
L
H
H
BA
Row Address
Write
H
H
L
H
L
L
BA
Column
L
Column
4)5)8)
Write with Auto-Precharge
H
H
L
H
L
L
BA
Column
H
Column
4)5)8)
Read
H
H
L
H
L
H
BA
Column
L
Column
4)5)8)
Read with Auto-Precharge
H
H
L
H
L
H
BA
Column
H
Column
4)5)8)
No Operation
H
X
L
H
H
H
X
X
X
X
4)
Device Deselect
H
X
H
X
X
X
X
X
X
X
4)
Power Down Entry
H
L
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
Power Down Exit
L
H
4)5)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
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TABLE 13
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1)
CKE
Previous Cycle6) Current Cycle6)
(N-1)
(N)
Command (N)2)3)RAS, Action (N)2)
CAS, WE, CS
Note4)5)
L
L
X
Maintain Power-Down
7)8)11)
L
H
DESELECT or NOP
Power-Down Exit
7)9)10)11)
L
L
X
Maintain Self Refresh
8)11)12)
L
H
DESELECT or NOP
Self Refresh Exit
9)12)13)14)
Bank(s)Active
H
L
DESELECT or NOP
Active Power-Down Entry
7)9)10)11)15)
All Banks Idle
H
L
DESELECT or NOP
Precharge Power-Down Entry
9)10)11)15)
H
L
AUTOREFRESH
Self Refresh Entry
7)11)14)16)
Any State other
H
than listed above
H
Refer to the Command Truth Table
Power-Down
Self Refresh
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
16)
17)
17)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
CKE must be maintained HIGH while the device is in OCD calibration mode.
Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
“X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2×tCKE + tIH.
VREF must be maintained during Self Refresh operation.
On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after tXSRD (200 clocks) is satisfied.
Valid commands for Self Refresh Exit are NOP and DESELCT only.
Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
Self Refresh mode can only be entered from the All Banks Idle state.
Must be a legal command as defined in the Command Truth Table.
TABLE 14
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data; provided coincident with the corresponding data.
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256-Mbit Double-Data-Rate-Two SDRAM
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 18 at any time.
TABLE 15
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5
+2.3
V
1)
Junction Temperature
–
+125
°C
1)
Storage Temperature
–55
+150
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
°C
1)2)
VDD
VDDQ
VDDL
VIN, VOUT
TJ
TSTG
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 16
DRAM Component Operating Temperature Range
Symbol
TCASE
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 μs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
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256-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
TABLE 17
Recommended DC Operating Conditions (SSTL_18)
Symbol
VDD
VDDDL
VDDQ
VREF
VTT
Parameter
Rating
Unit
Notes
Min.
Typ.
Max.
Supply Voltage
1.7
1.8
1.9
V
1)2)
Supply Voltage for DLL
1.7
1.8
1.9
V
1)2)
Supply Voltage for Output
1.7
1.8
1.9
V
1)2)
Input Reference Voltage
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
3)4)
Termination Voltage
VREF – 0.04
VREF
VREF + 0.04
V
5)
1) HYB18T256161BF–20/25/28
2) VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
3) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
4) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in die dc level of VREF.
TABLE 18
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom.
Max.
Unit
Note
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Rtt1(eff)
60
75
90
Ω
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
120
150
180
Ω
1)
Deviation of VM with respect to VDDQ / 2
delta VM
–6.00
—
+ 6.00
%
2)
1)
Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –
1) x 100%
TABLE 19
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Notes
IIL
Input Leakage Current; any input 0 V < VIN < VDD
–2
+2
μA
1)
IOL
Output Leakage Current; 0 V < VOUT < VDDQ
–5
+5
μA
2)
1) all other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS are disabled and ODT is turned off
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256-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS signals are internally disabled and
don’t care.
TABLE 20
DC & AC Logic Input Levels
Symbol
Parameter
Min.
Max.
Units
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
VREF + 0.125
V
DC input low
–0.3
VDDQ + 0.3
VREF – 0.125
AC input logic high
VREF + 0.250
—
V
AC input low
—
VREF – 0.250
V
V
TABLE 21
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Notes
VREF
VSWING.MAX
Input reference voltage
0.5 x VDDQ
V
1)
Input signal maximum peak to peak swing
1.0
V
1)
SLEW
Input signal minimum Slew Rate
1.0
V / ns
2)3)
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to
VIL(ac).MAX for falling edges as shown in Figure 2
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative
transitions.
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256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 2
Single-ended AC Input Test Conditions Diagram
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8
62%& 6),DCMAX 6),ACMAX 633
DELTA4&
DELTA42
MIN 62%
6
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W )( A C DELTA42
62%
&
6),A CMAX
&ALLIN
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DELTA4&
TABLE 22
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
Min.
Max.
Unit
Notes
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
DC input signal voltage
–0.3
—
1)
DC differential input voltage
0.25
—
2)
AC differential input voltage
0.5
V
3)
AC differential cross point input voltage
0.5 × VDDQ – 0.175
V
4)
AC differential cross point output voltage
0.5 × VDDQ – 0.125
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
5)
1)
2)
3)
4)
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc).
VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac).
The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
FIGURE 3
Differential DC and AC Input and Output Logic Levels Diagram
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256-Mbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
TABLE 23
Full Strength Calibrated Pull-up Driver Characteristics
Voltage (V)
Calibrated Pull-up Driver Current [mA]
Nominal(18
Nominal Minimum1) Nominal
(21 Ohms)
Low2)(18.75 Ohms) ohms)3)
Nominal
High2)(17.25
Ohms)
Nominal
Maximum4) (15
Ohms)
0.2
–9.5
–10.7
–11.4
–11.8
–13.3
0.3
–14.3
–16.0
–16.5
–17.4
–20.0
0.4
–18.3
–21.0
–21.2
–23.0
–27.0
1)
2)
3)
4)
The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8 V, any process
The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
TABLE 24
Full Strength Calibrated Pull-down Driver Characteristics
Voltage (V)
Calibrated Pull-down Driver Current [mA]
Nominal Minimum1)
(21 Ohms)
Nominal
Low2)(18.75
Ohms)
Nominal3)(18
ohms)
Nominal
High2)(17.25
Ohms)
Nominal
Maximum4) (15
Ohms)
0.2
9.5
10.7
11.5
11.8
13.3
0.3
14.3
16.0
16.6
17.4
20.0
0.4
18.7
21.0
21.6
23.0
27.0
1)
2)
3)
4)
The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8V, any process
The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
Rev. 1.20, 2007-06
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256-Mbit Double-Data-Rate-Two SDRAM
5.5
Input / Output Capacitance
TABLE 25
Input / Output Capacitance
Symbol
Parameter
Min.
Max.
Unit
CCK
Input capacitance, CK and CK
1.0
2.0
pF
CDCK
Input capacitance delta, CK and CK
—
0.25
pF
CI
Input capacitance, all other input-only pins
1.0
1.75
pF
CDI
Input capacitance delta, all other input-only pins
—
0.25
pF
CIO
Input/output capacitance,
DQ, DM, DQS, DQS
2.5
3.5
pF
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS
—
0.5
pF
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256-Mbit Double-Data-Rate-Two SDRAM
5.6
Overshoot and Undershoot Specification
TABLE 26
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
–20
–25
–28
Unit
Maximum peak amplitude allowed for overshoot area
0.5
0.5
0.5
V
Maximum peak amplitude allowed for undershoot area
0.5
0.5
0.5
V
Maximum overshoot area above VDD
0.80
0.80
0.80
V.ns
Maximum undershoot area below VSS
0.80
0.80
0.80
V.ns
FIGURE 4
AC Overshoot / Undershoot Diagram for Address and Control Pins
6OLTS6
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UM!M
PLITUDE
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OOT!R E
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UM!M
PLITUDE
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5NDERS HOOT!
RE
A
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256-Mbit Double-Data-Rate-Two SDRAM
TABLE 27
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
–20
–25
–28
Unit
Maximum peak amplitude allowed for overshoot area
0.9
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area
0.9
0.9
0.9
V
Maximum overshoot area above VDDQ
0.23
0.23
0.23
V.ns
Maximum undershoot area below VSSQ
0.23
0.23
0.23
V.ns
FIGURE 5
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
6OLTS 6 -AXIM
UM!M
PLITUDE
/VE
RSH
OOT!R E
A
6$$
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633
1
-AXIM
UM!M
PLITUDE
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HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
5.7
AC Characteristics
5.7.1
Speed Grade Definitions
TABLE 28
Speed Grade Definition
Speed Grade
Symbol
Parameter
Clock
Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
@ CL = 7
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tCK
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
–20
–25
–28
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
5
8
5
8
5
8
ns
1)2)3)4)
3.75
8
3.75
8
3.75
8
ns
1)2)3)4)
3
8
3
8
3
8
ns
1)2)3)4)
2.5
8
2.5
8
2.8
8
ns
1)2)3)4)
2.0
8
—
—
—
—
ns
1)2)3)4)
45
70k
45
70k
45
70k
ns
1)2)3)4)5)
60
—
60
—
60
—
ns
1)2)3)4)
15
—
15
—
15
—
ns
1)2)3)4)
15
—
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8Timings
are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” according
to Chapter 7.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 7.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT. See Chapter 7.1 for the reference load for timing measurements.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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256-Mbit Double-Data-Rate-Two SDRAM
5.7.2
AC Timing Parameters
List of Timing Parameters
TABLE 29
DQ output access time from CK tAC
/ CK
–20
–25
Notes1)
–28
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Parameter
Symbol
Timing Parameter by Speed Grade
–450
+450
–500
+500
–550
+550
ps
CAS A to CAS B command
period
tCCD
2
—
2
—
2
—
tCK
CK, CK high-level width
tCH
tCKE
0.45
0.55
0.45
0.55
0.45
0.55
3
—
3
—
3
—
tCK
tCK
tCL
Auto-Precharge write recovery tDAL
0.45
0.55
0.45
0.55
0.45
0.55
CKE minimum high and low
pulse width
CK, CK low-level width
+ precharge time
WR + tRP —
WR + tRP —
WR + tRP —
tCK
tCK
2)3)4)5)6)
7)18)
Minimum time clocks remain
ON after CKE asynchronously
drops LOW
tDELAY
tIS + tCK + ––
tIH
tIS + tCK + ––
tIH
tIS + tCK + ––
tIH
ns
8)
DQ and DM input hold time
(differential data strobe)
tDH
145
––
250
––
275
––
ps
9)
DQ and DM input hold time
(single ended data strobe)
tDH1
-105
––
0
––
25
––
ps
9)
DQ and DM input pulse width
(each input)
tDIPW
0.35
—
0.35
—
0.35
—
tCK
DQS output access time from
CK / CK
tDQSCK –450
+450
–500
+500
–550
+550
ps
DQS input low (high) pulse
width (write cycle)
tDQSL,H 0.35
—
0.35
—
0.35
—
tCK
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
—
450
—
450
—
450
ps
Write command to 1st DQS
latching transition
tDQSS
WL –
0.25
WL +
0.25
WL –
0.25
WL +
0.25
WL –
0.25
WL +
0.25
tCK
DQ and DM input setup time
(differential data strobe)
tDS
20
125
––
150
––
ps
9)
DQ and DM input setup time
(single ended data strobe)
tDS1
-105
0
––
25
––
ps
9)
DQS falling edge hold time
from CK (write cycle)
tDSH
0.2
—
0.2
—
0.2
—
tCK
DQS falling edge to CK setup
time (write cycle)
tDSS
0.2
—
0.2
—
0.2
—
tCK
Clock half period
tHP
MIN. (tCL,
tCH)
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
MIN. (tCL,
tCH)
28
MIN. (tCL,
tCH)
9)
10)
11)
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
–20
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Data-out high-impedance time
from CK / CK
Notes1)
Symbol
Parameter
tHZ
—
tAC.MAX
—
tAC.MAX
—
tAC.MAX
ps
575
—
625
—
ps
0.6
—
0.6
—
tCK
—
500
—
ps
–25
–28
2)3)4)5)6)
12)
Address and control input hold tIH
time
525
Address and control input pulse tIPW
width
(each input)
0.6
Address and control input setup tIS
time
400
450
2 × tAC.MIN tAC.MAX
2 × tAC.MIN tAC.MAX
2 × tAC.MIN tAC.MAX
ps
12)
tAC.MAX
tAC.MIN
tAC.MAX
tAC.MIN
tAC.MAX
ps
12)
DQ low-impedance time from
CK / CK
tLZ(DQ)
DQS low-impedance from CK / tLZ(DQS) tAC.MIN
CK
—
Mode register set command
cycle time
tMRD
2
—
2
—
2
—
tCK
OCD drive mode output delay
tOIT
tQH
0
12
0
12
0
12
ns
tHP–tQHS
—
tHP–tQHS
—
tHP–tQHS
—
tQHS
tREFI
—
600
—
600
—
600
ps
—
7.8
—
7.8
—
7.8
μs
13)14)
—
3.9
—
3.9
—
3.9
μs
13)15)
75
—
75
—
75
—
ns
16)
0.9
1.1
0.9
1.1
0.9
1.1
12)
0.40
0.60
0.40
0.60
0.40
0.60
tCK
tCK
7.5
—
7.5
—
7.5
—
ns
14)17)
—
7.5
—
7.5
—
ns
Data output hold time from
DQS
Data hold skew factor
Average periodic refresh
Interval
Auto-Refresh to Active/AutoRefresh command period
tRFC
tRPRE
Read postamble
tRPST
Active bank A to Active bank B tRRD
Read preamble
12)
command period
Internal Read to Precharge
command delay
tRTP
7.5
Write preamble
tWPRE
tWPST
tWR
0.35 x tCK —
0.35 x tCK —
0.35 x tCK —
0.40
0.60
0.40
0.60
0.40
0.60
tCK
tCK
13
—
15
—
15
—
ns
Write recovery time for write
with Auto-Precharge
WR
tWR/tCK
Internal Write to Read
command delay
tWTR
7.5
—
7.5
—
7.5
Exit power down to any valid
command
(other than NOP or Deselect)
tXARD
2
—
2
—
Exit active power-down mode
to Read command (slow exit,
lower power)
tXARDS
10 – AL
—
8 – AL
—
Write postamble
Write recovery time for write
without Auto-Precharge
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11232006-QP6X-6EM0
tWR/tCK
29
17)
tCK
18)
—
ns
19)
2
—
tCK
20)
7 – AL
—
tCK
20)
tWR/tCK
Internet Data Sheet
Exit Self-Refresh to Read
command
1) VDDQ, VDD refer to Chapter 1.
–25
Notes1)
–28
Min.
Max.
Min.
Max.
Min.
Max.
2
—
2
—
2
—
tCK
tXSNR
tRFC +10
—
tRFC +10
—
tRFC +10
—
ns
tXSRD
200
—
200
—
200
—
tCK
Exit precharge power-down to tXP
any valid command (other than
NOP or Deselect)
Exit Self-Refresh to non-Read
command
–20
Unit
Parameter
Symbol
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
2)3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this
data sheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 5.3 of this data sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change
during power-down, a specific procedure is required.
9) Timing is referenced to Industrial standard definition
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C ≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
18) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
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Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
5.7.3
ODT AC Electrical Characteristics
TABLE 30
ODT AC Characteristics and Operating Conditions for all bins
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
nCK
1)
ODT turn-on
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
1)2)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT turn-off delay
2.5
2.5
nCK
1)
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
1)3)
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT to Power Down Mode Entry Latency
3
—
nCK
nCK
1)
1)
ODT Power Down Exit Latency
8
—
1) Unit “tCK.AVG” represents the actual tCK.AVG of the input clock under operation. Unit “nCK” represents one clock cycle of the input clock,
counting the actual clock edges. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. tAOND is 2 clock cycles after the
clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. If tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after
the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
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Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
6
Specifications and Conditions
TABLE 31
IDD Measurement Conditions
Parameter
Symbol
Note
Operating Current - One bank Active - Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.
Address and control inputs are switching; Databus inputs are switching.
IDD0
1)2)3)4)5)6)
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL =
CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are
switching; Databus inputs are switching.
IDD1
1)2)3)4)5)6)
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs
are floating.
1)2)3)4)5)6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching,
Data bus inputs are switching.
1)2)3)4)5)6)
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable,
Data bus inputs are floating.
1)2)3)4)5)6)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus
inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
IDD3P(0)
1)2)3)4)5)6)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus
inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
IDD3P(1)
1)2)3)4)5)6)
Active Standby Current
IDD3N
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
1)2)3)4)5)6)
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS
= tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching; IOUT = 0 mA.
1)2)3)4)5)6)
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS
= tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
1)2)3)4)5)6)
Burst Refresh Current
IDD5B
tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5)6)
Distributed Refresh Current
IDD5D
tCK = tCK(IDD), Refresh command every tREFI = 7.8 μs interval, CKE is LOW and CS is HIGH between
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5)6)
Rev. 1.20, 2007-06
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32
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
1)2)3)4)5)6)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
1)2)3)4)5)6)7)
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK =
tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address
bus inputs are stable during deselects; Data bus is switching.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
4)
5)
6)
7)
Note
Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS.
Definitions for IDD: see Table 32
Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..
A = Activate, RA = Read with Auto-Precharge, D=DESELECT
TABLE 32
Definition for IDD
Parameter
Description
LOW
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
defined as inputs are stable at a HIGH or LOW level
FLOATING
defined as inputs are VREF = VDDQ / 2
SWITCHING
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
TABLE 33
IDD Specification
Speed Grade
–20
–25
-28
Symbol
typ.
typ.
typ.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
92
81
77
mA
99
89
85
mA
4
4
4
mA
46
41
38
mA
40
38
35
mA
30
28
27
mA
1)
5
5
5
mA
2)
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
Unit
52
47
43
mA
166
153
145
mA
189
163
149
mA
127
119
115
mA
5
5
5
mA
33
Note
3)
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Speed Grade
–20
–25
-28
Symbol
typ.
typ.
typ.
IDD6
IDD7
4
4
204
193
1) MRS(12)=0
2) MRS(12)=1
3) 0 ≤ TCASE ≤ 85°C
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
34
Unit
Note
4
mA
3)
193
mA
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
7
Package
7.1
Package Dimension
FIGURE 6
Package Outline P-TFBGA-84
[
-!8
"
!
[
-!8
-!8
#
-!8
-).
#
’ ›
X
’- !"
#
’-
$UMMYPADSWITHOUTBALL
-IDDLEOFPACKAGESEDGES
0ACKAGEORIENTATIONMARK!
"ADUNITMARKING"5-
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
35
4).'0,!.%
#3%!
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
7.2
Package Thermal Characteristics
TABLE 34
Package thermal characteristics
1)
JESD51
JEDEC Board
Theta_jC2)
Theta_jA
1s0p
2s0p
Air Flow
0 m/s
1 m/s
3 m/s
0 m/s
1 m/s
3 m/s
Rth[K/W]
69
53
47
41
35
33
5
1) Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the Industrial standard.
2) Junction to Case thermal resistance. The value has been obtained by simulation.
Rev. 1.20, 2007-06
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36
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Chip Configuration, PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline P-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
37
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Extended Mode Register Definition (BA[1:0] = 01B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
EMR(3) Programming Extended Mode Register Definition( BA[1:0]=11B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Full Strength Calibrated Pull-up Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 26
Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Timing Parameter by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ODT AC Characteristics and Operating Conditions for all bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
38
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
256 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.7.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
7.1
7.2
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
19
19
20
21
23
24
25
27
27
28
31
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
39
Internet Data Sheet
Edition 2007-06
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in
1. Any applications that are intended for military usage (including but not limited to weaponry), or
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining
or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if
a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or
(ii) Cause the failure of such Critical Systems; or
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to
property, whether tangible or intangible).
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