Preliminary FM28V020 256Kbit Bytewide F-RAM Memory Features 256Kbit Ferroelectric Nonvolatile RAM • Organized as 32Kx8 • 1014 Read/Write Cycles • NoDelay™ Writes • Page Mode Operation to 33MHz • Advanced High-Reliability Ferroelectric Process Superior to Battery-backed SRAM Modules • No battery concerns • Monolithic reliability • True surface mount solution, no rework steps • Superior for moisture, shock, and vibration • Resistant to negative voltage undershoots General Description The FM28V020 is a 32K x 8 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and virtually unlimited write endurance make F-RAM superior to other types of memory. SRAM Replacement • JEDEC 32Kx8 SRAM pinout • 60 ns Access Time, 90 ns Cycle Time Low Power Operation • 2.0V – 3.6V Power Supply • Standby Current 90 µA (typ) • Active Current 7 mA (typ) Industry Standard Configurations • Industrial Temperature -40° C to +85° C • 28-pin “Green”/RoHS SOIC (-SG) • 32-pin “Green”/RoHS TSOP (-TG) Pin Configuration NC OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP-I 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 NC In-system operation of the FM28V020 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. Read and write cycles may be triggered by /CE or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM28V020 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. Device specifications are guaranteed over the industrial temperature range -40°C to +85°C. Ordering Information 28-pin “Green”/RoHS SOIC 28-pin “Green”/RoHS SOIC, Tape & Reel FM28V020-TG 32-pin “Green”/RoHS TSOP FM28V020-TGTR 32-pin “Green”/RoHS TSOP, Tape & Reel FM28V020-SG FM28V020-SGTR This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.1 Sept. 2009 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Page 1 of 14 FM28V020 - 32Kx8 FRAM A(14:3) Row Decoder Address Latch A(14:0) 4K x 64 F-RAM Array A(2:0) ... Column Decoder CE WE Control Logic OE I/O Latch & Bus Driver DQ(7:0) Figure 1. Block Diagram Pin Descriptions Pin Name Type A(14:0) Input /CE Input /WE Input /OE Input DQ(7:0) VDD VSS Rev. 1.1 Sept. 2009 I/O Supply Supply Pin Description Address inputs: The 15 address lines select one of 32,768 bytes in the F-RAM array. The address value is latched on the falling edge of /CE. Addresses A(2:0) are used for page mode read and write operations. Chip Enable input: The device is selected and a new memory access begins on the falling edge of /CE. The entire address is latched internally at this point. Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM28V020 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE latches a new column address for fast page mode write cycles. Output Enable: When /OE is low, the FM28V020 drives the data bus when valid data is available. Deasserting /OE high tri-states the DQ pins. Data: 8-bit bi-directional data bus for accessing the F-RAM array. Supply Voltage Ground Page 2 of 14 FM28V020 - 32Kx8 FRAM Functional Truth Table /CE /WE H X H ↓ L H L H L ↓ L ↓ L ↓ X ↑ Notes: 1) 2) 3) 4) Rev. 1.1 Sept. 2009 A(14:3) X V No Change Change V V No Change X A(2:0) X V Change V V V V X Operation Standby/Idle Read Page Mode Read Random Read /CE-Controlled Write 2 /WE-Controlled Write 2, 3 Page Mode Write 4 Starts Precharge H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care. For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first. /WE-controlled write cycle begins as a Read cycle and A(14:3) is latched then. Addresses A(2:0) must remain stable for at least 15 ns during page mode operation. Page 3 of 14 FM28V020 - 32Kx8 FRAM Overview The FM28V020 is a bytewide F-RAM memory logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a different page is triggered by toggling the chip enable pin or simply by changing the upper address A(14:3). Memory Operation Users access 32,768 memory locations with 8 data bits each through a parallel interface. The F-RAM array is organized as 8 blocks each having 512 rows. Each row has 8 column locations, which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE, subsequent column locations may be accessed without the need to toggle the chip enable. When either chip enable pin is deasserted, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. Read Operation A read operation begins on the falling edge of /CE. The /CE-initiated access causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the access time has been satisfied. Once the address has been latched and the access completed, a new access to a random location (different row) may begin while /CE is still active. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM28V020’s /CE-initiated access time is faster than the address cycle time. The FM28V020 will drive the data bus only when /OE is asserted low and the memory access time has been satisfied. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive, the data bus will remain hi-Z. Write Operation Writes occur in the FM28V020 in the same time interval as reads. The FM28V020 supports both /CEand /WE-controlled write cycles. In both cases, the address is latched on the falling edge of /CE. In a CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when the device is activated with the chip enable. In this case, the device begins the memory cycle as a Rev. 1.1 Sept. 2009 write. The FM28V020 will not drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when the device is deselected with the chip enable. In a /WE-controlled write, the memory cycle begins when the device is activated with the chip enable. The /WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is asserted low. The /CE- and /WE-controlled write timing cases are shown on page 9. In the Write Cycle Timing 2 diagram, the data bus is shown as a hi-Z condition while the chip is write-enabled and before the required setup time. Although this is drawn to look like a mid-level voltage, it is recommended that all DQ pins comply with the minimum VIH/VIL operating levels. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the deassertion of /WE or /CE, whichever comes first. A valid write operation requires the user to meet the access time specification prior to deasserting /WE or /CE. Data setup time indicates the interval during which data cannot change prior to the end of the write access. Unlike other truly nonvolatile memory technologies, there is no write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM28V020 provides the user fast access to any data within a row element. Each row has eight column locations. An access can start anywhere within a row and other column locations may be accessed without the need to toggle the /CE pin. For page mode reads, once the first data byte is driven onto the bus, the column address inputs A(2:0) may be changed to a new value. A new data byte is then driven to the DQ pins. For page mode writes, the first write pulse defines the first write access. While the device is selected (/CE low), a subsequent write pulse along with a new column address provides a page mode write access. Precharge Operation The precharge operation is an internal condition in which the state of the memory is preparing for a new access. Precharge is user-initiated by driving at least one of the chip enable signals to an inactive state. The Page 4 of 14 FM28V020 - 32Kx8 FRAM chip enable must remain inactive for at least the minimum precharge time tPC. Precharge is also activated by changing the upper addess A(14:3). The current row is first closed prior to accessing the new row. The device automatically detects an upper order address change which starts a precharge operation, the new address is latched, and Endurance The FM28V020 is capable of being accessed at least 1014 times – reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A14-A3 and column addresses by A2-A0. The array is organized as 4K rows of 8-bytes each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. the new read data is valid within the tAA address access time. Refer to the Read Cycle Timing 1 diagram on page 9. Likewise a similar sequence occurs for write cycles. Refer to the Write Cycle Timing 3 diagram on page 11. The rate at which random addresses can be issued is tRC and tWC, respectively. The user may choose to write CPU instructions and run them from a certain address space. The table below shows endurance calculations for 256-byte repeating loop, which includes a starting address, 7 page mode accesses, and a CE precharge. The number of bus clocks needed to complete an 8-byte transaction is 8+1 at lower bus speeds, but 9+2 at 33MHz due to initial read latency and an extra clock to satisfy the device’s precharge timing constraint tPC. The entire loop causes each byte to experience only one endurance cycle. F-RAM read and write endurance is virtually unlimited even at 33MHz system bus clock rate. Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop Bus Freq Bus Cycle 256-byte Endurance Endurance Years to (MHz) Time (ns) Transaction Cycles/sec. Cycles/year Reach 1014 Cycles Time (µ µs) 12 30 10.56 33 94,690 2.98 x 10 33.5 40 12.8 40.6 25 78,125 2.46 x 1012 10 100 28.8 34,720 1.09 x 1012 91.7 5 200 57.6 17,360 5.47 x 1011 182.8 Rev. 1.1 Sept. 2009 Page 5 of 14 FM28V020 - 32Kx8 FRAM SRAM Drop-In Replacement The FM28V020 has been designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low indefinitely while VDD is applied. When /CE is low, the device automatically detects address changes and a new access begins. It also allows page mode operation at speeds up to 33MHz. A typical application is shown in Figure 2. It shows a pullup resistor on /CE which will keep the pin high during power cycles assuming the MCU/MPU pin tristates during the reset condition. The pullup resistor value should be chosen to ensure the /CE pin tracks VDD yet a high enough value that the current drawn when /CE is low is not an issue. VDD FM28V020 R when /WE is low is not an issue. A 10Kohm resistor draws 330uA when /WE is low and VDD=3.3V. VDD FM28V020 R MCU/ MPU CE WE OE A(14:0) DQ(7:0) Figure 3. Use of Pullup Resistor on /WE The FM28V020 is backward compatible with the 256Kbit FM18L08 device. Operating the FM28V020 with /CE toggling low on every address is perfectly acceptable. CE MCU/ MPU WE PCB Layout Recommendations OE A 0.1uF decoupling capacitor should be placed close to pin 28 (VDD) and the ground side of the capacitor should be connected to either a ground plane or low impedance path back to pin 14 (VSS). It is best to use a chip capacitor that has low ESR and has good high frequency characteristics. A(14:0) DQ(7:0) Figure 2. Typical Application using Pullup Resistor on /CE For applications that require the lowest power consumption, the /CE signal should be active only during memory accesses. Due to the external pullup resistor, some supply current will be drawn while /CE is low. When /CE is high, the device draws no more than the maximum standby current ISB. Note that if /CE is grounded, the user must be sure /WE is not low at powerup or powerdown events. If the chip is enabled and /WE is low during power cycles, data corruption will occur. Figure 3 shows a pullup resistor on /WE which will keep the pin high during power cycles assuming the MCU/MPU pin tristates during the reset condition. The pullup resistor value should be chosen to ensure the /WE pin tracks VDD yet a high enough value that the current drawn Rev. 1.1 Sept. 2009 If the controller drives the address and chip enable from the same timing edge, it is best to keep the address routes short and of equal length. A simple RC circuit may be inserted in the chip enable path to provide some delay and timing margin for the FM28V020’s address setup time tAS. As a general rule, the layout designer may need to add series termination resistors to controller outputs that have fast transitions or routes that are > 15cm in length. This is only necessary if the edge rate is less than or equal to the round trip trace delay. Signal overshoot and ringback may be large enough to cause erratic device behavior. It is best to add a 50 ohm resistor (30 – 60 ohms) near the output driver (controller) to reduce such transmission line effects. Page 6 of 14 FM28V020 - 32Kx8 FRAM Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) Package Moisture Sensitivity Level Ratings -1.0V to +4.5V -1.0V to +4.5V and VIN < VDD+1V -55°C to +125°C 260° C TBD TBD TBD MSL-1 (SOIC) MSL-3 (TSOP) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to +85° C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 2.0 3.3 3.6 V IDD VDD Supply Current 7 12 mA 1 ISB Standby Current – CMOS 90 150 2 µA ILI Input Leakage Current 3 ±1 µA ILO Output Leakage Current 3 ±1 µA VIH Input High Voltage 0.7 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 VDD V VOH1 Output High Voltage (IOH = -1 mA, VDD=2.7V) 2.4 V VOH2 Output High Voltage (IOH = -100 µA) VDD-0.2 V VOL1 Output Low Voltage (IOL = 2 mA, VDD=2.7V) 0.4 V VOL2 Output Low Voltage (IOL = 150 µA) 0.2 V Notes 1. VDD = 3.6V, /CE cycling at minimum cycle time. All inputs at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded. 2. VDD = 3.6V, /CE at VDD, All other pins at CMOS levels (0.2V or VDD-0.2V). 3. VIN, VOUT between VDD and VSS. Rev. 1.1 Sept. 2009 Page 7 of 14 FM28V020 - 32Kx8 FRAM Read Cycle AC Parameters (TA = -40° C to +85° C, CL = 30 pF, unless otherwise specified) VDD 2.0 to 2.7V VDD 2.7 to 3.6V Symbol Parameter Min Max Min Max tRC Read Cycle Time 105 90 tCE Chip Enable Access Time 70 60 tAA Address Access Time 105 90 tOH Output Hold Time 20 20 tAAP Page Mode Address Access Time 40 30 tOHP Page Mode Output Hold Time 3 3 tCA Chip Enable Active Time 70 60 tPC Precharge Time 35 30 tAS Address Setup Time (to /CE low) 0 0 tAH Address Hold Time (/CE-controlled) 70 60 tOE Output Enable Access Time 25 15 tHZ Chip Enable to Output High-Z 10 10 tOHZ Output Enable High to Output High-Z 10 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns Notes Write Cycle AC Parameters (TA = -40° C to +85° C, unless otherwise specified) VDD 2.0 to 2.7V VDD 2.7 to 3.6V Symbol Parameter Min Max Min Max tWC Write Cycle Time 105 90 tCA Chip Enable Active Time 70 60 tCW Chip Enable to Write Enable High 70 60 tPC Precharge Time 35 30 tPWC Page Mode Write Enable Cycle Time 40 30 tWP Write Enable Pulse Width 22 18 tAS Address Setup Time (to /CE low) 0 0 tAH Address Hold Time (/CE-controlled) 70 60 tASP Page Mode Address Setup Time (to /WE low) 8 5 tAHP Page Mode Address Hold Time (to /WE low) 20 15 tWLC Write Enable Low to /CE High 30 25 tWLA Write Enable Low to A(14:3) Change 30 25 tAWH A(14:3) Change to Write Enable High 105 90 tDS Data Input Setup Time 20 15 tDH Data Input Hold Time 0 0 tWZ Write Enable Low to Output High Z 10 10 tWX Write Enable High to Output Driven 5 5 tWS Write Enable to /CE Low Setup Time 0 0 tWH Write Enable to /CE High Hold Time 0 0 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 1 1,2 1,2 Notes 1 This parameter is characterized but not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. Power Cycle Timing (TA = -40° C to +85° C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max tVR VDD Rise Time 50 tVF VDD Fall Time 100 tPU Power Up (VDD min) to First Access Time 250 tPD Last Access to Power Down (VDD min) 0 - Units µs/V µs/V µs µs Notes 1 1 Notes 1 Slope measured at any point on VDD waveform. Rev. 1.1 Sept. 2009 Page 8 of 14 FM28V020 - 32Kx8 FRAM Data Retention (VDD = 2.0V to 3.6V, +85°C) Parameter Data Retention Capacitance (TA = 25° C , f=1 MHz, VDD = 3.3V) Symbol Parameter CI/O Input/Output Capacitance (DQ) CIN Input Capacitance Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Output Load Capacitance Min 10 Max - Units Years Notes Min - Max 8 6 Units pF pF Notes 1 1 0 to 3V 3 ns 1.5V 30 pF Read Cycle Timing 1 (/CE low, /OE low) tRC A(14:0) tAA tOH tOH DQ(7:0) Read Cycle Timing 2 (/CE-controlled) tCA tPC CE tAH tAS A(14:0) tOE tHZ OE tCE tOHZ DQ(7:0) Rev. 1.1 Sept. 2009 Page 9 of 14 FM28V020 - 32Kx8 FRAM Page Mode Read Cycle Timing Although sequential column addressing is shown, it is not required. Write Cycle Timing 1 (/WE-Controlled) Note: /OE is low only to show effect of /WE on DQ pins tCA tPC tCW CE tWLC tAS A(14:0) tWP tWX WE DQ(7:0) tWZ tDH tDS D out D in tHZ D out Write Cycle Timing 2 (/CE-Controlled) NOTE: See Write Operation section for detailed description (page 4). Rev. 1.1 Sept. 2009 Page 10 of 14 FM28V020 - 32Kx8 FRAM Write Cycle Timing 3 (/CE low) Note: /OE is low only to show effect of /WE on DQ pins tWC tAWH A(14:0) tWLA WE tWX tWZ DQ(7:0) D out tDS D in tDH D out D in Page Mode Write Cycle Timing Although sequential column addressing is shown, it is not required. Power Cycle Timing Rev. 1.1 Sept. 2009 Page 11 of 14 FM28V020 - 32Kx8 FRAM Mechanical Drawing 28-pin SOIC (JEDEC MS-013D Variation AE) All dimensions in millimeters 7.50 ±0.10 10.30 ±0.30 0.25 0.75 Pin 1 17.90 ±0.20 2.35 2.65 45 ° 0.23 0.32 0?- 8? 1.27 typ 0.10 0.30 0.33 0.51 0.10 0.40 1.27 SOIC Package Marking Scheme RAMTRON XXXXXXX-P RYYWWLLLLLLL Legend: XXXX= part number, P= package type (-SG) R=Rev, YY=year, WW=work week, LLLLLL= lot code Example: FM28V020, “Green”/RoHS SOIC package, R=Rev. A, Year 2009, Work Week 23, Lot code 6340282 RAMTRON FM28V020-SG A09236340282 Rev. 1.1 Sept. 2009 Page 12 of 14 FM28V020 - 32Kx8 FRAM 32-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters TSOP Package Marking Scheme RAMTRON XXXXXXX-P YYWWLLLLLL Rev. 1.1 Sept. 2009 Legend: XXXXXX= part number, P= package/option (T=TSOP, S=SOIC) R=rev code, YY=year, WW=work week, LLLLLL= lot code Example: FM28V020-TG, “Green” TSOP package, A rev., Year 2009, Work Week 31, Lot 6340282 RAMTRON FM28V020-T A09316340282 Page 13 of 14 FM28V020 - 32Kx8 FRAM Revision History Revision 1.0 1.1 Rev. 1.1 Sept. 2009 Date 4/15/2009 9/8/2009 Summary Initial release. Added TSOP package and MSL rating. Expanded explanation of precharge operation. Updated lead temperature rating in Abs Max table. Page 14 of 14