Revised March 2000 DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74LS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK J K Q L H X X X H L H L X X X L H L L X X X H H ↑ L L H H ↑ H L Q H (Note 1) H (Note 1) L H Toggle H H ↑ L H Q0 H H ↑ H H H L H H L X X Q0 Q0 Q0 H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↑ = Rising Edge of Pulse Q0 = The output logic level of Q before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each active transition of the clock pulse. Note 1: This configuration is nonstable; that is, it will not persist when preset and/or clear inputs return to their inactive (HIGH) state. © 2000 Fairchild Semiconductor Corporation DS006368 www.fairchildsemi.com DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 DM74LS109A Absolute Maximum Ratings(Note 2) Supply Voltage Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.75 5 5.25 V LOW Level Input Voltage 0.8 V mA VCC Supply Voltage VIH HIGH Level Input Voltage VIL 2 V IOH HIGH Level Output Current −0.4 IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 3) 0 25 MHz fCLK Clock Frequency (Note 4) 0 20 MHz tW Pulse Width (Note 3) tW tSU tSU Clock HIGH 18 Preset LOW 15 Clear LOW 15 Pulse Width Clock HIGH 25 (Note 4) Preset LOW 20 Clear LOW 20 Setup Time Data HIGH 30↑ (Note 3)(Note 5) Data LOW 20↑ Setup Time Data HIGH 35↑ (Note 5)(Note 4) Data LOW 25↑ tH Hold Time (Note 6) 0↑ TA Free Air Operating Temperature 0 Note 3: CL = 15 pF, R L = 2 kΩ, TA = 25°C and VCC = 5V. Note 4: CL = 50 pF, R L = 2 kΩ, TA = 25°C and VCC = 5V. Note 5: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 6: TA = 25°C and V CC = 5V. www.fairchildsemi.com 2 ns ns ns ns ns 70 °C over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min Typ (Note 7) 2.7 IIH −1.5 V V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max J, K 0.1 Input Voltage VI = 7V Clock 0.1 Preset 0.2 Clear 0.2 HIGH Level VCC = Max J,K 20 Input Current VI = 2.7V Clock 20 Preset 40 Clear IIL Units 3.4 IOL = 4 mA, VCC = Min II Max VCC = Max J, K −0.4 Input Current VI = 0.4V Clock −0.4 Preset −0.8 Clear −0.8 IOS Short Circuit Output Current VCC = Max (Note 8) Supply Current VCC = Max (Note 9) mA µA 40 LOW Level ICC V −20 4 mA −100 mA 8 mA Note 7: All typicals are at VCC = 5V, TA = 25°C. Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 9: ICC is measured with all outputs OPEN, with CLOCK grounded after setting the Q and Q outputs HIGH in turn. Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH tPHL tPLH Q or Q Clock to Q or Q Clear LOW-to-HIGH Level Output to Q Propagation Delay Time Clear HIGH-to-LOW Level Output to Q LOW-to-HIGH Level Output tPHL 25 Clock to Propagation Delay Time Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output CL = 50 pF Max Preset to Q Preset to Q 3 Min Units Max 20 MHz 25 35 ns 30 35 ns 25 35 ns 30 35 ns 25 35 ns 30 35 ns www.fairchildsemi.com DM74LS109A Electrical Characteristics DM74LS109A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 4 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)