Revised April 2000 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop. ■ DM74LS174 contains six flip-flops with single-rail outputs Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. ■ Buffered clock and direct clear inputs ■ DM74LS175 contains four flip-flops with double-rail outputs ■ Individual data input to each flip-flop ■ Applications include: Buffer/storage registers Shift registers Pattern generators ■ Typical clock frequency 40 MHz ■ Typical power dissipation per flip-flop 14 mW Ordering Code: Order Number Package Number Package Description DM74LS174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS174N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74LS174 © 2000 Fairchild Semiconductor Corporation DM74LS175 DS006404 www.fairchildsemi.com DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear August 1992 DM74LS174 • DM74LS175 Function Table (Each Flip-Flop) Inputs Outputs Clear Clock D Q Q† L X X L H H ↑ H H L H ↑ L L H H L X Q0 Q0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care ↑ = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established. † = DM74LS175 only Logic Diagrams DM74LS174 www.fairchildsemi.com DM74LS175 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range DM74LS174 Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency (Note 2) fCLK Clock Frequency (Note 3) tW Pulse Width Clock 20 (Note 4) Clear 20 2 V 8 mA 0 30 MHz 0 25 MHz ns tSU Data Setup Time (Note 4) 20 ns tH Data Hold Time (Note 4) 0 ns tREL Clear Release Time (Note 4) 25 TA Free Air Operating Temperature 0 ns °C 70 Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 4: TA = 25°C and VCC = 5V. DM74LS174 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min 2.7 IOL = 4 mA, VCC = Min II Input Current @ Max Input Voltage VCC = Max, VI = 7V IIH HIGH Level Input Current VCC = Max, VI = 2.7V IIL LOW Level VCC = Max Input Current VI = 0.4V IOS Short Circuit Output Current VCC = Max (Note 6) ICC Supply Current VCC = Max (Note 7) Typ (Note 5) Max Units −1.5 V 3.4 V 0.35 0.5 0.25 0.4 V 0.1 mA 20 µA −0.4 Clock Clear −0.4 Data −0.36 −20 16 mA −100 mA 26 mA Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: With all outputs OPEN and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock. 3 www.fairchildsemi.com DM74LS174 • DM74LS175 Absolute Maximum Ratings(Note 1) DM74LS174 • DM74LS175 DM74LS174 Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output www.fairchildsemi.com Max 30 CL = 50 pF Min Units Max 25 MHz Clock to Output 30 32 ns Clock to Output 30 36 ns Clear to Output 35 42 ns 4 Symbol Parameter Min Nom Max Units 4.75 5 5.25 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency (Note 8) fCLK Clock Frequency (Note 9) tW Pulse Width Clock 20 (Note 10) Clear 20 2 V 8 mA 0 30 MHz 0 25 MHz ns tSU Data Setup Time (Note 10) 20 tH Data Hold Time (Note 10) 0 ns ns tREL Clear Release Time (Note 10) 25 ns TA Free Air Operating Temperature 0 °C 70 Note 8: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 9: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 10: TA = 25°C and VCC = 5V. DM74LS175 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min VOL Min 2.7 Input Current @ Max Input Voltage VCC = Max, VI = 7V IIH HIGH Level Input Current VCC = Max, VI = 2.7V IIL LOW Level VCC = Max Input Current VI = 0.4V IOS Short Circuit Output Current VCC = Max (Note 12) ICC Supply Current VCC = Max (Note 13) Max Units −1.5 V 3.4 IOL = 4 mA, VCC = Min II Typ (Note 11) V 0.35 0.5 0.25 0.4 V 0.1 mA 20 µA −0.4 Clock Clear −0.4 Data −0.36 −20 11 mA −100 mA 18 mA Note 11: All typicals are at VCC = 5V, TA = 25°C. Note 12: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 13: With all outputs OPEN and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock input. DM74LS175 Switching Characteristics at VCC = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load) RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output Max 30 CL = 50 pF Min Units Max 25 MHz Clock to Q or Q 30 32 ns Clock to Q or Q 30 36 ns Clear to Q 25 29 ns Clear to Q 35 42 ns 5 www.fairchildsemi.com DM74LS174 • DM74LS175 DM74LS175 Recommended Operating Conditions DM74LS174 • DM74LS175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com