5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is low the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is high the J and K inputs are disabled. On the negative transition of the clock, the data from the master is trans- ferred to the slave. The logic state of J and K inputs must not be allowed to change while the clock is high. The data is transfered to the outputs on the falling edge of the clock pulse. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Features Y Connection Diagram Alternate Military/Aerospace device (5476) is available. Contact a National Semiconductor Sales Office/Distributor for specifications. Function Table Dual-In-Line Package Inputs Outputs PR CLR CLK J K Q L H L H H H H H L L H H H H X X X É É É É X X X L H L H X X X L L H H H L L H H* H* Q0 Q0 H L L H Toggle Q H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level É e Positive pulse data. The J and K inputs must be held constant while the clock is high. Data is transfered to the outputs on the falling edge of the clock pulse. TL/F/6528 – 1 Order Number 5476DMQB, 5476FMQB, DM5476J, DM5476W or DM7476N See NS Package Number J16A, N16E or W16A C1995 National Semiconductor Corporation TL/F/6528 * e This configuration is nonstable; that is, it will not persist when the preset and/or clear inputs return to their inactive (high) level. Q0 e The output logic level before the indicated input conditions were established. Toggle e Each output changes to the complement of its previous level on each complete active high level clock pulse. RRD-B30M105/Printed in U. S. A. 5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 and 54 DM74 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM5476 Parameter DM7476 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 6) 0 tW Pulse Width (Note 6) Clock High 20 Clock Low 47 47 Preset Low 25 25 2 2 V V 0.8 0.8 V b 0.4 b 0.4 mA 16 15 0 16 mA 15 MHz 20 Clear Low 25 25 tSU Input Setup Time (Notes 1 & 6) 0u 0u tH Input Hold Time (Notes 1 & 6) 0v 0v TA Free Air Operating Temperature b 55 125 ns ns ns 0 70 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max VI e 2.4V 2.4 Typ (Note 2) Low Level Input Current 0.2 J, K VCC e Max VI e 0.4V ICC b 1.5 V V 0.4 V 1 mA 40 Clock 80 Clear 80 b 1.6 Clock b 3.2 (Note 5) Clear b 3.2 Short Circuit Output Current VCC e Max (Note 3) DM54 b 20 b 55 DM74 b 18 b 55 Supply Current VCC e Max (Note 4) Note 1: The symbol ( 18 34 Note 2: All typicals are at VCC e 5V, TA e 25§ C. Note 3: Not more than one output should be shorted at a time. Note 4: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement the clock input is grounded. Note 5: Clear is measured with preset high and preset is measured with clear high. 2 mA b 3.2 u, v) indicates the edge of the clock pulse is used for reference (u) for rising edge, (v) for falling edge. Note 6: TA e 25§ C and VCC e 5V. mA 80 J, K Preset IOS Units 3.4 Preset IIL Max mA mA Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol RL e 400X CL e 15 pF From (Input) To (Output) Parameter Min Units Max fMAX Maximum Clock Frequency tPHL Propagation Delay Time High to Low Level Output Preset to Q 40 ns tPLH Propagation Delay Time Low to High Level Output Preset to Q 25 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 40 ns tPLH Propagation Delay Time Low to High Level Output Clear to Q 25 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q or Q 40 ns tPLH Propagation Delay Time Low to High Level Output Clock to Q or Q 25 ns 15 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 5476DMQB or DM5476J NS Package Number J16A 3 MHz 5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM7476N NS Package Number N16E LIFE SUPPORT POLICY 16-Lead Ceramic Flat Package (W) Order Number 5476FMQB or DM7476W NS Package Number W16A NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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