FAIRCHILD MTD56

Revised November 2000
74VCXF162835
Low Voltage 18-Bit Universal Bus Driver with 3.6V
Tolerant Outputs and 26Ω Series Resistors in Outputs
General Description
Features
The VCXF162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
■ Compatible with PC133 DIMM module specifications
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
■ 1.65V–3.6V VCC specifications provided
■ 3.6V tolerant outputs
■ 26Ω series resistors in outputs
■ tPD (CLK to O n)
3.2 ns max for 3.0V to 3.6V VCC
4.1 ns max for 2.3V to 2.7V VCC
7.4 ns max for 1.65V to 1.95V VCC
■ Power-down high impedance outputs
The VCXF162835 is designed with 26Ω series resistors in
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus transceivers/transmitters.
■ Static Drive (IOH/IOL)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
The 74VCXF162835 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
■ Latchup performance exceeds 300 mA
The 74VCXF162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
■ ESD performance:
Human body model > 2000V
Machine model >200V
Ordering Code:
Order Number
Package
Number
74VCXF162835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74VCXF162835MTX
(Note 1)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Package Description
Note 1: Use this Order Number to receive devices in Tape and Reel.
© 2000 Fairchild Semiconductor Corporation
DS500259
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74VCXF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in
Outputs
October 1999
74VCXF162835
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
Output Enable Input (Active LOW)
LE
Latch Enable Input
CLK
Clock Input
I1 - I18
Data Inputs
O1 - O18
3-STATE Outputs
Truth Table
Inputs
Outputs
OE
LE
CLK
In
On
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
O0 (Note 2)
L
L
L
X
O0 (Note 3)
H = Logic HIGH
L = Logic LOW
X = Don’t Care, but not floating
Z = High Impedance
↑ = LOW-to-HIGH Clock Transition
Note 2: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Logic Diagram
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2
Supply Voltage (VCC)
−0.5V to +4.6V
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Recommended Operating
Conditions (Note 7)
Power Supply
Output Voltage (VO)
Operating
−0.5V to +4.6V
Outputs 3-STATE
Outputs Active (Note 5)
1.65V to 3.6V
Data Retention Only
−0.5V to VCC + 0.5V
1.2V to 3.6V
−0.3V to VCC
Input Voltage
DC Input Diode Current (IIK)
Output Voltage (VO)
VI < −0.5V
−50 mA
Output in Active States
0V to VCC
VI > VCC + 0.5V (Note 6)
+50 mA
Output in 3-STATE
0V to 3.6V
DC Output Diode Current (IOK)
Output Current in IOH/IOL
VO < 0V
−50 mA
VCC = 3.0V to 3.6V
±12 mA
VO > VCC
+50 mA
VCC = 2.3V to 2.7V
±8 mA
VCC = 1.65V to 2.3V
DC Output Source/Sink Current
±50 mA
(IOH/IOL)
Minimum Input Edge Rate (∆t/∆V)
DC VCC or Ground Current per
Supply Pin (I CC or Ground)
Storage Temperature Range (TSTG)
±3 mA
−40°C to +85°C
Free Air Operating Temperature (TA)
±100 mA
VIN = 0.8V to 2.0V, VCC = 3.0V
−65°C to +150°C
10 ns/V
Note 4: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Inputs do not have over-voltage tolerance.
Note 7: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < VCC ≤ 3.6V)
Symbol
Parameter
Conditions
VCC
(V)
VIH
HIGH Level Input Voltage
2.7–3.6
VIL
LOW Level Input Voltage
2.7–3.6
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
IOH = −100 µA
Min
Max
2.0
V
0.8
2.7–3.6
VCC − 0.2
IOH = −6 mA
2.7
2.2
IOH = −8 mA
3.0
2.4
IOH = −12 mA
3.0
2.2
IOL = 100 µA
2.7–3.6
0.2
IOL = 6mA
2.7
0.4
IOL = 8 mA
3.0
0.55
IOL = 12mA
II
Input Leakage Current
VI = V CC or GND
IOZ
3-STATE Output Leakage
0V ≤ VO ≤ 3.6V
VI = V IH or VIL
IOFF
Power Off Leakage Current
0V ≤ (VO) ≤ 3.6V
ICC
Quiescent Supply Current
VI = V CC or GND
∆ICC
Increase in ICC per Input
VIH = VCC − 0.6V
VCC ≤ (VO) ≤ 3.6V (Note 8)
Units
V
V
V
3.0
0.8
2.7–3.6
±5.0
µA
2.7–3.6
±10
µA
0
10
µA
2.7–3.6
2.7–3.6
20
±20
750
µA
µA
Note 8: Outputs disabled or 3-STATE only.
3
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74VCXF162835
Absolute Maximum Ratings(Note 4)
74VCXF162835
DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V)
Symbol
Parameter
VCC
Conditions
(V)
VIH
HIGH Level Input Voltage
2.3–2.7
VIL
LOW Level Input Voltage
2.3–2.7
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
IOH = −100 µA
Min
Max
1.6
V
0.7
2.3–2.7
VCC − 0.2
IOH = −3 mA
2.3
2.0
IOH = −6 mA
2.3
1.8
IOH = −8 mA
2.3
1.7
IOL = 100 µA
Units
V
V
2.3–2.7
0.2
IOL = 6 mA
2.3
0.4
IOL = 8 mA
2.3
0.6
2.3–2.7
±5.0
µA
2.3–2.7
±10
µA
0
10
µA
II
Input Leakage Current
VI = VCC or GND
IOZ
3-STATE Output Leakage
0V ≤ VO ≤ 3.6V
VI = VIH or VIL
IOFF
Power Off Leakage Current
0V ≤ (VO) ≤ 3.6V
ICC
Quiescent Supply Current
VI = VCC or GND
VCC ≤ (VO) ≤ 3.6V (Note 9)
20
2.3–2.7
±20
V
µA
Note 9: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V ≤ VCC < 2.3V)
Symbol
Parameter
Conditions
VCC
(V)
VIH
HIGH Level Input Voltage
1.65 - 2.3
VIL
LOW Level Input Voltage
1.65 - 2.3
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
IOH = −100 µA
Max
0.65 × VCC
Units
V
0.35 × VCC
V
1.65 - 2.3
VCC − 0.2
IOH = −3 mA
1.65
1.25
IOL = 100 µA
1.65 - 2.3
0.2
1.65
0.3
1.65 - 2.3
±5.0
µA
1.65 - 2.3
±10
µA
0
10
µA
IOL = 3 mA
II
Input Leakage Current
VI = VCC or GND
IOZ
3-STATE Output Leakage
0V ≤ VO ≤ 3.6V
IOFF
Power Off Leakage Current
0V ≤ (VO) ≤ 3.6V
ICC
Quiescent Supply Current
VI = VCC or GND
VI = VIH or VIL
VCC ≤ (VO) ≤ 3.6V (Note 10)
Note 10: Outputs disabled or 3-STATE only.
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Min
4
1.65 - 2.3
V
20
±20
V
µA
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
Min
fMAX
Maximum Clock Frequency
tPHL, tPLH
Propagation Delay
Bus to Bus
tPHL, tPLH
Propagation Delay
Clock to Bus
tPHL, tPLH
Propagation Delay
Max
250
VCC = 2.5 ± 0.2V
VCC = 1.8 ± 0.15V
Min
Min
Max
200
Units
Max
100
MHz
0.6
3.1
0.8
4.0
1.5
7.2
ns
1.0
3.2
1.5
4.1
2.0
7.4
ns
0.6
3.7
0.8
4.7
1.5
8.5
ns
tPZL, tPZH
Output Enable Time
0.6
4.3
0.8
5.9
1.5
9.8
ns
tPLZ, tPHZ
Output Disable Time
0.6
4.2
0.8
4.7
1.5
7.9
ns
tS
Setup Time
1.5
1.5
2.5
tH
Hold Time
0.7
0.7
1.0
ns
tW
Pulse Width
1.5
1.5
4.0
ns
tOSHL
Output to Output Skew
tOSLH
(Note 12)
LE to Bus
0.5
ns
0.5
0.75
ns
Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
AC Electrical Characteristics Over Load (Note 13)
TA = −0°C to +85°C, RL = 500Ω V CC = 3.3V ± 03V
Symbol
CL = 50 pF
Parameter
Units
Min
Max
tPHL, tPLH
Propagation Delay Bus to Bus
1.0
3.4
ns
tPHL, tPLH
Propagation Delay Clock to Bus
1.4
3.5
ns
tPHL, tPLH
Propagation Delay LE to Bus
1.0
4.0
ns
tPZL, tPZH
Output Enable Time
1.0
4.6
ns
tPLZ, tPHZ
Output Disable Time
1.0
4.5
ns
tS
Setup Time
1.0
ns
tH
Hold Time
0.6
ns
Note 13: Characterized only.
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VOHV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
5
VCC
TA=+25°C
(V)
Typical
1.8
0.25
2.5
0.40
3.3
0.55
1.8
−0.25
2.5
−0.40
3.3
−0.55
1.8
1.35
2.5
1.80
3.3
2.30
Units
V
V
V
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74VCXF162835
AC Electrical Characteristics (Note 11)
74VCXF162835
Capacitance
Symbol
Parameter
Conditions
TA = +25°C
Typical
Units
CIN
Input Capacitance
VI = 0V or VCC, VCC = 1.8V, 2.5V, or 3.3V,
3.5
CI/O
Input/Output Capacitance
VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V
5.5
pF
CPD
Power Dissipation Capacitance
VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V
13
pF
IOUT - VOUT Characteristics
IOH versus VOH
FIGURE 1. Characteristics for Output - Pull Up Drive
IOL versus VOL
FIGURE 2. Characteristics for Output - Pull Down Driver
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6
pF
74VCXF162835
AC Loading and Waveforms
FIGURE 3. AC Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V to ± 0.15V
tPZH, tPHZ
GND
FIGURE 4. Waveform for Inverting and
Non-inverting Functions
tr = tf ≤ 2.0ns, 10% to 90%
FIGURE 5. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
tr = tf ≤ 2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
tr = tf ≤ 2.0ns, 10% to 90%
Symbol
VCC
3.3V ± 0.3V
2.5V ± 0.2V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
Vx
VOL + 0.3V
VOL + 0.15V
VOL + 0.15V
Vy
VOH − 0.3V
VOH − 0.15V
VOH − 0.15V
7
1.8 ± 0.15V
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74VCXF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in
Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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