Revised September 2001 74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs General Description Features The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. ■ Compatible with PC100 DIMM module specifications Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVC162835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVC162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.65V–3.6V VCC specifications provided ■ 3.6V tolerant inputs and outputs ■ 26Ω series resistors in outputs ■ tPD (CLK to O n) 5.4 ns max for 3.0V to 3.6V VCC 6.3 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC ■ Power-down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ Latchup conforms to JEDEC JED78 ■ ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pulldown resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number 74ALVC162835T Package Number Package Description MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS500646 www.fairchildsemi.com 74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs September 2001 74ALVC162835 Connection Diagram Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input I1 - I18 Data Inputs O1 - O18 3-STATE Outputs Truth Table Inputs Outputs OE LE CLK In On H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H L L H X O0 (Note 2) L L L X O0 (Note 3) H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 2: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 3: Output level before the indicated steady-state input conditions were established. Logic Diagram www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions (Note 6) −0.5V to +4.6V −0.5V to +4.6V DC Input Voltage (VI) Output Voltage (VO) (Note 5) Power Supply −0.5V to VCC + 0.5V Operating DC Input Diode Current (IIK) VI < 0V −50 mA 0V to VCC Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC Free Air Operating Temperature (TA) VO < 0V −50 mA −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V DC Output Source/Sink Current ±50 mA (IOH/IOL) ±100 mA Supply Pin (ICC or Ground) 10 ns/V Note 4: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. DC VCC or Ground Current per Storage Temperature Range (TSTG) 1.65V to 3.6V Input Voltage −65°C to +150°C Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH VOL IOH IOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC (V) Min 1.65 - 1.95 0.65 x VCC 2.3 - 2.7 1.7 2.7 - 3.6 2.0 Max V 1.65 - 1.95 0.35 x VCC 2.3 - 2.7 0.7 2.7 - 3.6 0.8 1.65 - 3.6 1.65 1.2 IOH = −4 mA 2.3 1.9 IOH = −6 mA 2.3 1.7 3.0 2.4 IOH = −8 mA 2.7 2 IOH = −12 mA 3.0 2 IOL = 100 µA 1.65 - 3.6 0.2 IOL = 2 mA 1.65 0.45 IOL = 4 mA 2.3 0.4 IOL = 6 mA 2.3 0.55 3.0 0.55 V IOL = 8 mA 2.7 0.6 IOL = 12 mA 3 0.8 1.65 −2 2.3 −6 2.7 −8 3.0 −12 LOW Level Output Current V VCC - 0.2 IOH = −2 mA High Level Output Current Units 1.65 2 2.3 6 2.7 8 V mA mA 3 12 II Input Leakage Current 0 ≤ VI ≤ 3.6V 3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA ICC Quiescent Supply Current VI = V CC or GND, IO = 0 3.6 40 µA ∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 - 3.6 750 µA 3 www.fairchildsemi.com 74ALVC162835 Absolute Maximum Ratings(Note 4) 74ALVC162835 AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol CL = 50 pF Parameter VCC = 3.3V ± 0.3V Min fCLOCK Clock Frequency tW Pulse Width LE High tS Setup Time tH Hold Time Min Max VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V Min Max 150 Min 100 3.3 3.3 CLK High or Low 3.3 3.3 3.3 4.0 Data Before CLK ↑ 1.7 2.1 2.2 2.5 Data Before CLK ↓ CLK High 1.5 1.6 1.9 CLK Low 1.0 1.1 1.3 0.7 0.6 0.6 1.4 1.7 1.4 Data After CLK ↑ CLK High Maximum Clock Frequency 150 tPHL, tPLH Propagation I to O 1.0 150 5.0 MHz 4.0 ns ns 1.0 ns 150 4.2 Units Max 150 3.3 or Low Delay Max 150 Data After LE ↓ fMAX CL = 30 pF VCC = 2.7V 100 1.0 5.0 MHz 1.5 9.8 LE to O 1.3 5.1 5.8 1.3 5.9 1.5 9.8 CLK to O 1.4 5.4 6.1 1.4 6.3 2.0 9.2 ns tPZL, tPZH Output Enable Time 1.1 5.5 6.5 1.4 6.3 1.5 9.8 ns tPLZ, tPHZ Output Disable Time 1.3 4.5 4.9 1.0 4.9 1.5 7.9 ns AC Electrical Characteristics Over Load (Note 7) RL = 500Ω, VCC = 3.3V ± 0.15V Symbol Parameter TA = −0°C to +85°C TA = −0°C to +65°C CL = 0 pF CL = 50 pF Units Min Max Min Max tPHL, tPLH Propagation Delay Bus to Bus 0.9 2.0 1.0 4.0 ns tPHL, tPLH Propagation Delay Clock to Bus 1.4 2.9 1.9 5.0 ns Note 7: Characterized only. Capacitance Symbol CIN Parameter Input Capacitance Conditions TA = +25°C VCC Typical Control VI = 0V or VCC 3.3 3.5 Data VI = 0V or VCC 3.3 5 VI = 0V, or VCC COUT Output Capacitance 3.3 7 CPD Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 0 pF 3.3 40 2.5 35 Outputs Disabled f = 10 MHz, CL = 0 pF 3.3 14 2.5 125 www.fairchildsemi.com 4 Units pF pF pF 74ALVC162835 IOUT - VOUT Characteristics IOH versus VOH FIGURE 1. Characteristics for Output - Pull Up Drive IOL versus VOL FIGURE 2. Characteristics for Output - Pull Down Driver 5 www.fairchildsemi.com 74ALVC162835 AC Loading and Waveforms FIGURE 3. AC Test Circuit TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V to ± 0.15V tPZH, tPHZ GND FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% FIGURE 4. Waveform for Inverting and Non-inverting Functions tr = tf ≤ 2.0ns, 10% to 90% FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% Symbol www.fairchildsemi.com VCC 3.3V ± 0.3V 2.5V ± 0.2V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 Vx VOL + 0.3V VOL + 0.15V VOL + 0.15V Vy VOH − 0.3V VOH − 0.15V VOH − 0.15V 6 1.8 ± 0.15V 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com 74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs Physical Dimensions inches (millimeters) unless otherwise noted