Revised November 2004 74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in Outputs General Description Features The 74ALVCF322835 low voltage 36-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. ■ Compatible with PC133 DIMM module specifications Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The 74ALVCF322835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. ■ 1.65V to 3.6V VCC specifications provided ■ 3.6V tolerant outputs ■ 26Ω series resistors in outputs ■ tPD (CLK to O n) 3.7 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 7.4 ns max for 1.65V to 1.95V VCC ■ Power-down high impedance outputs ■ Latchup conforms to JEDEC JED78 ■ ESD performance: Human body model > 2000V Machine model >200V The 74ALVCF322835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVCF322835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Ordering Code: Order Number 74ALVCF322835G (Note 1)(Note 2) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Note 1: Ordering Code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2004 Fairchild Semiconductor Corporation DS500741 www.fairchildsemi.com 74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in Outputs May 2002 74ALVCF322835 Connection Diagram FBGA Pin Assignments (Top Thru View) 2 3 4 1O2 1O1 NC NC 5 6 1I1 1I2 B 1O4 1O3 NC C 1O6 1O5 GND GND 1I3 1I4 GND 1I5 D 1O8 1O7 1I6 VCC VCC 1I7 E 1O10 1I8 1O9 GND GND 1I9 F 1I10 1O12 1O11 GND GND 1I11 1I12 G 1O14 1O13 VCC VCC 1I13 1I14 H 1O15 1O16 GND GND 1I16 1I15 1I17 J 1O17 1O18 OE1 CLK1 1I18 K NC NC LE1 GND NC NC L 2O2 2O1 NC GND 2I1 2I2 M 2O4 2O3 GND GND 2I3 2I4 N 2O6 2O5 VCC VCC 2I5 2I6 P 2O8 2O7 GND GND 2I7 2I8 R 2O10 2O9 GND GND 2I9 2I10 T 2O12 2O11 VCC VCC 2I11 2I12 U 2O14 2O13 GND GND 2I13 2I14 V 2O15 2O16 OE2 CLK2 2I16 2I15 W 2O17 2O18 LE2 GND 2I18 2I17 Truth Table Pin Descriptions Pin Names 1 A Inputs Description Outputs OEn Output Enable Input (Active LOW) OEn LEn CLKn In On LEn Latch Enable Input H X X X Z CLKn Clock Input L H X L L 1I1 - 1I18 Data Inputs L H X H H 2I1 - 2I18 Data Inputs L L ↑ L L 1O1 - 1O18 3-STATE Outputs L L ↑ H H 2O1 - 2O18 3-STATE Outputs L L H X O0 (Note 3) L L L X O0 (Note 4) H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 3: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 4: Output level before the indicated steady-state input conditions were established. Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 7) −0.5V to +4.6V Supply Voltage (VCC) −0.5V to 4.6V DC Input Voltage (VI) Output Voltage (VO) (Note 6) Power Supply −0.5V to VCC +0.5V Operating DC Input Diode Current (IIK) VI < 0V −50 mA 0V to VCC Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC Free Air Operating Temperature (TA) VO < 0V −50 mA −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V DC Output Source/Sink Current ±50 mA (IOH/IOL) ±100 mA Supply Pin (ICC or GND) 10 ns/V Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC VCC or GND Current per Storage Temperature Range (TSTG) 1.65V to 3.6V Input Voltage −65°C to +150°C Note 6: IO Absolute Maximum Rating must be observed. Note 7: Floating or unused control inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH VOL IOH IOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC (V) Min 1.65 - 1.95 0.65 x VCC 2.3 - 2.7 1.7 2.7 - 3.6 2.0 Max V 1.65 - 1.95 0.35 x VCC 2.3 - 2.7 0.7 2.7 - 3.6 0.8 1.65 - 3.6 1.65 1.2 IOH = −4 mA 2.3 1.9 IOH = −6 mA 2.3 1.7 3.0 2.4 IOH = −8 mA 2.7 2 IOH = −12 mA 3.0 2 IOL = 100 µA 1.65 - 3.6 0.2 IOL = 2 mA 1.65 0.45 IOL = 4 mA 2.3 0.4 IOL = 6 mA 2.3 0.55 3.0 0.55 V IOL = 8 mA 2.7 0.6 IOL = 12 mA 3.0 0.8 1.65 −2 2.3 −6 2.7 −8 Low Level Output Current V VCC - 0.2 IOH = −2 mA High Level Output Current Units 3.0 −12 1.65 2 2.3 6 2.7 8 V mA mA 3.0 12 II Input Leakage Current 0 ≤ VI ≤ 3.6V 1.65 - 3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V, V I = VIH or VIL 1.65 - 3.6 ±10 µA IOFF Power Off Leakage Current 0V ≤ (VI, VO) ≤ 3.6V ICC Quiescent Supply Current VI = V CC or GND, IO = 0 ∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 0 10 mA 3.6 40 µA 2.7 - 3.6 750 µA www.fairchildsemi.com 74ALVCF322835 Absolute Maximum Ratings(Note 5) 74ALVCF322835 AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter CL = 50 pF VCC = 3.3V ± 0.3V Min fMAX Maximum Clock Frequency tPHL, tPLH Propagation Delay Max 250 CL = 30 pF VCC = 2.7V Min Max 200 VCC = 2.5 ± 0.2V Min Max 200 VCC = 1.8V ± 0.15V Min Units Max 100 MHz 1.1 3.6 1.3 4.5 0.8 4.0 1.5 7.2 ns 1.5 3.7 2.0 4.6 1.5 4.1 2.0 7.4 ns 1.1 4.2 1.3 5.2 0.8 4.7 1.5 8.5 ns Bus-to-Bus tPHL, tPLH Propagation Delay Clock to Bus tPHL, tPLH Propagation Delay LE to Bus tPZL, tPZH Output Enable Time 1.1 4.8 1.3 6.4 0.8 5.9 1.5 9.8 ns tPLZ, tPHZ Output Disable Time 1.1 4.7 1.3 5.2 0.8 4.7 1.5 7.9 ns tS Setup Time 1.5 1.5 1.5 2.5 tH Hold Time 0.7 0.7 0.7 1.0 ns tW Pulse Width 1.5 1.5 1.5 4.0 ns ns Capacitance Symbol Parameter Conditions TA = +25°C VCC Typical Units CIN Input Capacitance VI = 0V or VCC 3.3 3.5 pF COUT Output Capacitance VI = 0V or VCC 3.3 5.5 pF CPD Power Dissipation Capacitance 3.3 13 2.5 13 www.fairchildsemi.com Outputs Enabled f = 10 MHz, CL = 0 pF 4 pF 74ALVCF322835 IOUT - VOUT Characteristics IOH versus VOH FIGURE 1. Characteristics for Output - Pull Up Drive IOL versus VOL FIGURE 2. Characteristics for Output - Pull Down Driver 5 www.fairchildsemi.com 74ALVCF322835 AC Loading and Waveforms Table 1: Values for Figure 1 TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VL tPZH, tPHZ GND FIGURE 3. AC Test Circuit Table 2: Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V 1.5V VCC/2 VCC/2 Vmo 1.5V 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.3V VOH − 0.15V VOH − 0.15V VL 6V 6V VCC*2 VCC*2 FIGURE 4. Waveform for Inverting and Non-inverting Functions FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic www.fairchildsemi.com 6 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com 74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in Outputs Physical Dimensions inches (millimeters) unless otherwise noted