TI SN74ALVCHS162830

SN74ALVCHS162830
1-BIT TO 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES097F – APRIL 1997 – REVISED JUNE 1999
D
D
D
D
D
D
D
D
DBB PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
Diodes on Inputs Clamp Overshoot
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in Thin Very Small-Outline
Package
2Y2
1Y2
GND
2Y1
1Y1
VCC
A1
A2
GND
A3
A4
GND
A5
A6
VCC
A7
A8
GND
A9
OE1
OE2
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
GND
A17
A18
VCC
2Y18
1Y18
GND
2Y17
1Y17
NOTE: For order entry:
The DBB package is abbreviated to G.
For tape and reel:
The DBBR package is abbreviated to GR.
description
This 1-bit to 2-bit address driver is designed for
2.3-V to 3.6-V VCC operation.
Diodes to VCC have been added on the inputs to
clamp overshoot.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to
12 mA, include equivalent 26-Ω series resistors to
reduce overshoot and undershoot.
To ensure the high-impedance state during power
up or power down, the output-enable (OE) input
should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
41
1Y3
2Y3
GND
1Y4
2Y4
VCC
1Y5
2Y5
GND
1Y6
2Y6
GND
1Y7
2Y7
VCC
1Y8
2Y8
GND
1Y9
2Y9
1Y10
2Y10
GND
1Y11
2Y11
VCC
1Y12
2Y12
GND
1Y13
2Y13
GND
1Y14
2Y14
VCC
1Y15
2Y15
GND
1Y16
2Y16
The SN74ALVCHS162830 is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVCHS162830
1-BIT TO 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES097F – APRIL 1997 – REVISED JUNE 1999
FUNCTION TABLE
INPUTS
OUTPUTS
OE1
OE2
A
1Yn
2Yn
L
H
H
H
Z
L
H
L
L
Z
H
L
H
Z
H
H
L
L
Z
L
L
L
H
H
H
L
L
L
L
L
H
H
X
Z
Z
logic diagram (positive logic)
VCC
21
OE2
VCC
20
OE1
VCC
A1
5
1Y1
7
4
2Y1
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCHS162830
1-BIT TO 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES097F – APRIL 1997 – REVISED JUNE 1999
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High
level input voltage
High-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low level input voltage
Low-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI
VO
Input voltage
IOH
∆t/∆v
Input transition rise or fall rate
3.6
1.7
UNIT
V
V
2
0.7
0.8
0
High-level output current
Low-level output current
MAX
2.3
0
Output voltage
IOL
MIN
VCC
VCC
VCC = 2.3 V
VCC = 2.7 V
–6
VCC = 3 V
VCC = 2.3 V
–12
VCC = 2.7 V
VCC = 3 V
8
–8
V
V
V
mA
6
mA
12
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ALVCHS162830
1-BIT TO 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES097F – APRIL 1997 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
II = 18 mA
VIK
IOH = –8 mA,
IOH = –12 mA,
IOL = 100 µA
IOL = 4 mA,
IOL = 8 mA,
IOL = 12 mA,
II(hold)
(
)
2.3 V
1.7
3V
2.4
2.7 V
2
VIH = 2 V
3V
2
2.3 V
0.4
2.3 V
0.55
VIL = 0.8 V
VIL = 0.8 V
3V
0.55
2.7 V
0.6
VIL = 0.8 V
3V
0.8
±5
2.3 V
45
VI = 1.7 V
VI = 0.8 V
2.3 V
–45
∆ICC
One input at VCC – 0.6 V,
V
V
VIL = 0.7 V
VIL = 0.7 V
IO = 0
Other inputs at VCC or GND
UNIT
0.2
3.6 V
VO = VCC or GND
VI = VCC or GND,
Data inputs
VCC–0.2
1.9
VI = VCC or GND
VI = 0.7 V
IOZ
ICC
Control inputs
2.3 V
VIH = 2 V
VIH = 2 V
VI = 2 V
VI = 0 to 3.6 V‡
Ci
VCC+1.2
2.3 V to 3.6 V
IOL = 6 mA
II
MAX
–1.2
2.3 V to 3.6 V
VIH = 1.7 V
VIH = 1.7 V
IOH = –6
6 mA
VOL
TYP†
2.3 V
IOH = –100 µA
IOH = –4 mA,
VOH
MIN
VCC
2.3 V
3V
75
3V
–75
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
VI = VCC or GND
5.5
33V
3.3
pF
7
Co
Outputs
VO= VCC or GND
3.3 V
7.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
tdis
PARAMETER
VCC = 2.5 V
± 0.2 V
MIN
MAX
Y
1.2
OE
Y
OE
Y
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
3.8
4
1.7
3.5
ns
1
5.7
5.7
1
4.8
ns
1
4.9
5.4
1.7
5.2
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
4
Power dissipation capacitance
per driver
TEST CONDITIONS
All outputs enabled
All outputs disabled
POST OFFICE BOX 655303
CL = 0
0,
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
49
53
6
7.5
UNIT
pF
SN74ALVCHS162830
1-BIT TO 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES097F – APRIL 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74ALVCHS162830
1-BIT TO 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES097F – APRIL 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
0V
0V
tsu
th
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
VOH
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
2.7 V
Output
Control
(low-level
enabling)
tPZL
2.7 V
Output
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
Data
Input
Input
1.5 V
1.5 V
Input
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1999, Texas Instruments Incorporated