Audio Driver for TV CXA3785R Description The CXA3785R is an integrated audio sub-system designed for TV audio application. It has a stereo headphone amplifier, and 4 stereo amplifiers. It also integrated gain control, mute control, input selector, and voltage detectors. Each settable value is controlled through I2C compatible interface. Features 4 stereo audio amplifiers (HP, AMP1, AMP2, AMP3) with programmable gain control Cap less headphone amplifier 2 amplifiers (HP and AMP1) with 3rd order LPF for PWM input AMP3 with 2 stereo input multiplexer and LL/RR output AMP4 for Digital Media Port (DMP) with differential input 4 voltage detection circuits for VUNREG (un-regulated power supply voltage), REGAUD (audio amp power supply voltage), REG33 (DSP power supply voltage) and speaker output 3 muting circuits with external mute control and buffer transistor REGAUD output for supply voltage of 4 stereo audio amplifiers and DMP REG33 output for supply voltage of DSP and PWM output stage I2C control Package size: 64pin LQFP (Body size: 10mm × 10mm) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E08906 CXA3785R Absolute Maximum Ratings Item Supply voltage Symbol Rating Unit VCC 24.0 V VUNREG 24.0 V DVDD 4.5 V Operating temperature range TA –25 to +85 °C Storage temperature range Tstg –55 to +125 °C Junction temperature TJ(max) +125 °C Power dissipation PD (TJ(max) – TA) / θJA*1 — θJA 80 °C/W θJC 20 °C/W Thermal impedance *1 Glass fabric base epoxy two-layer board, 76mm × 114mm, t = 1.6mm Recommended Operating Conditions Item Supply voltage Operating ambient temperature Symbol Min. Typ. Max. VCC 8.0 12.0 13.0 VCC = REGAUD V VUNREG 11.5 15.0 18.0 VUNREG – REGAUD ≥ 2.5V V DVDD 3.0 3.3 3.6 V Topt –25 — +85 °C -2- Condition Unit CXA3785R DGND DVDD MTSEL_CNT MT_CNT VFAULT X_PROTECTOUT AMP4INR_P AMP4INR_N AMP4OUTR GND_AMP4 AMP4OUTL VCC_AMP4 AMP4INL_P AMP4INL_N SEL2INR SEL1INR Block Diagram 48 47 46 45 44 43 42 41 40 39 23 37 36 35 34 33 SCL 49 32 VCC_AMP3 AMP4 (Differential input amp) BGR Logic REG33 51 31 AMP3OUTR SELECTOR 4:1 SDA 50 30 GND_AMP3 AMP3AG (+4 to +16dB/1dB) SELECTOR 4:1 REG33NFB 52 GND_REF 53 BGR 28 SEL2INL DETAUD REGAUD 54 27 SEL1INL Bandgap reference VUNREG_REF 55 29 AMP3OUTL 26 CREFH DETUNREG Current reference 30kΩ AMP1_MT 56 DET33 AMP2_MT 57 25 CREF 30kΩ 24 REF Mute control 60kΩ 23 VCC_AMP2 AMP3_MT 58 VUNREG_MT 59 SPDET_L 22 AMP2INR SPDET_R 3rd order LPF GND_MT 60 3rd order LPF SPLN 61 SPLP 62 3rd order LPF 21 AMP2OUTR AMP2AG (+4 to +16dB/1dB) 3rd order LPF 20 GND_AMP2 19 AMP2OUTL REF SPRN 63 18 AMP2INL AMP1AG (+4 to +16dB/1dB) HPAG (+8 to +20dB/1dB) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HPINL_P HPOUTL GND_HP HPBIASOUT VCC_HP HPOUTR HPINR_N HPINR_P AMP1INL_N AMP1INL_P VCC_AMP1 AMP1OUTL GND_AMP1 AMP1OUTR AMP1INR_N 17 AMP1INR_P HPINL_N SPRP 64 -3- CXA3785R Pin Description Pin No. Pin name Direction Description 1 HPINL_N I Headphone amp Lch negative input 2 HPINL_P I Headphone amp Lch positive input 3 HPOUTL O Headphone amp Lch output 4 GND_HP — Headphone amp GND 5 HPBIASOUT O Headphone amp bias output 6 VCC_HP — Headphone amp power 7 HPOUTR O Headphone amp Rch output 8 HPINR_N I Headphone amp Rch negative input 9 HPINR_P I Headphone amp Rch positive input 10 AMP1INL_N I AMP1 Lch negative input 11 AMP1INL_P I AMP1 Lch positive input 12 VCC_AMP1 — AMP1 power 13 AMP1OUTL O AMP1 Lch output 14 GND_AMP1 — AMP1 GND 15 AMP1OUTR O AMP1 Rch output 16 AMP1INR_N I AMP1 Rch negative input 17 AMP1INR_P I AMP1 Rch positive input 18 AMP2INL I AMP2 Lch input 19 AMP2OUTL O AMP2 Lch output 20 GND_AMP2 — AMP2 GND 21 AMP2OUTR O AMP2 Rch output 22 AMP2INR I AMP2 Rch input 23 VCC_AMP2 — AMP2 power 24 REF O All Amp reference 25 CREF O Reference capacitor 26 CREFH O “H” reference capacitor 27 SEL1INL I AMP3 Lch selector input 1 28 SEL2INL I AMP3 Lch selector input 2 29 AMP3OUTL O AMP3 Lch output 30 GND_AMP3 — AMP3 GND 31 AMP3OUTR O AMP3 Rch output 32 VCC_AMP3 — AMP3 power 33 SEL1INR I AMP3 Rch selector input 1 34 SEL2INR I AMP3 Rch selector input 2 35 AMP4INL_N I AMP4 Lch negative input 36 AMP4INL_P I AMP4 Lch positive input 37 VCC_AMP4 — AMP4 power -4- CXA3785R Pin No. Pin name Direction Description 38 AMP4OUTL O AMP4 Lch output 39 GND_AMP4 — AMP4 GND 40 AMP4OUTR O AMP4 Rch output 41 AMP4INR_N I AMP4 Rch negative input 42 AMP4INR_P I AMP4 Rch positive input 43 X_PROTECTOUT O Protect signal output 44 VFAULT I Fault signal input 45 MT_CNT I All amp mute control signal input 46 MTSEL_CNT I Selected amp mute control signal input 47 DVDD — Logic power 48 DGND — Logic GND 49 SCL I I2C clock 50 SDA I/O I2C data 51 REG33 O REG33 external FET control signal output 52 REG33NFB O REG33 negative feedback output 53 GND_REF — Reg/reference GND 54 REGAUD O Regulator output for audio amp 55 VUNREG_REF — Un-regulated power for reg/reference 56 AMP1_MT O AMP1 mute control signal output 57 AMP2_MT O AMP2 mute control signal output 58 AMP3_MT O AMP3 mute control signal output 59 VUNREG_MT — Un-regulated power for mute circuit 60 GND_MT — Mute circuit GND 61 SPLN I Speaker Lch negative input 62 SPLP I Speaker Lch positive input 63 SPRN I Speaker Rch negative input 64 SPRP I Speaker Rch positive input -5- CXA3785R Pin Circuit Pin Symbol Equivalent circuit VCC_HP REF VCC_HP 20pF 20kΩ 20kΩ 30kΩ 20kΩ 2 1 2 8 9 HPINL_N HPINL_P HPINR_N HPINR_P 28pF 9 VCC_HP 28pF 20kΩ 20kΩ 20kΩ 3pF GND_HP 20pF VCC_HP 30kΩ 2.5kΩ 2.5kΩ 1 3pF 8 GND_HP GND_HP VCC_HP VCC_HP VCC_HP 10pF 5kΩ 3 7 HPOUTL HPOUTR 3 5kΩ 20pF 100kΩ 10pF 20Ω 7 24.9kΩ GND_HP GND_HP GND_HP GND_HP REF VCC_HP VCC_HP VCC_HP 5 8pF 8pF 1kΩ 1kΩ 1kΩ 1kΩ 8pF 8pF HPBIASOUT 5 50Ω GND_HP GND_HP -6- GND_HP GND_HP CXA3785R Pin Symbol Equivalent circuit VCC_AMP1 REF VCC_AMP1 20pF 20kΩ 20kΩ 30kΩ 20kΩ 11 10 11 16 17 AMP1INL_N AMP1INL_P AMP1INR_N AMP1INR_P 28pF 17 20kΩ VCC_AMP1 28pF 20kΩ 20kΩ GND_HP 3pF 30kΩ 20pF VCC_HP 2.5kΩ 2.5kΩ 10 3pF 16 GND_AMP1 GND_AMP1 VCC_AMP1 VCC_AMP1 VCC_AMP1 10pF 13 15 AMP1OUTL AMP1OUTR 10pF 1kΩ 1kΩ 1kΩ 1kΩ 13 10pF 50pF 20Ω 40kΩ 15 10pF 18kΩ GND_AMP1 GND_AMP1 GND_AMP1 GND_AMP1 REF VCC_AMP2 VCC_AMP2 18 22 AMP2INL AMP2INR 18 60kΩ 22 REF GND_AMP2 VCC_AMP2 VCC_AMP2 VCC_AMP2 19 21 AMP2OUTL AMP2OUTR 10pF 10pF 1kΩ 1kΩ 1kΩ 1kΩ 10pF 10pF 19 40kΩ 50pF 18kΩ GND_AMP2 GND_AMP2 REF -7- GND_AMP2 21 CXA3785R Pin Symbol Equivalent circuit VCC_AMP2 VCC_AMP2 VCC_AMP2 24 REF 24 5kΩ GND_AMP2 GND_AMP2 VCC_AMP2 VCC_AMP2 26 30kΩ 30kΩ 25 26 CREF CREFH GND_AMP2 VCC_AMP2 60kΩ GND_AMP2 25 GND_AMP2 VCC_AMP3 VCC_AMP3 27 28 33 34 SEL1INL SEL2INL SEL1INR SEL2INR 27 28 60kΩ 33 34 REF GND_AMP3 VCC_AMP3 VCC_AMP3 VCC_AMP3 29 31 AMP3OUTL AMP3OUTR 10pF 10pF 1kΩ 1kΩ 1kΩ 1kΩ 29 10pF 10pF 50pF 40kΩ 18kΩ 20Ω GND_AMP3 GND_AMP3 GND_AMP3 GND_AMP3 REF -8- 31 CXA3785R Pin Symbol Equivalent circuit VCC_AMP4 REF VCC_AMP4 15pF 42.48kΩ 60kΩ 36 35 36 41 42 AMP4INL_N AMP4INL_P AMP4INR_N AMP4INR_P VCC_AMP4 42 VCC_AMP4 60kΩ GND_AMP4 15pF 10pF 2pF 1kΩ 1kΩ 1kΩ 1kΩ 10pF 2pF 42.48kΩ VCC_AMP4 35 41 VCC_AMP4 GND_AMP4 GND_AMP4 GND_AMP4 VCC_AMP4 VCC_AMP4 38 40 AMP4OUTL AMP4OUTR 2pF 10pF 1kΩ 1kΩ 1kΩ 1kΩ 2pF 10pF 38 42.48kΩ 15pF 60kΩ GND_AMP4 GND_AMP4 GND_AMP4 35 GND_AMP4 20Ω 41 DVDD DVDD 43 X_PROTECTOUT 43 DGND DGND DVDD DVDD DVDD DVDD 400kΩ 44 VFAULT 44 1MΩ 200kΩ DGND DGND -9- DGND 40 CXA3785R Pin Symbol Equivalent circuit DVDD DVDD 45 46 MT_CNT MTSEL_CNT 45 46 100kΩ DGND DGND DGND DVDD 500Ω 49 SCL 49 DGND DGND DVDD 500Ω 50 DVDD 50 SDA 2kΩ DGND 10kΩ 2pF DGND DGND DGND VUNREG_REF VUNREG_REF 1kΩ 51 REG33 51 2.5kΩ 10pF GND_REF GND_REF VUNREG_REF VUNREG_REF 52 52 REG33NFB 40kΩ 26kΩ GND_REF GND_REF - 10 - CXA3785R Pin Symbol Equivalent circuit VUNREG_REF VUNREG_REF VUNREG_REF 10pF 54 40kΩ 54 REGAUD 56kΩ GND_REF GND_REF GND_REF VUNREG_MT 60kΩ 56 57 58 AMP1_MT AMP2_MT AMP3_MT VUNREG_MT 56 120kΩ 57 58 GND_MT REGAUD VUNREG_MT 61 62 63 64 SPLN SPLP SPRN SPRP 61 62 63 150kΩ 64 GND_MT - 11 - CXA3785R Block Diagram (Regulator, Reference) VUNREG_REF BGR REG33 2SJ668 REG33NFB 10µF GND_REF Bandgap reference Current reference GND_REF VUNREG_REF REGAUD 100µF GND_REF REGAUD[1:0] 9V to 12V/1V GND_REF - 12 - CXA3785R Electrical Spec. (HP Amp) Electrical Characteristics (Regulator, Reference) (Unless otherwise specified; Ta = 25°C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item REG33NFB output voltage Symbol Condition Min. Typ. Max. Unit 3.0 3.3 3.6 V VREG33NFB ILOAD = 1mA VREG33SW1 ILOAD = 1mA, REG33NFB = REG33NFB (ILOAD = 1mA) + 25mV VUNREG – 2.0 VUNREG – 1.0 — V VREG33SW2 ILOAD = 1mA, REG33NFB = REG33NFB (ILOAD = 1mA) – 25mV — 3.0 6.0 V IREG33SOURCE ILOAD = 1mA, REG33 = 10V, REG33NFB = REG33NFB (ILOAD = 1mA) + 25mV 10 20 40 μA REG33 sinking current IREG33SINK ILOAD = 1mA, REG33 = 10V REG33NFB = REG33NFB (ILOAD = 1mA) – 25mV 1.5 3.0 6.0 mA REGAUD output voltage 1 VAUD1 ILOAD = 100mA, VCC = REGAUD = 12V 11.0 12.0 13.0 V REGAUD output voltage 2 VAUD2 ILOAD = 100mA, VCC = REGAUD = 11V 10.0 11.0 12.0 V REGAUD output voltage 3 VAUD3 ILOAD = 100mA, VCC = REGAUD = 10V 9.0 10.0 11.0 V REGAUD output voltage 4 VAUD4 ILOAD = 100mA, VCC = REGAUD = 9V 8.0 9.0 10.0 V REGAUD load regulation VLO_AUD ILOAD = 1m – 100mA, VCC = REGAUD = 12V — — 0.3 V REGAUD line regulation VLI_AUD VUNREG = 14.5 – 18V, ILOAD = 100mA VCC = REGAUD = 12V — — 0.3 V REGAUD PSRR PSRRAUD ILOAD = 100mA 40 60 — dB CREF output voltage VCREF (VCC/2) × 0.9 VCC/2 (VCC/2) × 1.1 V CREFH output voltage VCREFH (3 × VCC/4) × 0.9 3 × VCC/4 (3 × VCC/4) × 1.1 V REF output voltage VREF (VCC/2) × 0.9 VCC/2 (VCC/2) × 1.1 V REG33 output voltage swing REG33 sourcing current - 13 - CXA3785R Design Procedure (REG33) Regulator Compensation VUNREG_REF The compensation network (C1, R1) is customizable and depends on load and MOSFET characteristics: VIN BGR FET REG33 REG33NFB C1 GND_REF R1 10µF GND_REF GND_REF Strength of the external p-channel MOSFET (gm), it's forward transconductance (gfs), and the gateto-source capacitance (Cgs). The driver transconductance (gmdrv) of the integrated circuit driver. Load current range (including the minimum load): Imin to Imax External MOSFET Selection The selected MOSFET must have a gate threshold voltage (at the required max load) that meets the following criteria: Vgs_min < VIN – VREG33SW2 - 14 - CXA3785R Block Diagram (HP Amp) 20pF 30kΩ 2.2µF 20kΩ 20kΩ 20kΩ VCC_HP VCC_HP HPINL_N HPINL_P 2.2µF 28pF 28pF 100Ω HPOUTL 20kΩ 20kΩ 20kΩ GND_HP 20pF 30kΩ GND_HP AMPEN HPAG[3:0] 8 to 20dB/1dB VCC_HP AMPEN GND_HP 30kΩ 2.2µF 20kΩ 20kΩ 20kΩ HPBIASOUT HPERR to detector block 20pF VCC_HP VCC_HP HPINR_N 2.2µF 28pF 28pF 100Ω HPINR_P HPOUTR 20kΩ 20kΩ 20kΩ VCC_AMP2 GND_HP 20pF 30kΩ AMPEN GND_HP HPAG[3:0] 8 to 20dB/1dB 30kΩ BIASEN CREFH 0.1µF 30kΩ VCC_AMP2 GND_AMP2 CREF REF 60kΩ 4.7µF GND_AMP2 10µF GND_AMP2 GND_AMP2 AMPEN GND_AMP2 - 15 - CXA3785R Electrical Spec. (HP Amp) Electrical Characteristics (HP Block) (Unless otherwise specified; Ta = 25°C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Symbol Condition Min. Typ. Max. Unit 48.0 60.0 72.0 kΩ (VCC/2) × 0.9 VCC/2 (VCC/2) × 1.1 V 8.0 — 20.0 dB 0 1.0 2.0 dB dB Input impedance RINHP Output DC voltage (HPOUT, HPBIASOUT) VOUTHP Gain = 14dB, AC coupled input Gain adjustment range GAINHP fsig = 1kHz Gain adjustment step STPHP LPF cutoff frequency LPFHP VO = 55kHz/1kHz –5.5 –3.0 –0.5 VOMHP_1 Gain = 14dB, THD = 1.0%, RL = 100Ω + 32Ω, VCC = REGAUD = 12.0V 2.8 — — VOMHP_2 Gain = 14dB, THD = 1.0%, RL = 100Ω + 32Ω, VCC = REGAUD = 9.0V 2.1 — — THD+N THDHP Gain = 14dB, LPF RL = 100Ω + 32Ω, VIN = 0.1Vrms — 0.10 0.50 % Output noise level VNHP Gain = 14dB, RL = 100Ω + 32Ω, Measured at RL of 32Ω — –92.0 –82.0 dBV Gain error GEHP Gain = 14dB, RL = 1kΩ –1.0 0 1.0 dB Channel separation CTHP Gain = 14dB, VIN = 0.4Vrms 70.0 80.0 — dB Mute level MTHP Gain = 14dB, Output level = 2.8Vrms — –90.0 –80.0 dB PSRR PSRRHP fsig = 1kHz 30.0 40.0 — dB Maximum output level - 16 - Vrms CXA3785R Block Diagram (AMP1 Amp) 20pF 30kΩ VCC_AMP1 2.2µF 20kΩ 20kΩ 20kΩ VCC_AMP1 AMP1INL_N 2.2µF AMP1OUTL 28pF 28pF 10µF AMP1INL_P 20kΩ 20kΩ 20kΩ 1kΩ GND_AMP1 20pF 30kΩ GND_AMP1 AMPEN AMP1AG[3:0] 4 to 16dB/1dB 20pF External audio power amplifier 30kΩ 2.2µF VCC_AMP1 20kΩ 20kΩ 20kΩ VCC_AMP1 AMP1INR_N 2.2µF AMP1OUTR 28pF 28pF 10µF AMP1INR_P 20kΩ 20kΩ 20kΩ 1kΩ VCC_AMP2 GND_AMP1 20pF 30kΩ AMPEN GND_AMP1 AMP1AG[3:0] 4 to 16dB/1dB 30kΩ BIASEN CREFH 0.1µF 30kΩ VCC_AMP2 GND_AMP2 CREF REF 4.7µF 60kΩ 10µF GND_AMP2 GND_AMP2 AMPEN GND_AMP2 - 17 - GND_AMP2 CXA3785R Electrical Spec. (AMP1 Amp) Electrical Characteristics (AMP1 Block) (Unless otherwise specified; Ta = 25°C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Symbol Condition Min. Typ. Max. Unit 48.0 60.0 72.0 kΩ (VCC/2) × 0.9 VCC/2 (VCC/2) × 1.1 V 4.0 — 16.0 dB 0 1.0 2.0 dB dB Input impedance RINAMP1 Output DC voltage VOUTAMP1 Gain = 10dB, AC coupled input Gain adjustment range GAINAMP1 fsig = 1kHz Gain adjustment step STPAMP1 LPF cutoff frequency LPFAMP1 VO = 55kHz/1kHz –5.5 –3.0 –0.5 VOMAMP1_1 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 12.0V 2.8 — — VOMAMP1_2 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 9.0V 2.1 — — THD+N THDAMP1 Gain = 10dB, RL = 1kΩ, VIN = 0.2Vrms — 0.01 0.10 % Output noise level VNAMP1 Gain = 10dB, RL = 1kΩ — –90.0 –80.0 dBV Gain error GEAMP1 Gain = 10dB, RL = 1kΩ –1.0 0 1.0 dB Channel separation CTAMP1 Gain = 10dB, VIN = 1.0Vrms 70.0 80.0 — dB PSRR PSRRAMP1 fsig = 1kHz 30.0 40.0 — dB Maximum output level - 18 - Vrms CXA3785R Block Diagram (AMP2 Amp) VCC_AMP2 2.2µF AMP2OUTL AMP2INL 10µF 60kΩ 1kΩ GND_AMP2 AMP2EN 2.2µF AMP2INR AMP2AG[3:0] 4 to 16dB/1dB External audio power amplifier VCC_AMP2 AMP2OUTR 10µF 60kΩ VCC_AMP2 GND_AMP2 AMP2EN AMP2AG[3:0] 4 to 16dB/1dB 1kΩ 30kΩ BIASEN CREFH 0.1µF 30kΩ VCC_AMP2 GND_AMP2 CREF REF 4.7µF 60kΩ 10µF GND_AMP2 GND_AMP2 AMPEN GND_AMP2 - 19 - GND_AMP2 CXA3785R Electrical Spec. (AMP2 Amp) Electrical Characteristics (AMP2 Block) (Unless otherwise specified; Ta = 25°C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Symbol Condition Input impedance RINAMP2 Output DC voltage VOUTAMP2 Gain = 10dB, AC coupled input Gain adjustment range GAINAMP2 fsig = 1kHz Gain adjustment step STPAMP2 Min. Typ. Max. Unit 48.0 60.0 72.0 kΩ (VCC/2) × 0.9 VCC/2 (VCC/2) × 1.1 V 4.0 — 16.0 dB 0 1.0 2.0 dB — — VOMAMP2_1 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 12.0V 2.8 VOMAMP2_2 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 9.0V 2.1 — — THD+N THDAMP2 Gain = 10dB, RL = 1kΩ, VIN = 0.2Vrms — 0.01 0.10 % Output noise level VNAMP2 Gain = 10dB, RL = 1kΩ — –95.0 –85.0 dBV Gain error GEAMP2 Gain = 10dB, RL = 1kΩ –1.0 0 1.0 dB Channel separation CTAMP2 Gain = 10dB, VIN = 1.0Vrms 70.0 80.0 — dB PSRR PSRRAMP2 fsig = 1kHz 30.0 40.0 — dB Maximum output level - 20 - Vrms CXA3785R Block Diagram (AMP3 Amp) VCC_AMP3 AMP3OUTL 2.2µF SEL1INL SEL2INL 10µF 2.2µF 1kΩ 60kΩ 60kΩ GND_AMP3 AMPEN AMP3AG[3:0] 4 to 16dB/1dB External audio power amplifier 2.2µF SEL1INR SEL2INR VCC_AMP3 AMP3OUTR 10µF 2.2µF 60kΩ 60kΩ 1kΩ VCC_AMP2 GND_AMP3 AMPEN AMP3AG[3:0] 4 to 16dB/1dB 30kΩ BIASEN CREFH 0.1µF 30kΩ VCC_AMP2 GND_AMP2 CREF REF 60kΩ 4.7µF GND_AMP2 10µF GND_AMP2 GND_AMP2 AMPEN GND_AMP2 - 21 - CXA3785R Electrical Spec. (AMP3 Amp) Electrical Characteristics (AMP3 Block) (Unless otherwise specified; Ta = 25°C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Symbol Condition Input impedance RINAMP3 Output DC voltage VOUTAMP3 Gain = 10dB, AC coupled input Gain adjustment range GAINAMP3 fsig = 1kHz Gain adjustment step STPAMP3 Min. Typ. Max. Unit 48.0 60.0 72.0 kΩ (VCC/2) × 0.9 VCC/2 (VCC/2) × 1.1 V 4.0 — 16.0 dB 0 1.0 2.0 dB — — VOMAMP3_1 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 12.0V 2.8 VOMAMP3_2 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 9.0V 2.1 — — THD+N THDAMP3 Gain = 10dB, RL = 1kΩ, VIN = 0.2Vrms — 0.01 0.10 % Output noise level VNAMP3 Gain = 10dB, RL = 1kΩ — –95.0 –85.0 dBV Gain error GEAMP3 Gain = 10dB, RL = 1kΩ –1.0 0 1.0 dB Channel separation CTAMP3 Gain = 10dB, VIN = 1.0Vrms 70.0 80.0 — dB PSRR PSRRAMP3 fsig = 1kHz 30.0 40.0 — dB Maximum output level - 22 - Vrms CXA3785R Block Diagram (AMP4 Amp) 15pF 42.48kΩ VCC_AMP4 2.2µF 60kΩ 2.2µF 60kΩ AMP4OUTL AMP4INL_N 10µF AMP4INL_P 20kΩ AMPEN GND_AMP4 15pF 42.48kΩ External audio power amplifier 15pF 42.48kΩ 2.2µF 60kΩ 2.2µF 60kΩ VCC_AMP4 AMP4OUTR AMP4INR_N 10µF AMP4INR_P 20kΩ VCC_AMP2 AMPEN GND_AMP4 15pF 42.48kΩ BIASEN 30kΩ CREFH 0.1µF 30kΩ VCC_AMP2 GND_AMP2 CREF REF 60kΩ 4.7µF GND_AMP2 10µF GND_AMP2 GND_AMP2 AMPEN GND_AMP2 - 23 - CXA3785R Electrical Spec. (AMP4 Amp) Electrical Characteristics (AMP4 Block) (Unless otherwise specified; Ta = 25°C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Symbol Condition Min. Typ. Max. Unit 48.0 60.0 72.0 kΩ (VCC/2) × 0.9 VCC/2 (VCC/2) × 1.1 V dB Input impedance RINAMP4 Output DC voltage VOUTAMP4 AC coupled input Gain GAINAMP4 Single Input, fsig = 1kHz –4.0 –3.0 –2.0 VOMAMP4_1 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 12.0V 2.8 — — VOMAMP4_2 Gain = 10dB, THD = 1.0%, RL = 1kΩ VCC = REGAUD = 9.0V 2.1 — — THD+N THDAMP4 RL = 20kΩ, VIN = 1.0Vrms — 0.01 0.10 % Output noise level VNAMP4 RL = 20kΩ — –95.0 –85.0 dBV Gain error GEAMP4 RL = 20kΩ –1.0 0 1.0 dB Channel separation CTAMP4 VIN = 1.0Vrms 70.0 80.0 — dB PSRR PSRRAMP4 fsig = 1kHz 30.0 40.0 — dB Maximum output level - 24 - Vrms CXA3785R Block Diagram (Detector) VUNREG_REF DETUNREG[1:0] 6.0V to 12.0V/2.0V DVDD DETUNREG GND_MT GND_MT VCC_AMP2 DETAUD GND_MT GND_MT REG33NFB DVDD DET33 GND_MT GND_MT HPBIAS HPBIAS grounding error Reset logic HPERREN Power amplifier X_PROTECTOUT VFAULT µCOM PROMSK "L": Error "H": Normal REGAUD SPDETL 100kΩ SPLN 100kΩ Power amplifier 150kΩ SPLP 150kΩ 4.7µF GND_MT GND_MT REGAUD SPDETR 100kΩ SPRN 100kΩ Power amplifier SPRP 150kΩ 4.7µF 150kΩ "L": Normal "H": Error GND_MT GND_MT - 25 - CXA3785R Block Diagram (Mute Control) µCOM MT_CNT MTSEL_CNT VUNREG_MT AMP1_MT AMP1MTSEL AMP1OUT AMP1MT DETUNREG GND_MT VUNREG_MT AMP2_MT AMP2MTSEL AMP2OUT AMP2MT GND_MT VUNREG_MT AMP3MTSEL AMP3_MT AMP3OUT AMP3MT GND_MT - 26 - CXA3785R Electrical Spec. (Detector 1) Electrical Characteristics (Detector Block1) (Unless otherwise specified; Ta = 25°C, VCC = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Detection voltage 1_1 Symbol *1 VDET1_1 Condition Min. Typ. Max. VUNREG voltage detection (set: 6.0V) 4.8 6.0 6.6 — — 7.0 VUNREG voltage detection (set: 8.0V) 7.0 8.0 8.8 — — 9.5 VUNREG voltage detection (set: 10.0V) 9.0 10.0 11.0 — — 12.0 VUNREG voltage detection (set: 12.0V) 10.8 12.0 13.2 — — 14.0 5.4 6.0 6.6 — — 7.0 1.44 1.60 1.76 — — 1.80 Unit V Release voltage 1_1 *1 VREL1_1 Detection voltage 1_1 VDET1_1 Release voltage 1_1 VREL1_2 Detection voltage 1_2 VDET1_3 Release voltage 1_2 VREL1_3 Detection voltage 1_3 VDET1_4 Release voltage 1_3 VREL1_4 Detection voltage 2 VDET2 Release voltage 2 VREL2 Detection voltage 3 VDET3 Release voltage 3 VREL3 Minimum input voltage (SPP/N) VIN_SPP/N SPP/N minimum input voltage 3.0 — — V Detection voltage 4_2*2,*3 VDET4 Speaker out (|SPP – SPN|) voltage detection Rin = 100kΩ + 150kΩ Input voltage (SPxP/N) is over 3.0V necessary. 1.10 1.45 1.80 V Detection voltage 5 VDET5 HPBIAS voltage detection, HPERREN = “1” 1.50 2.50 3.50 V *1 *2 *3 REGAUD voltage detection REG33NFB voltage detection This is not tested. Therefore the characteristics is guaranteed by design. X_PROTECTOUT outputs “L” when input voltage (SPxP/N) become under 3.0V. Next page shows the measurement circuit example. - 27 - V V V V V CXA3785R SPDET Measurement Circuit REGAUD SPDETx 100kΩ SPxN 150kΩ 100kΩ SPK_SPxN SPK_SPxP 150kΩ SPxP GND_MT GND_MT Input pin (SPxN/P) is should be biased to over 3.0V. Electrical Spec. (Detector 2) Electrical Characteristics (Detector Block2) (Unless otherwise specified; Ta = 25°C, VCC = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Symbol Condition Min. Typ. Max. Unit VFAULT High level input voltage VFAULTH Input: High level 2.5 — 18.0 V VFAULT Low level input voltage VFAULTL Input: Low level 0 — 0.5 V X_PROTECTOUT High level output voltage VOPROH Output: High level, RL = 1MΩ 2.5 — DVDD V X_PROTECTOUT Low level output voltage VOPROL Output: Low level, RL = 1MΩ 0 — 0.5 V MT_CNT / MTSEL_CNT High level input voltage VIMT_CNT Input: High level 2.5 — DVDD V MT_CNT / MTSEL_CNT Low level input voltage VIMT_CNT Input: Low level 0 — 0.5 V MT output voltage (Low: OFF) VMT_L Rout = 10kΩ — 0 0.5 V MT output voltage (High: ON) VMT_H Rout = 10kΩ 13.0 VUNREG — V MT output current (OFF) IOMTH Rout = 10kΩ — 0 3.0 μA MT output current (ON) IOMTL Rout = 10kΩ 1.4 1.5 — mA - 28 - CXA3785R Detector Waveform VUNREG_REF (Pin; DETUNREG) VCC_AMP2 (Pin; DETAUD) REG33 (Pin; DET33) HPBIAS (Pin) Detect Voltage 6V 1.6V 2.5V Detect Voltage SPDETL/R (Pin: SP(L/R) P-SP(L/R)N) VFAULT (Pin) DETUNREG[1:0] (Register) Default Det. voltage setting Default PROMSK (Register) HPERREN (Register) X_PROTECTOUT (External Output Pin) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Description of Detector Waveform (1) to (8) Despite each voltage falls below detect voltage, X_PROTECTOUT keeps "H" because PROMSK is "H". (9) (10) (11) (12) (13) (14) (15) (16) When difference voltage between SPxP and SPxN rise over detect voltage, X_PROTECTOUT is "L". Same as (9). When VUNREG_REF is falls below detect voltage, X_PROTECTOUT is "L". When VCC_AMP2 falls below the detect voltage, X_PROTECTOUT is "L". When REG33 falls below the DETAUD detect voltage, X_PROTECTOUT is "L". When HPBIAS falls below the detect voltage but HPEREN is "L", X_PROTECTOUT keeps "H". When HPBIAS falls below the detect voltage, X_PROTECTOUT is "L". When VFAULT is "H", X_PROTECTOUT is "L". - 29 - CXA3785R Mute Control Waveform VUNREG_REF (Pin) MT_CNT (Pin) MTSEL_CNT (Pin) HPMTCNT (Register) AMP1MT (Register) AMP2MT (Register) AMP3MT (Register) HPMTSEL (Register) AMP1MTSEL (Register) AMP2MTSEL (Register) AMP3MTSEL (Register) HPMT (Internal) AMP1_MT (Pin) AMP2_MT (Pin) AMP3_MT (Pin) Un-Mute Mute Un-Mute Mute Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z (1) Un-Mute Mute Hi-Z Hi-Z Hi-Z Hi-Z (2) (3) (4) (6) When MT_CNT is "L", all amp output is muted except for AMP4. When MTSEL_CNT is "L" and XXSEL is "H", XXAMP output is muted. When MTSEL_CNT is "L" and XXSEL is "L", XXAMP keeps un-mute. When HPMTCNT is "H", HPAMP output is muted. When AMP1MTCNT is "H", AMP1AMP output is muted. When AMP2MTCNT is "H", AMP2AMP output is muted. When AMP3MTCNT is "H", AMP3AMP output is muted. When VUNREG_REF is fall below the VUNREG detector voltage, all amp output is muted except for AMP4. - 30 - Hi-Z Hi-Z (5) Hi-Z Hi-Z Hi-Z Description of Mute Control Waveform (1) (2) (3) (4) (5) (6) (7) (8) Mute Un-Mute (7) Hi-Z (8) CXA3785R Amp Sequence with Mute Transistor (HP, AMP1-3) REGAUD 9V 12V 9V (Register) OFF ON OFF AMPEN OFF ON OFF 0dB XXdB 0dB MUTE UN-MUTE MUTE (Register) BIASEN (Register) HPAG (Register) HPMTCNT (Register) >1s >1ms HPOUT (Pin) (1) (1) (2) (3) (4) (2) (3)(4) BIASEN and AMPEN set on, REGAUD and HPAG set intended value. MTCNT should be set un-mute at least 1s after (1). When shut off the AMP, MTCNT should be set mute at first. All settings set off or set default at least 1ms after (3). - 31 - CXA3785R Amp Sequence without Mute Transistor (HP) REGAUD (Register) BIASEN (Register) AMPEN (Register) HPAG (Register) HPMTCNT (Register) 9V 12V 9V OFF ON OFF OFF ON OFF 0dB XXdB 0dB MUTE UN-MUTE MUTE >1ms >2s >1ms >1ms HPOUT (Pin) (1)(2) (1) (2) (3) (4) (5) (3) (4)(5)(6) REGAUD set intended value and BIASEN set on. AMPEN should be set on at least 1ms after (1). HPAG set intended value and HPMTCNT set un-mute at least 2s after (2). When shut off HPAMP, first HPAG set 0dB and HPMTCNT set mute at the same time. BIASEN and AMPEN set off at least 1ms after (4). (6) REGAUD set default value at least 1ms after (5) if needed. - 32 - CXA3785R Power-On/Power-Off Sequence Recommended Power-On Sequence VUNREG REGAUD DVDD Internal RST >1ms I2C should be controlled at least 1ms after DVDD is supplied. Power-Off Sequence (with Mute Transistor) Power-Off Sequence (without Mute Transistor) VUNREG VUNREG REGAUD REGAUD DVDD DVDD >1ms >2s VUNREG should be turn off at least 1ms after DVDD turn off. - 33 - DVDD should be turn off at least 2s after VUNREG turn off. CXA3785R Electrical Spec. (I2C BUS Block) Electrical Characteristics (I2C BUS Block) (Unless otherwise specified; Ta = 25°C, VCC = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Symbol Condition Min. Typ. Max. Unit High level input voltage VIH 2.5 — DVDD V Low level input voltage VIL 0 — 0.5 V High level input current IIH — — 10.0 μA Low level input current IIL — — 10.0 μA Low level output voltage VOL 0 — 0.4 V Clock frequency fSCL 0 — 400 kHz Data change minimum waiting time tBUF 1.3 — — μs Data transfer start waiting time tHD;STA 0.6 — — μs Low level clock pulse width tLOW 1.3 — — μs High level clock pulse width tHIGH 0.6 — — μs Start setup waiting time tSU;STA 0.6 — — μs Data hold time tHD;DAT 0 — — μs Data setup time tSU;DAT 100 — — ns Rise time tR — — 300 ns Fall time tF — — 300 ns Stop setup waiting time tSU;STO 0.6 — — μs with SDA 3mA current supplied SDA tBUF tR tF SCL tHD;STA tLOW P tHD;DAT tHIGH S tSU;DAT tSU;STA S Fig. I2C BUS Control Signal Timing Chart - 34 - tSU:STO P CXA3785R 43 42 40 49 39 23 37 36 BGR 2.2µF 33 31 1kΩ SELECTOR 4:1 M 53 BGR 29 2.2µF 2.2µF Bandgap reference 0.1µF 26 DETUNREG Current reference M 56 M DET33 57 1kΩ 27 M 55 10µF 28 DETAUD 54 10µF 30 AMP3AG (+4 to +16dB/1dB) 52 100µF 34 32 Logic 51 10µF 35 AMP4 (Differential input amp) 50 2SJ668 2.2µF 2.2µF 2.2µF 10µF 10µF 41 M 44 M 45 SELECTOR 4:1 4.7µF 30kΩ 25 30kΩ Over 10µF 24 Mute control 60kΩ M 23 58 2.2µF 22 SPDET_R 3rd order LPF 60 100kΩ 21 10µF 1kΩ AMP2AG (+4 to +16dB/1dB) 3rd order LPF 3rd order LPF 61 3rd order LPF 20 10µF 100kΩ 100kΩ 62 19 REF 2.2µF 63 18 AMP1AG (+4 to +16dB/1dB) 2.2µF HPAG (+8 to +20dB/1dB) 64 17 100kΩ M 32Ω 10 11 12 13 1kΩ M - 35 - 14 15 M 16 2.2µF 32Ω 9 10µF M 8 2.2µF 7 2.2µF 6 2.2µF 5 2.2µF 4 100Ω 3 100Ω 2 2.2µF 2.2µF 1 M SPDET_L M M 59 1kΩ DVDD DVDD M 46 2.2µF 2.2µF M Rp 47 M I2C control 48 Rp 20kΩ 20kΩ Measurement Circuit 1kΩ CXA3785R I2C BUS Interface Description The bus protocol conforms to the I2C bus specifications, but the following restrictions are applied. Bus slave operation only Supports fast mode only The general call address and start byte of the slave address are not supported. CBUS compatibility is not supported. 10-bit slave addresses are not supported. Write mode and read mode (only 1bit: sub add “00”, S7) are supported. Slave Address Transmit the 7-bit slave address and the 1-bit read/write code following the START condition. Write operation to this IC is allowed only when the input slave address and the device code match. When the slave address dose not match the device code, an ACK (acknowledge response) is not generated and the IC dose not respond. Slave Address Slave address word (8bits) R/W code (fixed) Device code (fixed) S7 S6 S5 S4 S3 S2 S1 S0 1 0 0 1 1 1 0 0/1 - 36 - CXA3785R Register Function (Write Register) Write Cycle After providing slave address from master, set next transfer cycle data as write start sub address of control register to internal control register address. After that, cycle write the data providing from master to sub address indicated by control register address. Designated control register address is incremented automatically every one byte transfer completion. See the control register map for writable control register. 1 1 0 0 S6 S5 S4 S3 S2 S1 R/W Start sub address Write data STOP Write data ACK 1 ACK 0 ACK 0 ACK 1 S7 START Slave address from Master to Slave from Slave to Master - 37 - CXA3785R Register Function (Read Register) Read Cycle The sub address that can read is only 00hex. To be operated read, transfer sub address (00hex) in the same procedure of write cycle. After that, re-transfer slave address from master in read mode and then the CXA3785R is in a read mode, data from sub address (00hex) accessed by control register address is returned to host. Also, data from sub address (00hex) is returned to host continuously, until stop condition is transferred. 0 S2 S1 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 S7 S6 S5 S4 S3 S2 S1 R/W 0 0 0 0 0 0 0 0 0 0 0 0 1 STOP 0 0 ACK 1 RTEST 0 RTEST 0 ACK 1 D7 RTEST Read data Slave address START 0 STOP 0 ACK 1 ACK 1 ACK 1 S3 S6 0 S4 0 Sub address S5 1 S7 START Slave address from Master to Slave from Slave to Master - 38 - CXA3785R Register Map Write Register Address 00 R/W Default Address Register name AMP ENABLE PROTECTOR READ REGISTER Register name D7 RTEST HP/AMP1 GAIN Register name AMP2/AMP3 GAIN Register name 03 R/W Default Address Register name 04 R/W Default D0 AMPEN W W W W 0 0 1 1 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 AMP1AG[3:0] W W W W W W W W 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 AMP3AG[3:0] W W W W W W W W 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 AMP3SEL_L[1:0] REGAUD[1:0] DETUNREG[1:0] W W W W W W W W 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 HPMTSEL AMP1MTSEL AMP2MTSEL AMP3MTSEL HPMTCNT AMP1MT MUTE CONTROL D1 W AMP3SEL_R[1:0] DETUNREG AMP3SEL D2 W AMP2AG[3:0] Default Address D3 W 02 R/W D4 HPAG[3:0] Default Address D5 R/W 01 R/W D6 AMP2EN PROMSK HPERREN HPOLPEN REGOLPEN BIASEN D1 D0 AMP2MT AMP3MT W W W W W W W W 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 RTEST 0 0 0 0 0 0 0 Read Register Address 00 Register name READ REGISTER - 39 - CXA3785R Register Function (ADD: 00) Address 00 R/W Default Register name AMP ENABLE PROTECTOR READ REGISTER D7 D6 D5 D4 D3 RTEST AMP2EN R/W W W W W 0 0 1 1 1 D2 D1 D0 BIASEN AMPEN W W W 1 0 0 PROMSK HPERREN HPOLPEN REGOLPEN D7: RTEST Read register D6: AMP2EN AMP2 enable “0” OFF (default) “1” ON D5: PROMSK X_PROTECTOUT mask control “0” Mask OFF “1” Mask ON (default) (X_PROTECTOUT function OFF) D4: HPERREN HP bias short error to VFAULT enable “0” OFF “1” ON (default) D3: HPOLPEN HP bias over load protect “0” OFF “1” ON (default) D2: REGOLPEN REGAUD over load protect “0” OFF “1” ON (default) D1: BIASEN Amp bias enable “0” OFF (default) “1” ON D0: AMPEN HPAMP, AMP1, AMP3, AMP4 enable “0” OFF (default) “1” ON - 40 - CXA3785R Register Function (ADD: 01) Address Register name D7 01 R/W D6 D5 D4 D3 HPAG[3:0] HP/AMP1 GAIN Default D2 D1 D0 AMP1AG[3:0] W W W W W W W W 0 0 0 0 0 0 0 0 D7-4: HPAG[3:0] HP gain control “0000” 0dB (default) “0001” 8dB “0010” 9dB “0011” 10dB “0100” 11dB “0101” 12dB “0110” 13dB “0111” 14dB “1000” 15dB “1001” 16dB “1010” 17dB “1011” 18dB “1100” 19dB “1101” 20dB “1110” Don’t care “1111” Don’t care D3-0: AMP1AG[3:0] AMP1 gain control “0000” 0dB (default) “0001” 4dB “0010” 5dB “0011” 6dB “0100” 7dB “0101” 8dB “0110” 9dB “0111” 10dB “1000” 11dB “1001” 12dB “1010” 13dB “1011” 14dB “1100” 15dB “1101” 16dB “1110” Don’t care “1111” Don’t care - 41 - CXA3785R Register Function (ADD: 02) Address Register name D7 02 R/W D6 D5 D4 D3 AMP2AG[3:0] AMP2/AMP3 GAIN Default D2 D1 D0 AMP3AG[3:0] W W W W W W W W 0 0 0 0 0 0 0 0 D7-4: AMP2AG[3:0] AMP2 gain control “0000” 0dB (default) “0001” 4dB “0010” 5dB “0011” 6dB “0100” 7dB “0101” 8dB “0110” 9dB “0111” 10dB “1000” 11dB “1001” 12dB “1010” 13dB “1011” 14dB “1100” 15dB “1101” 16dB “1110” Don’t care “1111” Don’t care D3-0: AMP3AG[3:0] AMP3 gain control “0000” 0dB (default) “0001” 4dB “0010” 5dB “0011” 6dB “0100” 7dB “0101” 8dB “0110” 9dB “0111” 10dB “1000” 11dB “1001” 12dB “1010” 13dB “1011” 14dB “1100” 15dB “1101” 16dB “1110” Don’t care “1111” Don’t care - 42 - CXA3785R Register Function (ADD: 03) Address Register name 03 R/W D7 D6 AMP3SEL_R[1:0] DETUNREG AMP3SEL D5 D4 AMP3SEL_L[1:0] D3 D2 REGAUD[1:0] D1 D0 DETUNREG[1:0] W W W W W W W W 0 0 0 0 0 0 0 0 Default D7-6: AMP3SEL_R[1:0] AMP3 Rch selector control “00” SEL1INL (default) “01” SEL2INL “10” SEL1INR “11” SEL2INR D5-4: AMP3SEL_L[1:0] AMP3 Lch selector control “00” SEL1INL (default) “01” SEL2INL “10” SEL1INR “11” SEL2INR D3-2: REGAUD[1:0] REGAUD output voltage control “00” 9V (default) “01” 10V “10” 11V “11” 12V D1-0: DETUNREG[1:0] UNREG detector voltage control “00” 6V (default) “01” 8V “10” 10V “11” 12V - 43 - CXA3785R Register Function (ADD: 04) Address Register name 04 R/W D7 D6 D5 D4 D3 D2 HPMTSEL AMP1MTSEL AMP2MTSEL AMP3MTSEL HPMTCNT AMP1MT MUTE CONTROL Default D1 D0 AMP2MT AMP3MT W W W W W W W W 0 0 0 0 0 0 0 0 D7: HPMTSEL HP select mute control “0” no select (default) “1” select D6: AMP1MTSEL AMP1 select mute control “0” no select (default) “1” select D5: AMP2MTSEL AMP2 select mute control “0” no select (default) “1” select D4: AMP3MTSEL AMP3 select mute control “0” no select (default) “1” select D3: HPMTCNT HP mute control “0” Mute (default) “1” Un-mute D2: AMP1MT AMP1 mute control “0” Mute (default) “1” Un-mute D1: AMP2MT AMP2 mute control “0” Mute (default) “1” Un-mute D0: AMP3MT AMP3 mute control “0” Mute (default) “1” Un-mute - 44 - CXA3785R Register Function (Read Register) Address Register name D7 D6 D5 D4 D3 D2 D1 D0 00 READ REGISTER RTEST 0 0 0 0 0 0 0 D7: RTEST Read register - 45 - CXA3785R Application Circuit External audio power amplifier 47 46 45 44 43 42 40 39 23 37 36 35 2.2µF 2.2µF 2.2µF 2.2µF REGAUD 10µF 10µF 41 34 33 49 32 AMP4 (Differential input amp) Rp 50 BGR 10µF Logic 51 30 AMP3AG (+4 to +16dB/1dB) 52 53 BGR VCC_XXXX 100µF 31 SELECTOR 4:1 2SJ668 10µF 29 2.2µF 28 DETAUD 54 27 Bandgap reference 55 AMP1OUT REGAUD 10µF 0.1µF Current reference 4.7µF 30kΩ 56 25 30kΩ DET33 57 2.2µF 26 DETUNREG AMP2OUT External audio power amplifier Rp SELECTOR 4:1 DVDD DVDD 48 2.2µF 2.2µF µCOM Over 10µF 24 Mute control 60kΩ 58 23 SPDET_L 22 SPDET_R 3rd order LPF 60 3rd order LPF 100kΩ 61 3rd order LPF 21 100kΩ 100kΩ 62 3rd order LPF 20 19 REF 63 10µF 2.2µF AMP1AG (+4 to +16dB/1dB) 18 4.7µF 2.2µF HPAG (+8 to +20dB/1dB) 64 10µF AMP2AG (+4 to +16dB/1dB) 4.7µF 17 100kΩ 13 14 15 16 2.2µF 12 10µF 11 10µF 10 REGAUD 9 2.2µF 8 2.2µF 7 2.2µF 6 2.2µF 5 100Ω 4 REGAUD 3 100Ω 2 2.2µF 1 2.2µF Speaker amplifier Speaker amplifier 59 REGAUD 2.2µF External audio power amplifier Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 46 - External audio power amplifier AMP3OUT CXA3785R Package Outline (Unit: mm) - 47 - Sony Corporation