PANASONIC AN30182A

AN30182A
600mA Synchronous DC-DC Step Down Regulator (2ch)
300mA LDO Regulator (6ch)
Multi Power Supply (High Efficiency Power LSI)
FEATURES
DESCRIPTION
z High-Speed Response DC-DC Step Down Regulator
Circuit that employs Hysteretic System
z DC-DC Step Down Regulator : 2-ch
Input voltage Range VBAT :2.5V to 5.5V
DVDD : 1.7V to 3.0V
Output voltage Range 0.8 V to 2.4 V
Up to 600 mA Output Current
AN30182A is a multi power supply LSI which has HighSpeed Response DC-DC Step Down Regulators (2-ch)
and LDO Regulators (6-ch).
By this DC-DC system, when load current charges
suddenly, it responds at high speed and minimizes the
changes of output voltage.
Since it is possible to use capacitors with small
capacitance and it is unnecessary to add external parts
for system phase compensation, this IC realizes
downsizing of set and reducing in the number of external
parts.
The output DC of each power supply is variable by I2C
control.
z LDO Regulator : 6-ch
Input voltage Range VBAT :2.5V to 5.5V
DVDD : 1.7V to 3.0V
Output voltage Range 1.0 V to 3.3 V
Up to 300 mA Output Current
z I2C control (2-slave address selectable)
z 25 pin Wafer Level Chip Size Package (WLCSP)
(Size : 2.15 mm × 2.15 mm, 0.4 mm Pitch)
APPLICATIONS
Mobile phone, Portable appliance, etc
SIMPLIFIED APPLICATION
EFFICIENCY CURVE
DDVBAT2 DDVBAT1
VB
0.1µF
VIN2
4.7µF
SDA
SCL
ASEL
1µF
4.7µF
4.7µF
LX1
FB1
DDGND1
LX2
FB2
DDGND2
1µH
VLDO4
DCDCOUT1
100
4.7µF
90
DCDCOUT2
1µH
4.7µF
VLDO1
1µF
AN30182A
VLDO5
VLDO2
1µF
1µF
AN30182A DCDC1 Efficiency
4.7µF
1µF
VLDO6
VLDO3
VREG REF RESET LDO1ON AGND
1µF
80
Efficiency [%]
DVDD
70
60
50
Vout=0.8V
40
30
Vout=1.2V
Vout=1.8V
20
Vout=2.4V
10
1µF
0
1µF
1
10
100
1000
Load Current [mA]
Notes) This application circuit is an example. The operation
of mass production set is not guaranteed. You should
perform enough evaluation and verification on the
design of mass production set. You are fully
responsible for the incorporation of the above
application circuit and information in the design of
your equipment.
Publication date: October 2012
Condition )
DDVBAT1 = DDVBAT2 = VB = VIN2 = 3.7V
Lo = 1.0 µH, Cout = 4.7 µF
Vout=0.8 , 1.2 , 1.8 , 2.4V
1
Ver. BEB
AN30182A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Notes
VB,VIN2,DDVBAT1,DDVBAT2
6.0
V
*1
DVDD
3.6
V
*1
Operating free-air temperature
Topr
– 30 to + 85
°C
*2
Operating junction temperature
Tj
– 30 to + 150
°C
*2
Tstg
– 55 to + 150
°C
*2
RESET,LDO1ON,FB1,FB2
– 0.3 to VVBAT + 0.3
V
*1
*3
SCL,SDA,ASEL
– 0.3 to VDVDD + 0.3
V
*1
*3
LX1,LX2,VREG,REF,LDO1,
LOD2,LDO3,LDO4,LDO5,LDO6
– 0.3 to VVBAT + 0.3
V
*1
*3
HBM (Human Body Model)
2
kV
—
Supply voltage
Storage temperature
Input Voltage Range
Output Voltage Range
ESD
Notes) Do not apply external currents and voltages to any pin not specifically mentioned.
This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating.
This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated
recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product
may be affected.
*1:The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2:Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25 °C.
*3:VVBAT is voltage for DDVBAT1, DDVBAT2. VB = VIN2, (VVBA + 0.3) V must not be exceeded 6 V.
VDVDD is voltage for DVDD, (VDVDD + 0.3) V must not be exceeded 3.6 V.
POWER DISSIPATION RATING
PACKAGE
25 pin Wafer level chip size Package
(WLCSP Type)
θJA
PD ( Ta = 25 °C)
PD ( Ta = 85 °C )
Notes
294.1 °C / W
0.425 W
0.221 W
*1
Note). For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply
voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not
exceed the allowable value.
*1:Glass Epoxy Substrate ( 4 Layers ) [ Glass-Epoxy: 50 X 50 X 0.8 t ( mm ) ]
Die Pad Exposed , Soldered.
CAUTION
Although this has limited built-in ESD protection circuit, but permanent damage may occur on it.
Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates
2
Ver. BEB
AN30182A
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage range
Input Voltage Range
Output Voltage Range
Pin Name
Min.
Typ.
Max.
Unit
Notes
VB
2.5
3.7
5.5
V
*1
VIN2
2.5
3.7
5.5
V
*1
DDVBAT1
2.5
3.7
5.5
V
*1
DDVBAT2
2.5
3.7
5.5
V
*1
DVDD
1.7
1.85
3.0
V
*1
RESET
– 0.3
—
VVBAT + 0.3
V
*2
LDO1ON
– 0.3
—
VVBAT + 0.3
V
*2
FB1
– 0.3
—
VVBAT + 0.3
V
*2
FB2
– 0.3
—
VVBAT + 0.3
V
*2
SCL
– 0.3
—
VDVDD + 0.3
V
*2
SDA
– 0.3
—
VDVDD + 0.3
V
*2
ASEL
– 0.3
—
VDVDD + 0.3
V
*2
LX1
– 0.3
—
VVBAT + 0.3
V
*2
LX2
– 0.3
—
VVBAT + 0.3
V
*2
VREG
– 0.3
—
VVBAT + 0.3
V
*2
REF
– 0.3
—
VVBAT + 0.3
V
*2
LDO1
– 0.3
—
VVBAT + 0.3
V
*2
LDO2
– 0.3
—
VVBAT + 0.3
V
*2
LDO3
– 0.3
—
VVBAT + 0.3
V
*2
LDO4
– 0.3
—
VVBAT + 0.3
V
*2
LDO5
– 0.3
—
VVBAT + 0.3
V
*2
LDO6
– 0.3
—
VVBAT + 0.3
V
*2
Note) Do not apply external currents and voltages to any pin not specifically mentioned.
Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, DDGND1 = DDGND2
VVBAT is voltage for DDVBAT1, DDVBAT2, VB = VIN2.VDVDD is voltage for DVDD.
*1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2 : (VVBAT + 0.3) V must not be exceeded 6 V. (VDVDD + 0.3) V must not be exceeded 3.6 V.
3
Ver. BEB
AN30182A
ELECRTRICAL CHARACTERISTICS
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.7V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Limits
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Notes
[ Consumption current ]
Consumption current 1 on active
IBAT_1 only LDO1 (PS mode) ON
—
10
20
μA
—
Consumption current 2 on active
IBAT_2 DCDC1-2, LDO1-6 = ON
—
360
600
μA
—
Static consumption current
IBAT_3 DCDC1-2, LDO1-6 = OFF
—
0.1
1.0
μA
—
4
Ver. BEB
AN30182A
ELECRTRICAL CHARACTERISTICS (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.7V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Limits
Parameter
Symbol
Conditions
Unit
Notes
1.897
V
—
Min
Typ
Max
1.803
1.850
[ LDO1 – 6 ( Normal Mode ) ] (LDO Regulator)
ILDO = – 150 mA
Vout = 1.85 V setting
Output voltage
VLDO
Output current
ILDO
—
300
—
—
mA
—
Load regulation
DVLDO
Δ ILDO = – 10 μA → – 150 mA
–5
20
50
mV
—
Line regulation
VLDOLR
VB = 3.1 V → 4.5 V
ILDO = – 150 mA
Vout = 1.85 V setting
– 10
0
10
mV
—
Short-circuit current
ISTLDO
VB = 3.7 V
VLDO = 0 V
35
100
255
mA
—
1.803
1.850
1.897
V
—
10
—
—
mA
—
–5
20
50
mV
—
– 25
0
25
mV
—
[ LDO1 – 6 ( Power Save Mode ) ] (LDO Regulator)
ILDO = – 5 mA
Vout = 1.85 V setting
Output voltage
VLDOPS
Output current
ILDOPS
Load regulation
DVLDOPS
Line regulation
VB = 3.1 V → 4.5 V
VLDOLRPS ILDO = – 5 mA
Vout = 1.85 V setting
—
Δ ILDO = – 10 μA → – 5 mA
5
Ver. BEB
AN30182A
ELECRTRICAL CHARACTERISTICS (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.7V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Limits
Parameter
Symbol
Conditions
Unit
Notes
1.230
V
—
Min
Typ
Max
1.170
1.200
[ DCDC1 ] (DC-DC Step Down Regulator)
IDCDC1 = – 300 mA
Vout = 1.2 V setting
Output voltage
VDCDC1
Output current
IDCDC1
—
600
—
—
mA
—
Load regulation
DVDCDC1
Δ IDCDC1 = – 10 μA → – 500 mA
Vout = 1.2 V setting
—
25
45
mV
—
Line regulation
DDVBAT1 = 3.1 V → 4.5 V
VDCDC1LR IDCDC1 = – 300 mA
Vout = 1.2 V setting
—
4
13
mV
—
Oscillation frequency
ISTDCDC1
2
3
4
MHz
—
1.803
1.850
1.897
V
—
IDCDC1 = – 300 mA (CCM)
[ DCDC2 ] (DC-DC Step Down Regulator)
IDCDC2 = – 300 mA
Vout = 1.85 V setting
Output voltage
VDCDC2
Output current
IDCDC2
—
600
—
—
mA
—
Load regulation
DVDCDC2
Δ IDCDC2 = – 10 μA → – 500 mA
Vout = 1.85 V setting
—
25
45
mV
—
Line regulation
DDVBAT2 = 3.1 V → 4.5 V
VDCDC2LR IDCDC2 = – 300 mA
Vout = 1.85 V setting
—
4
13
mV
—
Oscillation frequency
ISTDCDC2
2
3
4
MHz
—
IDCDC2 = – 300 mA (CCM)
[ I/O characteristics of control terminal (RESET, LDO1ON) ]
Low input voltage
VIL1
Voltage recognized as low level
—
—
0.45
V
—
High input voltage
VIH1
Voltage recognized as high level
1.2
—
—
V
—
Input pull-down resistance
PDR1
1
3
6
MΩ
—
—
[ I/O characteristics of control terminal (ASEL) ]
Low input voltage
VIL2
Voltage recognized as low level
—
—
VDVDD
× 0.3
V
—
High input voltage
VIH2
Voltage recognized as high level
VDVDD
× 0.7
—
—
V
—
6
Ver. BEB
AN30182A
APPLICATION INFORMATION
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.7V, VDVDD = 1.85V
Ta = 25 °C ± 2 °C unless otherwise noted.
Reference values
Parameter
Symbol
Conditions
Min
Typ
Max
0.3 ×
VDVDD
Unit
Notes
V
*1
*2
V
*1
*2
[I2C Bus (Internal I/O Stage Characteristics) ]
Low-level input voltage
VIL1
Voltage which recognized that
SDA and SCL are Low-level
– 0.5
—
High-level input voltage
VIH1
Voltage which recognized that
SDA and SCL are High-level
0.7 ×
VDVDD
—
VDVDD
max
+ 0.5
Low-level output voltage 1
VOL1
VDVDD > 2 V
SDA(sink current) = 3 mA
0
—
0.4
V
*2
Low-level output voltage 2
VOL2
VDVDD < 2 V
SDA(sink current) = 3 mA
0
—
0.2 ×
VDVDD
V
*2
Input current each I/O pin
IL
– 10
—
10
μA
*2
0
—
400
kHz
*2
SCL clock frequency
SCL, SDA =
0.1 × VDVDDmax to
0.9 × VDVDDmax
FOSC
—
Notes) *1 : The input threshold voltage of I2C bus (Vth) is linked to VDVDD.
In case the pull-up voltage is not VDVDD, the threshold voltage (Vth) is fixed to ((VDVDD / 2) ± (Schmitt width) / 2 ) and High-level,
Low-level of input voltage are not specified.
In this case, pay attention to Low-level (max.) value (VILmax).
It is recommended that the pull-up voltage of I2C bus is set to the I2C bus I/O stage supply voltage (VDVDD).
*2 :Checked by design, not production tested.
7
Ver. BEB
AN30182A
APPLICATION INFORMATION (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.1V to 4.5V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Reference values
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Notes
[ LDO1 – 6 ( Normal Mode ) ] (LDO Regulator)
VLDO
ILDO = – 150 mA
Vout = 1.85 V setting
1.803
1.850
1.897
V
*2
Consumption current on active
IREGLDO
Normal mode
VB > Vout + 0.1 V or
VIN2 > Vout + 0.1 V
25
50
75
μA
*2
I/O voltage difference
VSATLDO
ILDO = – 300 mA
0.3
—
—
V
*2
Ripple rejection
VLDORR
Δ VB = 3.7 V ± 0.15 V
ILDO = – 150 mA
fvin = 100 Hz to 10 kHz
—
– 60
– 40
dB
*2
Discharge resistance
RDISLDO
—
50
100
200
kΩ
*2
Load change characteristic
LTRLDO
ILDO = – 10 μA ↔ – 100 mA
—
30
150
mV
*2
1.803
1.850
1.897
V
*2
1
3
5
μA
*2
Output voltage
[ LDO1 – 6 ( Power Save Mode ) ] (LDO Regulator)
Output voltage
VLDOPS
ILDO = – 5 mA
Vout = 1.85 V setting
Consumption current on active
Power Save mode
IREGLDOPS VB > Vout + 0.1 V or
VIN2 > Vout + 0.1 V
Ripple rejection
VLDOPSRR
Δ VB = 3.7 V ± 0.15 V
ILDO = – 5 mA
fvin = 100 Hz to 10 kHz
—
– 10
–5
dB
*2
Short-circuit current
ISTLDOPS
VB = 3.7 V
VLDO = 0 V
5
20
40
mA
*2
Notes)
*2:Checked by design, not production tested.
8
Ver. BEB
AN30182A
APPLICATION INFORMATION (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.1V to 4.5V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Reference values
Parameter
Symbol
Conditions
Unit
Notes
1.23
V
*2
25
40
μA
*2
—
1.0
1.2
A
*2
Min
Typ
Max
1.17
1.200
10
[DCDC1 ] (DC-DC Step Down Regulator)
Output Voltage
VDCDC1
IDCDC1 = – 300 mA
Vout = 1.2 V setting
Consumption current on active IREGDCCD1 IDCDC1 = 0 mA
From FB1 × 100% to FB1 ×
70%
VB = 3.7 V
Output over current limit
ILIMDCDC1
Efficiency 1
DDVBAT1 = 3.4 V
EFFDCDC11 VDCDC1 = 2.4 V
IDCDC1 = – 150 mA
85
90
—
%
*2
Efficiency 2
DDVBAT1 = 3.7 V
EFFDCDC12 VDCDC1 = 1.2 V
IDCDC1 = – 150 mA
75
80
—
%
*2
DDVBAT1 = 5.5 V
DCDC1 = Disable
VLX1 = 0 V or 5.5 V
–1
0
1
μA
*2
0.5
1.0
2.0
kΩ
*2
1.803
1.850
1.897
V
*2
10
25
40
μA
*2
—
1.0
1.2
A
*2
LX leak current
Discharge resistance
ILXL1
RDISDCDC1
—
[DC-DC2 ] (DC-DC Step Down Regulator)
Output Voltage
VDCDC2
IDCDC2 = – 300 mA
Vout = 1.85 V setting
Consumption current on active IREGDCCD2 IDCDC2 = 0 mA
From FB2 × 100% to FB2 ×
70%
VB = 3.7 V
Output overcurrent limit
ILIMDCDC2
Efficiency 1
DDVBAT2 = 3.4 V
EFFDCDC21 VDCDC2 = 2.4 V
IDCDC2 = – 150 mA
85
90
—
%
*2
Efficiency 2
DDVBAT2 = 3.7 V
EFFDCDC22 VDCDC2 = 1.85 V
IDCDC2 = – 150 mA
80
85
—
%
*2
DDVBAT2 = 5.5 V
DCDC2 = Disable
VLX2 = 0 V or 5.5 V
–1
0
1
μA
*2
0.5
1.0
2.0
kΩ
*2
LX leak current
Discharge resistance
Notes)
ILXL2
RDISDCDC2
—
*2:Checked by design, not production tested.
9
Ver. BEB
AN30182A
APPLICATION INFORMATION (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.1V to 4.5V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Reference values
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Notes
[ I2C bus (Internal I/O stage characteristics) ]
Hysteresis of Schmitt trigger
input 1
Vhys1
VIO > 2 V,
Hysteresis 1 of SDA, SCL
0.05 ×
VDVDD
—
—
V
*2
Hysteresis of Schmitt trigger
input 2
Vhys2
VIO < 2 V,
Hysteresis 2 of SDA, SCL
0.1 ×
VDVDD
—
—
V
*2
Output fall time from VIHmin to VILmax
Tof
Bus capacitance : 10 pF to
400 pF
IP ≤ 6 mA (VOLmax = 0.6 V)
IP : Max. sink current
20 +
0.1 ×
Cb
—
250
ns
*2
Pulse width of spikes which must
be suppressed by the input filter
Tsp
—
0
—
50
ns
*2
Ci
—
—
—
10
pF
*2
0.6
—
—
μs
*2
Capacitance for each I/O pin
[
I2 C
bus (Bus line specifications) ]
The first clock pulse is
generated after tHD:STA.
Hold time
(repeated) START condition
tHD:STA
Low period of the SCL clock
tLOW
—
1.3
—
—
μs
*2
High period of the SCL clock
tHIGH
—
0.6
—
—
μs
*2
Set-up time for a repeat START
condition
tSU:STA
—
0.6
—
—
μs
*2
Data hold time
tHD:DAT
—
0
—
0.9
μs
*2
Data set-up time
tSU:DAT
—
100
—
—
ns
*2
Rise time of both SDA
and SCL signals
tr
—
20 +
0.1 ×
Cb
—
300
ns
*2
Fall time of both SDA
and SCL signals
tf
—
20 +
0.1 ×
Cb
—
300
ns
*2
Set-up time of STOP condition
tSU:STO
—
0.6
—
—
μs
*2
Bus free time between STOP
and START condition
tBUF
—
1.3
—
—
μs
*2
Notes)
*2 : Checked by design, not production tested.
10
Ver. BEB
AN30182A
APPLICATION INFORMATION (Continued)
VVBAT(DDVBAT1 = DDVBAT2 = VB = VIN2) = 3.1V to 4.5V, VDVDD = 1.85V
DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF
Ta = 25 °C ± 2 °C unless otherwise noted.
Reference values
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Notes
[ I2C bus (Bus line specifications) (continued) ]
Capacitive load for each bus line
Cb
—
—
—
400
pF
*2
*3
Noise margin at the Low-level for
each connected device
VnL
—
0.1 ×
VDVDD
—
—
V
*2
*3
Noise margin at the High-level for
each connected device
VnH
—
0.2 ×
VDVDD
—
—
V
*2
*3
*2 : Checked by design, not production tested.
*3 : Checked by design, not production tested.
The timing of Fast-mode devices in I2C-bus is specified as the following.
All values referred to VIHmin and VILmax level.
SDA
tf
tLOW
tSU;DAT
tr
tf
tHD;STA
tSP
tr
tBUF
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P
S
S : START condition
Sr : Repeat START condition
P : STOP condition
11
Ver. BEB
AN30182A
PIN CONFIGURATION
BOTTOM VIEW
E
LX2
DD
GND2
SDA
DD
GND1
LX1
D
DD
VBAT2
SCL
ASEL
DVDD
DD
VBAT1
C
VLDO6
FB2
AGND
VBAT2
FB1
VLDO1
B
VIN2
RESET
REF
VBON
LDO1
ON
VB
A
VLDO5
VLDO4
VREG
VBAT2
VLDO3
VLDO2
1
2
3
4
5
PIN FUNCTIONS
Pin No.
Pin name
Type
Description
A1
VLDO5
Output
LDO5 output
A2
VLDO4
Output
LDO4 output
A3
VREG
Output
Reference output
A4
VLDO3
Output
LDO3 output
A5
VLDO2
Output
LDO2 output
B1
VIN2
B2
RESET
Input
B3
REF
Output
B4
LDO1ON
Input
B5
VB
C1
VLDO6
Output
C2
FB2
Input
C3
AGND
Ground
C4
FB1
Input
C5
VLDO1
Output
D1
DDVBAT2
D2
SCL
Input
I2C clock input
D3
ASEL
Input
I2C slave address select
D4
DVDD
D5
DDVBAT1
E1
LX2
Output
DCDC2 switching
E2
DDGND2
Ground
GND
E3
SDA
Input/Output
E4
DDGND1
Ground
GND
E5
LX1
Output
DCDC1 switching
Power Supply Input for LDO4, LDO5, and LDO6
Reset input for Logic
Reference output
LDO1 ON/OFF control
Power Supply Input for LDO1, LDO2, LDO3, and other VB
LDO6 output
DCDC2 voltage feedback
GND
DCDC1 voltage feedback
LDO1 output
Power Supply DCDC2 input
Power Supply Power supply for Logic
Power Supply DCDC1 input
I2C data input/output
Notes) Concerning detail about pin description, please refer to OPERATION and APPLICATION INFORMATION section.
12
Ver. BEB
AN30182A
FUNCTIONAL BLOCK DIAGRAM
D5
DVDD
D4
E5
DCDC1
0.8 V - 2.4 V / 600 mA(min)
SDA
SCL
ASEL
E3
I2C
I/F
D2
E4
C4
DVDD
→VB
D3
D1
E1
DCDC2
RESET
B2
VB→DVDD
0.8 V - 2.4 V / 600 mA(min)
DVDD
E2
C2
3 MΩ
VB
DVDD
DET
B5
LDO1
1.0 - 3.3 V / 300 mA(min)
LDO2
1.0 - 3.3 V / 300 mA(min)
VB
LDO3
TSD
1.0 - 3.3 V / 300 mA(min)
C5
A5
A4
DDVBAT1
LX1
DDGND1
FB1
DDVBAT2
LX2
DDGND2
FB2
VB
VLDO1
VLDO2
VLDO3
VB
LDO1ON
B4
3 MΩ
REF
B3
B1
LDO4
REF
1.0 - 3.3 V / 300 mA (min)
LDO5
VREG
A3
1.0 -3.3 V / 300 mA (min)
A1
VIN2
VLDO4
VLDO5
VREG
LDO6
1.0 - 3.3 V / 300 mA (min)
AGND
A2
C1 VLDO6
C3
Notes) This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified.
13
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES
(1) Output Ripple Voltage of DC-DC1 and DC-DC2
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH , CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
DC-DC2 , Iout = 0mA
DC-DC1 , Iout = 0mA
Vout
Vout
LX1
LX1
DC-DC2 , Iout = 100mA
DC-DC1 , Iout = 100mA
Vout
Vout
LX1
LX1
DC-DC2 , Iout = 600mA
DC-DC1 , Iout = 600mA
Vout
Vout
LX1
LX1
14
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(2) Load Transient of DC-DC1 and DC-DC2
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH , CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
DC-DC2 , Iout = 10μA to 500mA
(ΔT=500mA/usec)
DC-DC1 , Iout = 10μA to 500mA
(ΔT=500mA/usec)
Vout
Vout
Iout
Iout
DC-DC2 , Iout = 500mA to 10μA
(ΔT=500mA/usec)
DC-DC1 , Iout = 500mA to 10μA
(ΔT=500mA/usec)
Vout
Vout
Iout
Iout
15
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(3) Efficiency of DC-DC1 and DC-DC2
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH , CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
AN30182A DC-DC1 Efficiency
100
90
Efficiency [%]
80
70
60
50
Vout=0.8V
40
30
Vout=1.2V
Vout=1.8V
20
Vout=2.4V
10
0
1
10
100
1000
Load Current [mA]
AN30182A DC-DC2 Efficiency
100
90
Efficiency [%]
80
70
60
50
Vout=0.8V
40
Vout=1.2V
30
Vout=1.8V
20
Vout=2.4V
10
0
1
10
100
1000
Load Current [mA]
16
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(4) Load Regulation of DC-DC1 and DC-DC2
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH , CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
Load Regulation of DC-DC1
1.4
VDCDCOUT1 [V]
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
0
100
200
300
400
500
600
Load Current [mA]
Load Regulation of DC-DC2
2.05
VDCDCOUT2 [V]
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
0
100
200
300
400
500
600
Load Current [mA]
17
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(5) Line Regulation of DC-DC1 and DC-DC2
Iout = 300mA, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH
CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
VIN = 2.4V to 5.5V
Line Regulation of DC-DC1
1.4
DCDCOUT1 [V]
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
2
2.5
3
3.5
4
4.5
5
5.5
6
5
5.5
6
VIN [V]
Line Regulation of DC-DC2
2.05
DCDCOUT2 [V]
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
2
2.5
3
3.5
4
4.5
VIN [V]
18
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(6) Start Up & Shut Down of DC-DC1 and DC-DC2
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH , CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
DC-DC2 , RDCDCOUT2 = No Load
Start Up
DC-DC1 , RDCDCOUT1 = No Load
Start Up
VDCDCOUT1
VDCDCOUT2
I2C Signal
I2C Signal
DC-DC2 , RDCDCOUT2 = No Load
Shut Down
DC-DC1 , RDCDCOUT1 = No Load
Shut Down
VDCDCOUT1
VDCDCOUT2
I2C Signal
I2C Signal
19
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(7) Start Up & Shut Down of DC-DC1 and DC-DC2
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH , CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
DC-DC2 , RDCDCOUT2 = 6Ω
Start Up
DC-DC1 , RDCDCOUT1 = 4Ω
Start Up
VDCDCOUT1
VDCDCOUT2
I2C Signal
I2C Signal
DC-DC2 , RDCDCOUT2 = 6Ω
Shut Down
DC-DC1 , RDCDCOUT1 = 4Ω
Shut Down
VDCDCOUT1
VDCDCOUT2
I2C Signal
I2C Signal
20
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(8) Short Protection of DC-DC1
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, L1 = 1 µH , CDCDCOUT1 = 4.7 µF
IOUT
VOUT
LX
21
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(9) Thermal Performance of DC-DC1
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, ILoad = 600mA , L1 = 1 µH , CDCDCOUT1 = 4.7 µF
(10) Thermal Performance of DC-DC2
VIN = 3.7 V, DC-DC2_Vout = 1.85 V, ILoad = 600mA , L2 = 1 µH , CDCDCOUT2 = 4.7 µF
22
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(11) Frequency of DC-DC1 and DC-DC2
VIN = 3.7 V, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH , CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
DC-DC2 , Iout = 0mA
DC-DC1 , Iout = 0mA
Vout
Vout
LX1
LX1
DC-DC2 , Iout = 300mA
DC-DC1 , Iout = 300mA
Vout
Vout
LX1
LX1
DC-DC2 , Iout = 600mA
DC-DC1 , Iout = 600mA
Vout
Vout
LX1
LX1
23
Ver. BEB
AN30182A
TYPICAL CHARACTERISTICS CURVES (Continued)
(12) Frequency of DC-DC1 and DC-DC2
IOUT = 300mA, DC-DC1_Vout = 1.2 V, DC-DC2_Vout=1.85V , L1 = L2 = 1 µH
CDCDCOUT1 = CDCDCOUT2 = 4.7 µF
DC-DC2 , VIN = 2.5V
DC-DC1 , VIN = 2.5V
Vout
Vout
LX1
LX1
DC-DC2 , VIN = 3.7V
DC-DC1 , VIN = 3.7V
Vout
Vout
LX1
LX1
DC-DC2 , VIN = 5.5V
DC-DC1 , VIN = 5.5V
Vout
Vout
LX1
LX1
24
Ver. BEB
AN30182A
OPERATION
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
1. I2C-bus Interface
a.) Basic Rules
d.) Data format
Slave Address
This IC, I2C-bus, is designed to correspond to the
Standard-mode (100 kbps) and Fast-mode(400 kbps)
Pin ASEL A6 A5 A4 A3 A2 A1 A0 R/W
Hex
devices in the version 2.1 of NXP's specification.
Low
1
1
1
0
0
1
0
x
72h
However, it does not correspond to the HS-mode (to 3.4
High
1
1
1
0
0
1
1
x
73h
2
Mbps). This IC will operate as a slave device in the I Cbus system. This IC will not operate as a master device.
Write mode
The program operation check of this IC has not been
conducted on the multi-master bus system and the mixS Slave Address W A Sub Address A Data Byte A P
speed bus system, yet. The connected confirmation of
this IC to the CBUS receiver also has not been checked.
Stop
Start
Ack
Please confirm with our company if the IC will be used in
Write mode : 0
Condition
Condition
these mode systems. The I2C is the brand of NXP.
b.) START and STOP conditions
Read mode
A High to Low transition on the SDA line while SCL is
High is one such unique case. This situation indicates
START condition. A Low to High transition on the SDA
line while SCL is High defines STOP condition.
START and STOP conditions are always generated by
the master. After START condition occur, the bus will be
busy. The bus is considered to be free again a certain
time after the STOP condition.
d1.) When Sub address is not specified
When data is read without assigning sub-address, it is
possible to read the value of sub-address specified in
Write mode immediately before.
S
Slave Address
Start
STOP condition Condition
START condition
R A
Data byte
Ack
Read mode : 1
A P
Stop
condition
Ex) When writing data into address and reading data
from "01 h".
SDA
Write
S
Slave
Address
0 A
Read
S
Slave
Address
1 A
Sub Address
A
01h
Data Byte
A P
SCL
Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most
significant bit (MSB) first.
MSB
S
SCL or
Sr
1
acknowledgement
signal from slave
2
START or
repeated START
condition
7
8
9
ACK
acknowledgement
signal from receiver
1
2 3–8 9
A P
d2.) When Sub address is specified
S
P
SDA
Data Byte
Slave
Sub
Slave
0A
AS
1 A Data Byte A P
Address
Address
Address
Stop
Ack
Ack
Condition
Repeated
Start
Read Mode : 1
Condition
Acknowledge Bit
Write Mode : 0
Start
Condition
Sr
Sr
or
P
ACK
STOP or
repeated START
condition
25
Sub-address should be assigned first.
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
2. Register map
Sub
Register
R/W
Address
Name
00h
R/W
Data
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
LD6ON
LD5ON
LD4ON
LD3ON
LD2ON
LD1ON
DD2ON
DD1ON
Default
0
0
0
0
0
0
0
0
CNT
Name
01h
VDC2[3:0]
Default
1
1
1
Name
02h
0
0
0
0
0
1
1
0
VL1[3:0]
0
0
1
0
VL4[3:0]
1
1
VL3[3:0]
0
Name
06h
0
R/W DAC3
Default
05h
1
VL2[3:0]
Name
04h
0
R/W DAC2
Default
03h
VDC1[3:0]
R/W DAC1
0
1
0
VL6[3:0]
VL5[3:0]
R/W DAC4
Default
1
1
1
1
1
0
0
0
Name
—
—
LD6PS
LD5PS
LD4PS
LD3PS
LD2PS
LD1PS
Default
—
—
0
0
0
0
0
0
Name
—
—
—
—
—
—
—
LDO1EN
SEL
Default
—
—
—
—
—
—
—
1
R/W PSCNT
R/W ENSEL
LDO6
LDO5
LDO4
LDO3
LDO2
LDO1
DCDC2
DCDC1
3.3 V
1.8 V
2.8 V
2.6 V
1.0 V
1.85 V
1.85 V
1.2 V
Initial voltage
26
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3. Register map details
Sub
Register
R/W
Address
Name
00h
R/W
Data
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
LD6ON
LD5ON
LD4ON
LD3ON
LD2ON
LD1ON
DD2ON
DD1ON
Default
0
0
0
0
0
0
0
0
CNT
D7 : LDO6 ON/OFF select register
[0] : OFF (default)
[1] : ON
D6 : LDO5 ON/OFF select register
[0] : OFF (default)
[1] : ON
D5 : LDO4 ON/OFF select register
[0] : OFF (default)
[1] : ON
D4 : LDO3 ON/OFF select register
[0] : OFF (default)
[1] : ON
D3 : LDO2 ON/OFF select register
[0] : OFF (default)
[1] : ON
D2 : LDO1 ON/OFF select register
[0] : OFF (default)
[1] : ON
D1 : DCDC2 ON/OFF select register
[0] : OFF (default)
[1] : ON
D0 : DCDC1 ON/OFF select register
[0] : OFF (default)
[1] : ON
27
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3. Register map details
Data
Sub
Register
R/W
Address
Name
Bit
D7
D6
Name
01h
D5
D4
D3
D2
VDC2[3:0]
D1
D0
VDC1[3:0]
R/W DAC1
Default
1
1
1
D7-4 : DCDC2 Register for output voltage setup
VDC2[3:0]
0
1
0
0
0
D3-0 : DCDC1 Register for output voltage setup
VDC1[3:0]
D7
D6
D5
D4
Output voltage
[V]
0
0
0
0
0.80
0
0
0
0
0.80
0
0
0
1
0.85
0
0
0
1
0.85
0
0
1
0
0.90
0
0
1
0
0.90
0
0
1
1
0.95
0
0
1
1
0.95
0
1
0
0
1.00
0
1
0
0
1.00
0
1
0
1
1.05
0
1
0
1
1.05
0
1
1
0
1.10
0
1
1
0
1.10
0
1
1
1
1.15
0
1
1
1
1.15
1
0
0
0
1.20
1
0
0
0
1.20 (Default)
1
0
0
1
1.30
1
0
0
1
1.30
1
0
1
0
1.40
1
0
1
0
1.40
1
0
1
1
1.50
1
0
1
1
1.50
1
1
0
0
1.65
1
1
0
0
1.65
1
1
0
1
1.80
1
1
0
1
1.80
1
1
1
0
1.85 (Default)
1
1
1
0
1.85
1
1
1
1
2.40
1
1
1
1
2.40
28
D3
D2
D1
D0
Output voltage
[V]
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3. Register map details
Data
Sub
Register
R/W
Address
Name
Bit
D7
D6
Name
02h
D5
D4
D3
D2
VL2[3:0]
D1
D0
VL1[3:0]
R/W DAC2
Default
0
0
0
D7-4 : LDO2 Register for output voltage setup
VL2[3:0]
0
0
1
0
1
D3-0 : LDO1 Register for output voltage setup
VL1[3:0]
D3
D2
D1
D0
Output voltage
[V]
D7
D6
D5
D4
Output voltage
[V]
0
0
0
0
1.00 (Default)
0
0
0
0
1.00
0
0
0
1
1.10
0
0
0
1
1.10
0
0
1
0
1.20
0
0
1
0
1.20
0
0
1
1
1.30
0
0
1
1
1.30
0
1
0
0
1.40
0
1
0
0
1.40
0
1
0
1
1.50
0
1
0
1
1.50
0
1
1
0
1.60
0
1
1
0
1.60
0
1
1
1
1.70
0
1
1
1
1.70
1
0
0
0
1.80
1
0
0
0
1.80
1
0
0
1
1.85
1
0
0
1
1.85 (Default)
1
0
1
0
2.60
1
0
1
0
1.90
1
0
1
1
2.70
1
0
1
1
2.70
1
1
0
0
2.80
1
1
0
0
2.80
1
1
0
1
2.85
1
1
0
1
2.85
1
1
1
0
3.00
1
1
1
0
3.00
1
1
1
1
3.30
1
1
1
1
3.30
29
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3. Register map details
Sub
Register
R/W
Address
Name
Data
Bit
D7
D6
Name
03h
R/W
D5
D4
D3
D2
VL4[3:0]
D1
D0
VL3[3:0]
DAC3
Default
1
1
0
D7-4 : LDO4 Register for output voltage setup
VL4[3:0]
0
0
1
1
0
D3-0 : LDO3 Register for output voltage setup
VL3[3:0]
D7
D6
D5
D4
Output voltage
[V]
0
0
0
0
1.00
0
0
0
0
1.00
0
0
0
1
1.10
0
0
0
1
1.10
0
0
1
0
1.20
0
0
1
0
1.20
0
0
1
1
1.30
0
0
1
1
1.30
0
1
0
0
1.40
0
1
0
0
1.40
0
1
0
1
1.50
0
1
0
1
1.50
0
1
1
0
1.60
0
1
1
0
1.60
0
1
1
1
1.70
0
1
1
1
1.70
1
0
0
0
1.80
1
0
0
0
1.80
1
0
0
1
1.85
1
0
0
1
1.85
1
0
1
0
2.60
1
0
1
0
2.60 (Default)
1
0
1
1
2.70
1
0
1
1
2.70
1
1
0
0
2.80 (Default)
1
1
0
0
2.80
1
1
0
1
2.85
1
1
0
1
2.85
1
1
1
0
3.00
1
1
1
0
3.00
1
1
1
1
3.30
1
1
1
1
3.30
30
D3
D2
D1
D0
Output voltage
[V]
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3. Register map details
Data
Sub
Register
R/W
Address
Name
Bit
D7
D6
Name
04h
D5
D4
D3
D2
VL6[3:0]
D1
D0
VL5[3:0]
R/W DAC4
Default
1
1
1
D7-4 : LDO6 Register for output voltage setup
VL6[3:0]
1
0
1
0
0
D3-0 : LDO5 Register for output voltage setup
VL5[3:0]
D7
D6
D5
D4
Output voltage
[V]
0
0
0
0
1.00
0
0
0
0
1.00
0
0
0
1
1.10
0
0
0
1
1.10
0
0
1
0
1.20
0
0
1
0
1.20
0
0
1
1
1.30
0
0
1
1
1.30
0
1
0
0
1.40
0
1
0
0
1.40
0
1
0
1
1.50
0
1
0
1
1.50
0
1
1
0
1.60
0
1
1
0
1.60
0
1
1
1
1.70
0
1
1
1
1.70
1
0
0
0
1.80
1
0
0
0
1.80 (Default)
1
0
0
1
1.85
1
0
0
1
1.85
1
0
1
0
2.60
1
0
1
0
2.60
1
0
1
1
2.70
1
0
1
1
2.70
1
1
0
0
2.80
1
1
0
0
2.80
1
1
0
1
2.85
1
1
0
1
2.85
1
1
1
0
3.00
1
1
1
0
3.00
1
1
1
1
3.30 (Default)
1
1
1
1
3.30
31
D3
D2
D1
D0
Output voltage
[V]
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3. Register map details
Sub
Register
R/W
Address
Name
05h
Data
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
—
—
LD6PS
LD5PS
LD4PS
LD3PS
LD2PS
LD1PS
Default
—
—
0
0
0
0
0
0
R/W PSCNT
* Please set it to normal mode when LDO starts.
D5 : LDO6 Power save mode select register
[0] : Normal mode (default)
[1] : Power save mode
D4 : LDO5 Power save mode select register
[0] : Normal mode (default)
[1] : Power save mode
D3 : LDO4 Power save mode select register
[0] : Normal mode (default)
[1] : Power save mode
D2 : LDO3 Power save mode select register
[0] : Normal mode (default)
[1] : Power save mode
D1 : LDO2 Power save mode select register
[0] : Normal mode (default)
[1] : Power save mode
D0 : LDO1 Power save mode select register
[0] : Normal mode (default)
[1] : Power save mode
32
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3. Register map details
Sub
Register
R/W
Address
Name
06h
Data
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
—
—
—
—
—
—
—
LDO1EN
SEL
Default
—
—
—
—
—
—
—
1
R/W ENSEL
D0 : LDO1ENSEL
[0] : LDO1ON control invalid
[1] : LDO1ON control valid (default)
33
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
4. Timing Chart (Sequence – 1 (DVDD input externally))
VBAT
(External input signal)
REF
(IC output signal)
1.24 V
2.4 V
VREG
(IC output signal)
2.2 V
2.1 V
REGW
(IC inner signal)
DVDD
(External input signal)
1.5 V
1.4 V
DVDD
DET
(IC inner signal)
I2C acceptance starts
RESET
(External input signal)
I2C acceptance stops
DVDD_DET:High and RESET:High
= I2C acceptance ON
DVDD_DET:Low and RESET:Low
= I2C acceptance OFF
All registers are initialized
(LDO and DCDC are turned off)
LDO1ON
(External input signal)
at DCDC-start
OSC
(IC inner signal)
VLDO1
(IC output signal)
at LDO-start
PS⇔NM
Pin LDO1 stops
LDO1 starts in NM mode
PS⇔NM
I2C starts
I2C stops
Pin LDO1 starts
NM
VLDO
2/3/4/5/6
(IC output signal)
PS
NM
NM
I2C starts
I2C input
I2C input
NM
DCDC1
DCDC2
(IC output signal)
I2C starts
34
@ 150 μs
PS
PS
NM
LDO* stop is possible
even in PS mode
I2C stops
NM
I2C stops
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
4. Timing Chart (Sequence – 2 (LDO1ON = fixed VBAT))
VBAT
(External input signal)
1.2 V
0.45 V
REF
(IC output signal)
1.24 V
VREG
(IC output signal)
2.4 V
2.2 V
2.1 V
REGW
(IC inner signal)
DVDD
(External input signal)
1.4 V
1.5 V
DVDD
DET
(IC inner signal)
I2C acceptance starts
RESET
(External input signal)
I2C acceptance stops
DVDD_DET:High and RESET:High
= I2C acceptance ON
LDO1ON
(External input signal)
1.2 V
0.45 V
OSC
(IC inner signal)
VLDO1
(IC output signal)
at DCDC-start
LDO1 starts in NM mode
at LDO-start
I2C stops
Pin LDO1 stops
I2C starts
Pin LDO1 starts
NM
NM
VLDO
2/3/4/5/6
(IC output signal)
I2C starts
I2C stops
NM
DCDC1
DCDC2
(IC output signal)
I2C starts
@ 150 μs
I2C stops
35
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
4. Timing Chart (Sequence – 3 (VLDO1 = connected DVDD))
VBAT
(External input signal)
REF
(IC output signal)
1.24 V
VREG
(IC output signal)
2.4 V
2.2 V
2.1 V
REGW
(IC inner signal)
DVDD:VLDO1
(External input signal)
1.5 V
1.4 V
DVDD
DET
(IC inner signal)
I2C acceptance starts
RESET
(External input signal)
I2C acceptance stops
DVDD_DET:High and RESET:High
= I2C acceptance ON
DVDD_DET:Low and RESET:Low
= I2C acceptance OFF
LDO1ON
(External input signal)
OSC
(IC inner signal)
VLDO1
(IC output signal)
at LDO-start
at DCDC-start
VLDO1 is connected directly with DVDD
Pin LDO1 starts
Pin LDO1 stops
1.4 V
1.5 V
VLDO
2/3/4/5/6
(IC output signal)
DCDC1
DCDC2
(IC output signal)
I2C starts
I2C stops
I2C starts @ 150 μs
36
I2C stops
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Overcurrent protection (about 1 A)
Ground short protection
hysteresis
< Operation explanation >
(1) The Overcurrent protection operates
at about 1 A (Typ).
(2) The Ground protection sequence is implemented
when the output voltage decreases to about 70%
of the set voltage.
(3) The Ground short protection operates intermittently.
(2 ms : ON, 16 ms : OFF)
Output voltage [V]
5. DC-DC Protection Operation
Ground short protection
about 70% of Vout
Intermittent operation area
Pendency characteristic
Output current [A]
about 150 mA
Operation explanation chart
6. DAC Voltage Accuracy
DCDC1 (VBAT = 3.7 V , Iout = 300 mA)
VDC1[3:0]
DCDC2 (VBAT = 3.7 V , Iout = 300 mA)
Output voltage Accuracy
[V]
[%]
VDC2[3:0]
D3
D2
D1
D0
Output voltage Accuracy
[V]
[%]
D3
D2
D1
D0
0
0
0
0
0.80
±5.0
0
0
0
0
0.80
±8.5
0
0
0
1
0.85
±5.0
0
0
0
1
0.85
±6.5
0
0
1
0
0.90
±4.5
0
0
1
0
0.90
±6.5
0
0
1
1
0.95
±4.0
0
0
1
1
0.95
±6.0
0
1
0
0
1.00
±4.0
0
1
0
0
1.00
±6.0
0
1
0
1
1.05
±4.0
0
1
0
1
1.05
±6.0
0
1
1
0
1.10
±3.5
0
1
1
0
1.10
±5.5
0
1
1
1
1.15
±3.5
0
1
1
1
1.15
±5.5
1
0
0
0
1.20 (Default)
±2.5
1
0
0
0
1.20
±3.0
1
0
0
1
1.30
±3.0
1
0
0
1
1.30
±3.0
1
0
1
0
1.40
±3.0
1
0
1
0
1.40
±4.0
1
0
1
1
1.50
±3.0
1
0
1
1
1.50
±3.0
1
1
0
0
1.65
±3.0
1
1
0
0
1.65
±3.0
1
1
0
1
1.80
±3.0
1
1
0
1
1.80
±4.0
1
1
1
0
1.85
±3.0
1
1
1
0
1.85 (Default)
±2.5
1
1
1
1
2.40
±3.0
1
1
1
1
2.40
±3.0
37
Ver. BEB
AN30182A
OPERATION ( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
6. DAC Voltage Accuracy (continued)
LDO VBAT = 3.7 V (Normal-mode : Iout = 150 mA, PS-mode : Iout = 5 mA)
Accuracy [%]
VL1[3:0]
D3
D2
D1
D0
Output voltage
[V]
Normal-mode
PS-mode
LDO1
LDO2 to 6
LDO1
LDO2 to 6
0
0
0
0
1.00
±5.0
±5.0
±5.0
±5.0
0
0
0
1
1.10
±4.5
±4.5
±4.5
±4.5
0
0
1
0
1.20
±4.0
±4.0
±4.0
±4.0
0
0
1
1
1.30
±4.0
±4.0
±4.0
±4.0
0
1
0
0
1.40
±3.0
±3.0
±3.0
±3.0
0
1
0
1
1.50
±3.0
±3.0
±3.0
±3.0
0
1
1
0
1.60
±3.0
±3.0
±3.0
±3.0
0
1
1
1
1.70
±3.0
±3.0
±3.0
±3.0
1
0
0
0
1.80
±3.0
±3.0
±3.0
±3.0
1
0
0
1
1.85
±2.5
±2.5
±2.5
±2.5
1.90
1
0
±2.5
—
0
±2.5
—
1
2.60
—
±3.0
—
±3.0
1
0
1
1
2.70
±3.0
±3.0
±3.0
±3.0
1
1
0
0
2.80
±3.0
±3.0
±3.0
±3.0
1
1
0
1
2.85
±3.0
±3.0
±3.0
±3.0
1
1
1
0
3.00
±3.0
±3.0
±3.0
±3.0
1
1
1
1
3.30
±3.0
±3.0
±3.0
±3.0
38
Ver. BEB
AN30182A
APPLICATION INFORMATION
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
1.Application Circuit and Evaluation Board
VIN2 DDVBAT2 DDVBAT1
VB
DVDD
CV1
CD1
CV2
C2
C1
L1
SDA
DCDCOUT1
LX1
FB1
DCDCGND1
SCL
ASEL
CDCDCOUT1
DCDCOUT2
LX2
FB2
DCDCGND2
LDO4
COUT4
AN30182A
LDO5
L2
CDCDCOUT1
LDO1
COUT1
LDO2
COUT2
COUT5
LDO6
LDO3
COUT6
COUT3
VREG
REF
RESET LDO1ON AGND
CVREG
CREF
Figure : Application Circuit
Figure : Top Layer with silk screen
( Top View ) with Evaluation Board
Figure : Bottom Layer with silk screen
( Bottom View ) with Evaluation Board
Notes) This application circuit and layout is an example. The operation of mass production set is not guaranteed. You should perform
enough evaluation and verification on the design of mass production set. You are fully responsible for the incorporation of the
above application circuit and information in the design of your equipment.
39
Ver. BEB
AN30182A
APPLICATION INFORMATION( Continued )
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
2.RECOMMENDED COMPONENT
Reference Designator
QTY
Value
Manufacturer
Part Number
C1
1
4.7µF
Murata
GRM21BB31C475KA87
C2
1
4.7µF
Murata
GRM21BB31C475KA87
CV1
1
4.7µF
Murata
GRM21BB31C475KA87
VC2
1
4.7µF
Murata
GRM21BB31C475KA87
CD1
1
0.1µF
Murata
GRM188B11C104KA01
L1
1
1.0 µH
FDK
MIPSZ2012D1R0
CDCDCOUT1
1
4.7µF
Murata
GRM21BB31A475KA74
L2
1
1.0 µH
FDK
MIPSZ2012D1R0
CDCDCOUT2
1
4.7µF
Murata
GRM21BB31A475KA74
COUT1
1
1.0µF
Murata
GRM185B31A105KE35
COUT2
1
1.0µF
Murata
GRM185B31A105KE35
COUT3
1
1.0µF
Murata
GRM185B31A105KE35
COUT4
1
1.0µF
Murata
GRM185B31A105KE35
COUT5
1
1.0µF
Murata
GRM185B31A105KE35
COUT6
1
1.0µF
Murata
GRM185B31A105KE35
CVREG
1
1.0µF
Murata
GRM185B31A105KE35
CREF
1
1.0µF
Murata
GRM185B31A105KE35
Figure : Recommended Component
40
Ver. BEB
AN30182A
PACKAGE INFORMATION ( Reference Data )
Outline Drawing
Package Code : XBGA025-W-2222AEL
Unit:mm
Body Materia l : Br/Sb Free Epoxy resin
Reroute Material : Cu
Bump
41
: SnAgCu
Ver. BEB
AN30182A
IMPORTANT NOTICE
1.The products and product specifications described in this book are subject to change without notice for
modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore,
ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your
requirements.
2.When using the LSI for new models, verify the safety including the long-term reliability for each product.
3.When the application system is designed by using this LSI, be sure to confirm notes in this book.
Be sure to read the notes to descriptions and the usage notes in the book.
4.The technical information described in this book is intended only to show the main characteristics and application
circuit examples of the products. No license is granted in and to any intellectual property right or other right owned
by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to
the infringement upon any such right owned by any other company which may arise as a result of the use of
technical information de-scribed in this book.
5.This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of
our company.
6.This LSI is intended to be used for general electronic equipment.
Consult our sales staff in advance for information on the following applications: Special applications in which
exceptional quality and reliability are required, or if the failure or malfunction of this LSI may directly jeopardize
life or harm the human body.
Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automobile, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in
connection with your using the LSI described in this book for any special application, unless our company agrees
to your using the LSI in this book for any special application.
7.This LSI is neither designed nor intended for use in automotive applications or environments unless the specific
product is designated by our company as compliant with the ISO/TS 16949 requirements.
Our company shall not be held responsible for any damage incurred by you or any third party as a result of or in
connection with your using the LSI in automotive application, unless our company agrees to your using the LSI in
this book for such application.
8.If any of the products or technical information described in this book is to be exported or provided to non-residents,
the laws and regulations of the exporting country, especially, those with regard to security export control, must be
observed.
9. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of
controlled substances, including without limitation, the EU RoHS Directive.
Our company shall not be held responsible for any damage incurred as a result of your using the LSI not
complying with the applicable laws and regulations.
42
Ver. BEB
AN30182A
USAGE NOTES
1. When designing your equipment, comply with the range of absolute maximum rating and the guaranteed
operating conditions (operating power supply voltage and operating environment etc.). Especially, please be
careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off
and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of
break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as
redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical
injury, fire, social damages, for example, by using the products.
2. Comply with the instructions for use in order to prevent breakdown and characteristics change due to external
factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's
process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf
life and the elapsed time since first opening the packages.
3. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board),
it might smoke or ignite.
4. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit
between pins. In addition, refer to the Pin Description for the pin configuration.
5. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to
problems such as a solder-bridge between the pins of the semiconductor device. Also, perform a full technical
verification on the assembly quality, because the same damage possibly can happen due to conductive
substances, such as solder ball, that adhere to the LSI during transportation.
6. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs
such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin
short (load short) .
And, safety measures such as an installation of fuses are recommended because the extent of the abovementioned damage and smoke emission will depend on the current capability of the power supply.
7. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit
should not work during normal operation.
Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is
momentarily exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground
fault), the LSI might be damaged before the thermal protection circuit could operate.
8. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not
applied to the pins because the device might be damaged, which could happen due to negative voltage or
excessive voltage generated during the ON and OFF timing when the inductive load of a motor coil or actuator
coils of optical pick-up is being driven.
9. The product which has specified ASO (Area of Safe Operation) should be operated in ASO
10. Verify the risks which might be caused by the malfunctions of external components.
11. Connect the metallic plates on the back side of the LSI with their respective potentials (AGND, PVIN, LX). The
thermal resistance and the electrical characteristics are guaranteed only when the metallic plates are connected
with their respective potentials.
43
Ver. BEB
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for general applications (such as office equipment, communications
equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book.
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment,
life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of
the products may directly jeopardize life or harm the human body.
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with
your using the products described in this book for any special application, unless our company agrees to your using the products in
this book for any special application.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
20100202