INTEGRATED CIRCUITS DATA SHEET TDA1388T Bitstream continuous calibration filter-DAC for CD-ROM audio applications Objective specification File under Integrated Circuits, IC01 1995 Dec 08 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio TDA1388T FEATURES Multiple format input interface • I2S-bus and LSB-justified input format compatible • 1fs input format data rate. Extensive channel manipulation features • Separate soft mute on left and right channel • Channel interchange function (left to right and right to left) GENERAL DESCRIPTION • Monaural function (left to right or right to left) The TDA1388T CMOS digital-to-analog bitstream convertor incorporates an up-sampling digital filter and noise shaper, unique signal processing features and integrated line and headphone drivers. The digital processing features are of high sound quality due to the wide dynamic range of the bitstream conversion technique. • True mono function (left plus right)/2. Digital sound processing • Separate digital volume control for left and right channels • Digital tone control, bass boost and treble The TDA1388T supports the I2S-bus data input mode with word lengths of up to 20 bits and the LSB justified serial data input format with word lengths of 16, 18 and 20 bits. Two cascaded half-band filters and a sample-and-hold function increase the oversampling rate from 1fs to 64fs. A 2nd-order noise shaper converts this oversampled data to a bitstream for the 5-bit continuous calibration digital-to-analog convertors (DACs). • dB-linear volume and tone control (low microcontroller load) • Digital de-emphasis • Soft mute. Advanced audio output configuration • Stereo line output (under microcontroller volume control) On board amplifiers convert the output current to a voltage signal capable of driving a line output. The signal is also used to feed the integrated headphone amplifiers. The volume of the headphone is controlled by an external potentiometer. • Stereo headphone output (under 5-tap potentiometer volume control) • Line output independent of headphone output volume • Power on/off click prevention circuitry The TDA1388T has special sound processing features for use in CD-ROM audio applications, which can be controlled by static pins or microcontroller interface. These functions are de-emphasis, volume, bass boost, treble, soft mute and the channel manipulation functions needed for ATAPI-compliant functionality in CD-ROM audio processing. • High linearity, dynamic range, low distortion. General • Integrated digital filter plus DAC plus headphone driver • No analog post filter required • Easy application • Functions controllable by static pins or by microcontroller interface • 5 V power supply • Low power consumption • Small package size (SO28 and SSOP28). 1995 Dec 08 2 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA1388T SO28 TDA1388TZ SSOP28 DESCRIPTION VERSION plastic small outline package; 28 leads; body width 7.5 mm. SOT136-1 plastic shrink small outline package; 28 leads; body width 5.3 mm. SOT341-1 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage note 1 4.5 5.0 5.5 V IDD supply current note 2 − 22 − mA VFS(rms) full-scale output voltage (RMS value) VDD = 5 V 0.9 1.0 1.1 V (THD+N)/S total harmonic distortion plus noise as a function of signal for the line output 0 dB signal − −85 −80 dB RL = 5 kΩ − 0.006 0.013 % −60 dB signal − −35 −30 dBA RL = 5 kΩ − 1.8 3.2 % 0 dB signal − −65 −60 dB RL = 16 Ω − 0.056 0.1 % 0 dB signal − −70 − dB RL = 32 Ω − 0.032 − % −60 dB signal − −35 −30 dBA RL = 16 Ω or RL = 32 Ω − 1.8 3.2 % A-weighted; at code 00000H 90 95 − dBA fsys = 256fs − 64fs − bits fsys = 384fs − 48fs − bits total harmonic distortion plus noise as a function of signal for the headphone output S/N signal-to-noise ratio BR input bit rate at data input fsys system clock frequency 8.192 − 18.432 MHz Tamb operating ambient temperature −20 − +70 °C Notes 1. All VDD and VSS pins must be connected to the same supply or ground respectively. 2. Measured at input code 00000H and VDD = 5 V. 1995 Dec 08 3 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T BLOCK DIAGRAM IF1 IF2 DATA 7 8 11 WS BCK 10 ACP 9 19 SERIAL DATA INPUT SYSCLK SYSSEL 14 CHANNEL INTERCHANGE TIMING 15 18 DE-EMPHASIS APPL2 VOLUME CONTROL TC 20 FEATURE CONTROL UNIT BASS BOOST AND TREBLE 17 APPL1 SOFT MUTE VDDD 12 FILTER STAGE 1 + 2 16 4fs VSSD SAMPLE-AND-HOLD 16 × OVERSAMPLING 13 TDA1388 FILTCL 5 RCONV1 − 4 VDDA Vref 2nd-ORDER NOISE SHAPER 64fs 2nd-ORDER NOISE SHAPER DATA ENCODER DATA ENCODER 22 23 16 (4-BIT) CALIBRATED CURRENT SOURCES 16 (4-BIT) CALIBRATED CURRENT SOURCES LEFT OUTPUT SWITCHES RIGHT OUTPUT SWITCHES + VOL 16 (4-BIT) CALIBRATED CURRENT SINKS REFERENCE SOURCE 24 25 + 16 (4-BIT) CALIBRATED CURRENT SINKS 28 21 + REFERENCE SOURCE − 26 − 30 kΩ 30 kΩ 30 kΩ 2 27 30 kΩ MGD015 HPOUTR HPOUTL Fig.1 Block diagram. 1995 Dec 08 4 VSSA FILTCR − 1 3 VDDA RCONV2 6 + HPINL APPL0 VOR VDDO VSSO1 VSSO2 HPINR Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T PINNING SYMBOL PIN DESCRIPTION VSSO 1 operational amplifier ground HPOUTL 2 left headphone output voltage HPINL 3 left headphone input voltage VOL 4 left channel audio voltage output FILTCL 5 capacitor for left channel 1st-order filter function, should be connected between this pin and VOL (pin 4) Vref 6 internal reference voltage IF1 7 input format selection 1 IF2 8 input format selection 2 BCK 9 bit clock input WS 10 word selection input DATA 11 data input VDDD 12 digital supply voltage VSSD 13 digital ground SYSCLK 14 system clock 256fs or 384fs SYSSEL 15 system clock selection APPL0 16 application mode 0 input APPL1 17 application mode 1 input APPL2 18 application mode 2 input ACP 19 TC handbook, halfpage 28 VDDO VSSO1 1 HPOUTL 2 27 HPOUTR HPINL 3 26 HPINR VOL 4 25 VOR FILTCL 5 24 FILTCR Vref 6 23 VSSA IF1 7 TDA1388 IF2 8 22 VDDA 21 VSSO2 20 TC BCK 9 19 ACP WS 10 DATA 11 18 APPL2 application control input VDDD 12 17 APPL1 20 test control VSSD 13 16 APPL0 n.c. 21 not connected VDDA 22 analog supply voltage VSSA 23 analog ground FILTCR 24 capacitor for right channel 1st-order filter function, should be connected between this pin and VOR (pin 25) VOR 25 right channel audio voltage output HPINR 26 right headphone input voltage HPOUTR 27 right headphone output voltage VDDO 28 operational amplifier supply voltage 1995 Dec 08 15 SYSSEL SYSCLK 14 MGD014 Fig.2 Pin configuration. 5 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications FUNCTIONAL DESCRIPTION Table 2 The TDA1388T CMOS DAC incorporates an up-sampling digital filter, a sample-and-hold register, a noise shaper, continuously calibrated current sources, line amplifiers and headphone amplifiers. The 1fs input data is increased to an oversampled rate of 64fs. This high-rate oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple 1st-order analog post-filtering. IF1 IF2 FORMAT 0 0 I2S-bus 0 1 LSB-justified, 16 bits 1 0 LSB-justified, 18 bits 1 1 LSB-justified, 20 bits Input mode The TDA1388T accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256fs and 384fs. The system clock must be locked in frequency to the I2S-bus input signals. The TDA1388T has two input modes, a static-pin mode and a microcontroller mode. In the static-pin mode, the digital sound processing features such as mute left, mute right and de-emphasis are controlled by external pins. The other digital sound processing features have a default value. In the microcontroller mode, all the digital sound processing features can be controlled by the microcontroller. The controllable features are; System clock selection SYSSEL DESCRIPTION 0 256fs • Volume left channel. 1 384fs • Volume right channel. • De-emphasis. • Flat/min/max switch. Multiple format input interface • Bass boost. The TDA1388T supports the following data input formats; • Treble. • I2S-bus with data word length of up to 20 bits. • Channel manipulation modes. • LSB justified serial format with data word length of 16, 18 or 20 bits. Table 3 Data input formats The input formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. System clock Table 1 TDA1388T The selection of one of the two modes is controlled by the ACP pin. When this pin is at logic 0 then the static pin mode will be selected. When the pin is at logic 1 then the microcontroller mode will be selected. Selectable values of the digital sound processing features FEATURES STATIC-PIN MODE MICROCONTROLLER MODE De-emphasis 0 Hz or 44.1 kHz 0 Hz or 44.1 kHz Volume left channel 0 dB (fixed) 0 dB to −∞ dB Volume right channel 0 dB (fixed) 0 dB to −∞ dB Flat/min/max switch flat (fixed) flat/min/max Bass boost flat set (fixed) flat, min or max set Treble flat set (fixed) flat, min or max set Mute left channel external pin selectable (see Table 4) Mute right channel external pin selectable (see Table 4) L_CHANNEL = L (fixed) see Table 10 Channel manipulation modes R_CHANNEL = R (fixed) 1995 Dec 08 6 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications STATIC-PIN MODE Table 5 In the static-pin mode most of the features have a default value (see Table 3). The features that are controlled by the external pins are, mute left channel, mute right channel and de-emphasis. Table 4 External pin feature control in the static-pin mode PIN FEATURE APPL0 mute left channel APPL1 mute right channel APPL2 de-emphasis Selection of data transfer BIT 1 BIT 0 TRANSFER 0 0 data (volume left, volume right, bass boost and treble) 0 1 not used 1 0 status (de-emphasis, mode and channel-manipulation) 1 1 not used Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the TDA1388T is 000101 (bit 7 to bit 2). In the event that the TDA1388T receives a different address, it will deselect its microcontroller interface logic. MICROCONTROLLER MODE The exchange of data and control information between the microcontroller and the TDA1388T is accomplished through a serial hardware interface comprising the following pins; Data transfer mode The selection preformed in the address mode remains active during subsequent data transfers, until the TDA1388T receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.4. The maximum input clock and data rate is 64fs. All transfers are bitwise, i.e. they are based on groups of 8 bits. Data will be stored in the TDA1388T after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.6. APPL0: microcontroller interface data line. APPL1: microcontroller interface mode line. APPL2: microcontroller interface clock line. Information transfer through the microcontroller bus is organized in accordance with the so-called ‘L3’ format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 5). Programming the sound processing and other features The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode, BIT 1 and BIT 0 (see Table 5). The second selection is performed by the 2 MSBs of the data byte (BIT 7 and BIT 6). The other bits in the data byte (BIT 5 to BIT 0) is the value that is placed in the selected registers. The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the TDA1388T can only be in one direction, input to the TDA1388T to program its sound processing and other functional features. Address mode When the data transfer of type “data” is selected, the features VOLUME_R, VOLUME_L, BASS BOOST and TREBLE can be controlled. When the data transfer of type “status” is selected, the features MODE, DE-EMPHASIS, CHANNEL_MANIP_R and CHANNEL_MANIP_L can be controlled. The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by APPL1 being LOW and a burst of 8 pulses on APPL2, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 0 to 1 indicate the type of the subsequent data transfer as shown in Table 5. Table 6 TDA1388T Data transfer of type “status” BIT 7 BIT6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 M1 M0 DE OR1 OR0 OL1 OL0 1995 Dec 08 7 REGISTER SELECTED MODE (1 : 0), DEEMPHASIS, CHANNEL_MANIP_R (1 : 0), CHANNEL_MANIP_L (1 : 0) Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications Table 7 TDA1388T Data transfer of type “data” BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 VR5 VR4 VR3 VR2 VR1 VR0 VOLUME_R (5 : 0) 0 1 VL5 VL4 VL3 VL2 VL1 VL0 VOLUME_L (5 : 0) 0 X(1) BB4 BB3 BB2 BB1 BB0 BASS BOOST (4 : 0) 1 X(1) TR4 TR3 TR2 TR1 TR0 TREBLE (4 : 0) 1 1 REGISTER SELECTED Note 1. X = don’t care MODE: a 2-bit value to program the mode of the sound processing filters of Bass Boost and Treble. There are three modes: flat, min and max. DE-EMPHASIS: a 1-bit value to enable the digital de-emphasis filter. Table 9 Table 8 The flat/min/max switch De-emphasis DEEM FUNCTION MODE 1 MODE 0 FUNCTION 0 no de-emphasis 0 0 flat 1 de-emphasis, 44.1 kHz 0 1 min 1 0 min 1 1 max CHANNEL_MANIP_R and CHANNEL_MANIP_L: both are a 2 bit value to program the right or left channel manipulation. Table 10 Channel manipulation modes CHANNEL_MANIP_L<1 : 0> CHANNEL_MANIP_R<1 : 0> L_CHANNEL R_CHANNEL 00 00 MUTE MUTE 00 01 MUTE R 00 10 MUTE L 00 11 MUTE (L + R)/2 01 00 R MUTE 01 01 R R 01 10 R L 01 11 R (L + R)/2 10 00 L MUTE 10 01 L R 10 10 L L 10 11 L (L + R)/2 11 00 (L + R)/2 MUTE 11 01 (L + R)/2 R 11 10 (L + R)/2 L 11 11 (L + R)/2 (L + R)/2 1995 Dec 08 8 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T VOLUME_R: a 6-bit value to program the right channel volume attenuation (VR5 to VR0). The range is 0 dB to −∞ dB in steps of 1 dB. Table 11 Volume right settings VR5 VR4 VR3 VR2 VR1 VR0 VOLUME (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 −1 0 0 0 0 1 1 −2 : : : : : : : 1 1 1 0 1 1 −58 1 1 1 1 0 0 −59 1 1 1 1 0 1 −60 1 1 1 1 1 0 −∞ 1 1 1 1 1 1 −∞ VOLUME_L: a 6-bit value to program the left channel volume attenuation (VL5 to VL0). The range is 0 dB to −∞ dB in steps of 1 dB. Table 12 Volume left settings VR5 VR4 VR3 VR2 VR1 VR0 VOLUME (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 −1 0 0 0 0 1 1 −2 : : : : : : : 1 1 1 0 1 1 −58 1 1 1 1 0 0 −59 1 1 1 1 0 1 −60 1 1 1 1 1 0 −∞ 1 1 1 1 1 1 −∞ 1995 Dec 08 9 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T BASS BOOST: a 5-bit value to program the bass boost setting. The used set depends on the MODE bits. Table 13 Bass boost settings BASS BOOST BB4 BB3 BB2 BB1 BB0 FLAT SET (dB) MIN SET (dB) MAX SET (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 2 2 0 0 1 0 1 0 2 2 0 0 1 1 1 0 4 4 0 0 1 1 0 0 4 4 0 1 0 0 1 0 6 6 0 1 0 0 0 0 6 6 0 1 0 1 1 0 8 8 0 1 0 1 0 0 8 8 0 1 1 0 1 0 10 10 0 1 1 0 0 0 10 10 0 1 1 1 1 0 12 12 0 1 1 1 0 0 12 12 1 0 0 0 0 0 14 14 1 0 0 0 1 0 14 14 1 0 0 1 0 0 16 16 1 0 0 1 1 0 16 16 1 0 1 0 0 0 18 18 1 0 1 0 1 0 18 18 1 0 1 1 1 0 18 20 1 0 1 1 0 0 18 20 1 1 0 0 1 0 18 22 1 1 0 0 0 0 18 22 1 1 0 1 1 0 18 24 1 1 0 1 0 0 18 24 : : : : : : : : 1 1 1 1 0 0 18 24 1995 Dec 08 10 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T TREBLE: a 5-bit value to program the treble setting. The used set depends on the MODE bits. Table 14 Treble settings TREBLE TR4 TR3 TR2 TR1 TR0 FLAT SET (dB) MIN SET (dB) MAX SET (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 2 2 0 0 1 0 1 0 2 2 0 0 1 1 1 0 2 2 0 0 1 1 0 0 2 2 0 1 0 0 1 0 4 4 0 1 0 0 0 0 4 4 0 1 0 1 1 0 4 4 0 1 0 1 0 0 4 4 0 1 1 0 1 0 6 6 0 1 1 0 0 0 6 6 0 1 1 1 1 0 6 6 0 1 1 1 0 0 6 6 : : : : : : : : 1 1 1 1 0 0 6 6 • Normal stereo output. Flat/min/max setting selection • Left/right reverse output. In the TDA1388T has three setting for the digital sound features bass boost and treble. The possible settings are called ‘flat’, ‘min’ and ‘max’. The flat setting has no influence on the audio signal, the minimum setting has a small influence on the audio signal and the maximum setting has a large influence on the audio signal. In the static-pin mode, the flat setting is used for the bass boost and treble filters. In the microcontroller mode, all three settings can by controlled by a register. • Mono left/right output: (L + R)/2. • Output muting with soft mute. De-emphasis De-emphasis is controlled by an external pin in the static-pin mode and by a register in the microcontroller mode.The digital de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 kHz. With its 18-bit dynamic range, the digital de-emphasis filter of the TDA1388T is a convenient and component saving alternative to analog de-emphasis. De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples. Channel manipulation modes In the TDA1388T there is a channel manipulation function implemented. This function has a fixed value in the static-pin mode, the left signal on the left channel and the right signal on the right channel. In the microcontroller mode several option are possible. The different modes are as follows; 1995 Dec 08 11 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications When the mute is active for a channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. 32 coefficients are used to step down the value of the data, each one being used 32 times before stepping on to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in the reverse order. The mute, on the left or right channel, is synchronized to the sample clock, so that operation always takes place on complete samples. Volume control The volume of the left and right channels are controlled by a fixed value (0 dB) in the static-pin mode and by separate registers in the microcontroller mode. In the microcontroller mode the values of both channels can vary, independent of each other, from 0 dB to −∞ dB. Since there is no headroom included into the sound control section, the volume control precedes the sound control. Full volume and neutral setting (flat) of the sound control results in full-scale output. Any tone boost will directly cause clipping, which can be avoided by reduction of the volume setting. Oversampling and noise shaper The digital filter is four times oversampling filter. It consists of two sections which each increase the sample rate by 2. The 2nd-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique used in combination with a sign-magnitude coding enables high signal-to-noise ratios to be achieved. The noise shaper outputs a 5-bit PDM bitstream signal to the DAC. Bass boost A strong bass boost effect, which is useful in compensating for poor response of portable headphone sets, is implemented digitally in the TDA1388T and can be controlled in the microcontroller mode. In the static-pin mode, the flat setting is fixed. In the microcontroller mode, valid settings range from flat (no influence on audio) to +18 dB with step sizes of 2 dB in minimum and to +24 dB with step sizes of 2 dB in maximum. The programmable bass boost filter is a 2nd-order shelving type with a fixed corner frequency of 130 Hz for the minimum setting and a fixed corner frequency of 230 Hz for the maximum setting and has a Butterworth characteristic. Because of the exceptional amount of programmable gain, bass boost should be used with adequate prior attenuation, using the volume control. Continuous calibration DAC The dual 5-bit DAC uses the continuous calibration technique. This method, based on charge storage, involves exact duplication of a single reference current source. In the TDA1388T, 32 such current sources plus 1 spare source are continuously calibrated. The spare source is included to allow continuous convertor operation. The DAC receives a 5-bit data bitstream from the noise shaper. This data is converted so that no current is switched to the output during digital silence (input 00000H). In this way very high signal-to-noise performance is achieved. Treble A treble effect is implemented digitally in the TDA1388T and can be controlled in the microcontroller mode. In the static-pin mode, the flat setting is fixed. In the microcontroller mode, valid settings range from flat (no influence on audio) to +6 dB with step sizes of 2 dB in minimum and to +6 dB with step sizes of 2 dB in maximum. The programmable treble filter is a 1st-order shelving type with a fixed corner frequency of 2.8 kHz for the minimum setting and a fixed corner frequency of 5.0 kHz for the maximum setting. Because of the exceptional amount of programmable gain, treble should be used with adequate prior attenuation, using the volume control. Stereo line driver High precision, low-noise amplifiers together with the internal conversion resistor RCONV1 and RCONV2 convert the converter output current to a voltage capable of driving a headphone. The voltage is available at VOL and VOR (pins 4 and 25). Stereo headphone driver High precision, low-noise amplifiers are capable of driving a headphone load. The voltage is available at HPOUTL and HPOUTR (pins 2 and 27). Soft mute Soft mute is controlled by external pins, for each channel one, in the static-pin mode and by the channel manipulation modes of left or right in the microcontroller mode. 1995 Dec 08 TDA1388T 12 1995 Dec 08 13 DATA BCK WS DATA BCK WS DATA BCK WS DATA BCK WS 1 MSB 2 B2 3 LEFT MSB 20 B2 19 B3 18 LEFT MSB 18 LEFT LEFT B4 17 B2 17 1 2 16 B5 16 B3 16 B6 15 B4 15 B2 15 LSB MSB MSB >=8 B2 1 S-BUS >=8 LSB 1 LSB 1 LSB-JUSTIFIED FORMAT 20 BITS B19 2 LSB-JUSTIFIED FORMAT 18 BITS B17 2 LSB-JUSTIFIED FORMAT 16 BITS B15 LSB 2 INPUT FORMAT I2 Fig.3 Input formats. 3 RIGHT 20 MSB LSB MSB B2 19 B3 18 MSB 18 B4 17 B5 16 RIGHT B2 16 B3 RIGHT 17 16 MSB RIGHT B6 15 B4 15 B2 15 1 LSB B19 MGD019 1 LSB B17 2 1 2 B15 LSB 2 Bitstream continuous calibration filter-DAC for CD-ROM audio applications handbook, full pagewidth Philips Semiconductors Objective specification TDA1388T Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T handbook, full pagewidth L3MODE t s;MA t h;MA tLC tHC t s;MA t h;MA L3CLOCK Tcy t s;DAT t h;DAT BIT 7 BIT 0 L3DATA MGD016 Fig.4 Timing address mode. handbook, full pagewidth thalt thalt L3MODE tLC t s;MT Tcy tHC t h;MT L3CLOCK t h;DAT L3DATA write t s;DAT BIT 0 t h;DAT BIT 7 MGD017 Fig.5 Timing for data transfer mode. 1995 Dec 08 14 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T thalt handbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGD018 Fig.6 Multibyte transfer. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground, VDDD = VDDA = VDDO 5 V; Tamb = 25 °C, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 7.0 V maximum crystal temperature − +150 °C storage temperature −65 +125 °C Tamb operating ambient temperature −20 +70 °C Ves electrostatic handling VDD supply voltage Txtal(max) Tstg note 1 note 2 −3000 +3000 V note 3 −300 +300 V Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. 1995 Dec 08 15 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER VALUE UNIT SOP28 tbf K/W SSOP28 tbf K/W thermal resistance from junction to ambient in free air DC CHARACTERISTICS VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins 1, 13 and 23); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage note 1 4.5 5.0 5.5 V VDDA analog supply voltage note 1 4.5 5.0 5.5 V VDDO operational amplifier supply voltage note 1 4.5 5.0 5.5 V IDDD digital supply current at digital silence − 7.0 − mA IDDA analog supply current at digital silence − 5.0 − mA IDDO operational amplifier supply current at digital silence − 10 − mA Ptot total power dissipation note 2 − 110 − mW Digital input pins VIH HIGH level input voltage 0.7VDDD − VDDD + 0.5 V VIL LOW level input voltage − − 0.3VDDD V |ILI| input leakage current − − 10 µA Cin input capacitance − − 10 pF 0.45VDDA 0.5VDDA 0.55VDDA V Analog audio pins Vref reference voltage Rout(ref) output reference resistance − 3 − kΩ RCONV current-to-voltage conversion resistor − 2.0 − kΩ Io(max) maximum output current (THD+N)/S < 0.1% RL = 32 Ω − 88 − mA (THD+N)/S < 0.1% RL = 16 Ω − 44 − mA note 3 − − 50 pF CL output load capacitance with respect to VSSA Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. No operational amplifier load resistor. 3. Load capacitance larger than 50 pF, a 22 µH inductor in parallel with a 270 Ω resistor must be inserted between the load and the operational amplifier output. 1995 Dec 08 16 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 5 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ all voltages referenced to ground (pins 1, 13 and 23); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT − − 18 bits 0.9 1.0 1.1 V − 20 − mV supply voltage ripple rejection VDDA and VDDO − fripple = 1 kHz; Vripple(p-p) = 100 mV(peak); Cpin = 10 µF 40 − dB |∆Vo| unbalance between the 2 DAC voltage outputs maximum volume − 0.1 − dB αct crosstalk between the 2 DAC voltage outputs for line outputs RL = 5 kΩ, note 2 − 90 − dB crosstalk between the 2 DAC voltage outputs for headphone outputs RL = 16 kΩ, note 2 − 60 − dB RL = 32 kΩ, note 2 − 65 − dB total harmonic distortion plus noise as a function of signal for the line output 0 dB signal − −85 −80 dB RES resolution VFS(rms) output voltage swing (RMS value) VDC(os) output voltage DC offset with respect to reference voltage level Vref SVRR (THD+N)/S total harmonic distortion plus noise as a function of signal for the headphone output S/N signal-to-noise ratio at bipolar zero note 1 RL = 5 kΩ − 0.006 0.013 % −60 dB signal − −35 −30 dBA RL = 5 kΩ − 1.8 3.2 % 0 dB signal − −65 −60 dB RL = 16 kΩ − 0.056 0.1 % 0 dB signal − −70 − dB RL = 32 kΩ − 0.032 − % −60 dB signal − −35 −30 dBA RL = 16 kΩ or RL = 32 kΩ − 1.8 3.2 % A weighting; at code 00000H 90 95 − dBA Notes 1. Proportional to VDDA. 2. One output digital silence, the other maximum volume. 1995 Dec 08 17 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 4.5 to 5.5 V; Tamb = −20 to +70 °C; RL = 5 kΩ; all voltages referenced to ground (pins 1, 13 and 23); unless otherwise specified. SYMBOL Tcy PARAMETER clock cycle CONDITIONS MIN. TYP. MAX UNIT fsys = 256fs 81.3 88.6 122 ns fsys = 384fs 54.2 59.1 81.3 ns tCWL fsys LOW level pulse width 22 − − ns tCWH fsys HIGH level pulse width 22 − − ns fsys = 256fs − 64fs − fsys = 384fs Serial input data timing (see Fig.7) BR clock input = data input rate − 48fs − fsys system clock frequency 8.192 − 18.432 MHz fWS word selection input frequency − 44.1 48 kHz tr rise time − − 20 ns tf fall time − − 20 ns tBCK(H) bit clock HIGH time 55 − − ns tBCK(L) bit clock LOW time 55 − − ns ts;DAT data set-up time 10 − − ns th;DAT data hold time 20 − − ns ts;WS word selection set-up time 20 − − ns th;WS word selection hold time 10 − − ns Fig.7 Timing and input signals. 1995 Dec 08 18 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T TEST AND APPLICATION INFORMATION +5 V handbook, full pagewidth 100 µF 4.7 Ω 100 nF 4.7 Ω 100 nF 100 µF 100 nF (1) L3 (2) (1) SYSTEM CLOCK INPUT 330 µF 100 nF VSSD VDDD VSSA VDDA VSSO1 VDDO Vref 23 22 1 28 13 12 SYSCLK 14 6 BCK 2 I S-BUS OR LSB-JUSTIFIED SERIAL INPUT DATA WS DATA IF1 IF2 ACP from MICROCONTROLLER APPL2/CL APPL1/MO APPL0/DA SYSSEL VSSO2 TC 100 nF 9 10 11 5 4 FILTCL VOL 1 nF 47 µF 8 19 2 18 17 27 16 24 15 25 20 26 (1) Optional. (2) Chip inductor BLM32A07. Fig.8 Application diagram. R1 10 kΩ HPOUTL HPOUTR 330 µF FILTCR 330 µF VOR 21 19 4.7 µF 3 HPINL TDA1388 100 Ω L 7 MGD152 1995 Dec 08 10 µF HPINR 1 nF 47 µF 100 Ω R 4.7 µF R1 10 kΩ Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.10 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013AE 1995 Dec 08 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 20 o 8 0o Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 pin 1 index A (A 3) A1 θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1995 Dec 08 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 21 o Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T SOLDERING SSOP Introduction Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Reflow soldering Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. METHOD (SO AND SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering SO Repairing soldered joints Wave soldering techniques can be used for all SO packages if the following conditions are observed: Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1995 Dec 08 22 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Dec 08 23 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 513061/1100/01/pp24 Document order number: Date of release: 1995 Dec 08 9397 750 00516