INTEGRATED CIRCUITS DATA SHEET SAA7710T Dolby* Pro Logic Surround; Incredible Sound Product specification Supersedes data of 1997 Oct 03 File under Integrated Circuits, IC01 1998 Mar 13 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T FEATURES • Two stereo I2S-bus digital input channels • Three stereo I2S-bus digital output channels • I2C-bus mode control • Up to 45 ms on-chip delay-line (fs = 44.1 kHz) • Optional clock divider for crystal oscillator • Hall/matrix surround sound functions • Package: SO32L • Incredible sound functions • Operating supply voltage range: 4.5 to 5.5 V. • 5-band parametric equalizer on main channels left, centre, right (fs = 32 kHz) Functions • Tone control (bass/treble) on all four output channels (fs = 44.1 kHz). • 4-channel active surround, 20 Hz to 20 kHz (maximum 1⁄2fs) • Adaptive matrix GENERAL DESCRIPTION • 7 kHz low-pass filters This data sheet describes the 104 ROM-code version of the SAA7710T chip. The SAA7710T chip is a high quality audio-performance digital add-on processor for digital sound systems. It provides all the necessary features for complete Dolby Pro Logic surround sound on chip. In addition to the Dolby Pro Logic surround function, this device also incorporates a 5-band parametric equalizer, a tone control section and a volume control. Instead of Dolby Pro Logic surround, the Hall/matrix surround and Incredible sound functions can be used together with the equalizer or tone control. • Adjustable delay for surround channel • Modified Dolby B noise reduction • Noise sequencer • Variable output matrix • Sub woofer • Centre mode control: on/off, normal, phantom, wide • Output volume control • Automatic balance and master level control with DC-offset filter QUICK REFERENCE DATA SYMBOL VDD ∆VDD Vi IDD ISS Tamb Tstg PARAMETER MIN. −0.5 − −0.5 − − −40 −65 DC supply voltage voltage difference between two VDDx pins maximum input voltage DC supply current DC supply current ambient operating temperature storage temperature range MAX. +6.5 550 VDD + 0.5 50 50 +85 +150 UNIT V mV V mA mA °C °C Remark Dolby*: Dolby’ and ‘Pro Logic’ are trademarks of Dolby Laboratories Licensing Corporation. They are available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. ORDERING INFORMATION TYPE NUMBER SAA7710T/N104 1998 Mar 13 PACKAGE NAME SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm 2 VERSION SOT287-1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 23 I2S_WSOUT SAA7710T S 24 I2S_BCKOUT SURROUND CHANNEL DELAY LINE I2S_DATAIN2 I2S input 2 I2S_BCKIN2 I2S_WSIN2 DSP_RESET 3 TSCAN RTCB I2S INPUT SWITCH CIRCUIT 25 I2S OUT 1 L data 1 27 26 17 DOLBY PRO LOGIC OR DOLBY 3 STEREO OR HALL/MATRIX OR INCREDIBLE SOUND C R SW 5-BAND PARAMETRIC EQUALIZER OR TONE CONTROL VARIABLE OUTPUT MATRIX I2S OUT 2 I2S OUT 3 I2S_DATAOUT1 29 I2S_DATAOUT2 30 I2S_DATAOUT3 5 13 + TEST 3 12 AUTO BALANCE FUNCTION + 32 19 I2C BUS TRANSCEIVER FLAG TEST CONTROL 18 11 31 8 10 SDA 16 SCL VDD3 VDD_XTAL 14 A0 DSP_OUT2 Fig.1 Block diagram. 21 OSC 20 XTAL VSS_XTAL VSS1 VSS2 VSS3 4 SHTCB MGE751 Product specification DSP_OUT1 DSP_IN2 15 VDD2 SAA7710T DSP_IN1 9 VDD1 OSCILLATOR 6 7 I2S outputs 28 Philips Semiconductors I2S_DATAIN1 2 Dolby* Pro Logic Surround; Incredible Sound I2S_WSIN1 22 BLOCK DIAGRAM I2S input 1 handbook, full pagewidth 1998 Mar 13 I2S_BCKIN1 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T PINNING SYMBOL I2S_WSOUT PIN 1 DESCRIPTION I2S-bus slave word-select output I2S_BCKOUT 2 I2S-bus slave bit-clock output RTCB 3 asynchronous reset test control block input (active LOW) SHTCB 4 clock divider switch enable input (LOW = divide) VDD1 5 positive power supply VSS1 6 ground power supply DSP_IN1 7 flag input 1 DSP_IN2 8 flag input 2 DSP_OUT1 9 DSP_OUT2 handbook, halfpage I2S_WSOUT 1 32 VDD3 I2S_BCKOUT 2 31 VSS3 RTCB 3 30 I2S_DATAOUT3 flag output 1 SHTCB 4 29 I2S_DATAOUT2 10 flag output 2 VDD1 5 28 I2S_DATAOUT1 VSS2 11 ground power supply VSS1 6 27 I2S_BCKIN2 VDD2 12 positive power supply DSP_IN1 7 26 I2S_WSIN2 TSCAN 13 scan control input 8 14 I2C-bus slave address selection input DSP_IN2 A0 DSP_OUT1 DSP_OUT2 10 SDA 15 I2C-bus serial data input/output SCL 16 I2C-bus serial clock input 25 I2S_DATAIN2 SAA7710T 9 24 I2S_DATAIN1 23 I2S_WSIN1 VSS2 11 22 I2S_BCKIN1 VDD2 12 21 OSC DSP_RESET 17 chip reset input (active LOW) VSS_XTAL 18 ground power supply crystal oscillator VDD_XTAL 19 positive power supply crystal oscillator A0 14 19 VDD_XTAL SDA 15 18 VSS_XTAL XTAL 20 crystal oscillator output SCL 16 17 DSP_RESET OSC 21 crystal oscillator input I2S_BCKIN1 22 I2S-bus master bit-clock input 1 I2S_WSIN1 23 I2S-bus master word-select input 1 I2S_DATAIN1 24 I2S-bus master data input 1 I2S_DATAIN2 25 I2S-bus master data input 2 I2S_WSIN2 26 I2S-bus master word-select input 2 I2S_BCKIN2 27 I2S-bus master bit-clock input 2 I2S_DATAOUT1 28 I2S-bus slave data output 1 I2S_DATAOUT2 29 I2S-bus slave data output 2 I2S_DATAOUT3 30 I2S-bus slave data output 3 VSS3 31 ground power supply VDD3 32 positive power supply 1998 Mar 13 TSCAN 13 20 XTAL MGE750 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T • Equalizer (3- or 5-band on L, C and R) or tone control (L, C, R and S); fixed output matrix(1); volume control FUNCTIONAL DESCRIPTION Figure 1 shows the block diagram of the SAA7710T. The SAA7710T consists of a Dolby Pro Logic decoder together with equalizer or tone control. The Dolby Pro Logic part of the IC may be used to decode audio soundtracks (Dolby surround movies or Dolby surround video productions) from for example, a video recorder (VCR) or a CD laser disc into four channels Left, Centre, Right and Surround (L, C, R and S). If desired, post-processing with either an equalizer or a tone control section is possible. In addition to this, a Sub Woofer (SW) channel, digital volume control and a user-programmable variable output matrix are implemented. • Equalizer (5-band on L, C and R); variable output matrix(1); volume control • Extra sub woofer(1). THE DOLBY 3 STEREO MODE In Dolby 3 stereo mode, several blocks must be initialized and controlled during operation: • Noise generator and noise sequencer • Centre channel mode(1) (normal, phantom, wide and off) • Combining network coefficients • Incredible Sound widening of the stereo base on two speakers Hall/matrix surround sound functions are implemented for material not encoded using Dolby Surround. These features can be used as an alternative to Dolby Pro Logic and can also be combined with the equalizer or tone control sections. • Effect is user adjustable. THE HALL/MATRIX SURROUND MODE In hall/matrix surround mode, the blocks listed below must be initialized and controlled during operation: Incredible sound is a Philips patented technology which substantially improves the stereo effect of a television or audio system. Using advanced signal processing, speakers that are positioned close together can imitate the sound produced by speakers that are far apart. • Input balance control • Hall or matrix surround Mode setting • All-pass and filter transfer characteristics(1) • 7 kHz low-pass filter in surround channel(1) Functional modes • Surround channel delay(1). The device thus supports three main modes, Dolby Pro Logic/Dolby 3 stereo or hall/matrix surround or Incredible sound mode. All modes can be combined with equalizing (3-band or 5-band) or tone control depending on fs and available cycle budget. Possible post-processing modes for hall/matrix surround are as above: • Volume control only • Equalizer (5-band on L, C and R) or tone control (L, C, R and S); fixed output matrix(1); volume control THE DOLBY PRO LOGIC MODE • Equalizer (5-band on L,C,R); variable output matrix(1); volume control In Dolby Pro Logic mode, several blocks must be initialized and controlled during operation: • Extra sub woofer(1). • Noise generator and noise sequencer • Centre channel mode(1) (normal, phantom, wide, off) THE INCREDIBLE SOUND MODE • Combining network coefficients • 7 kHz low-pass filter in surround channel(1) In the Incredible sound mode the blocks listed below must be initialized and controlled during operation: • Surround channel delay time(1) • Incredible sound coefficients • Modified Dolby B noise reduction must be on. • Combining network coefficients. Possible post-processing modes for Dolby Pro Logic are: Possible post-processing modes for incredible sound are as follows: • Volume control only • Volume control only • Equalizer (5-band on L and R) or tone control (L and R); variable output matrix(1), volume control (1) The coefficient set used to initialize and control the operation of the Dolby Pro Logic mode depends upon the selected sampling frequency fs = 32, 44.1 or 48 kHz. 1998 Mar 13 • Extra sub-woofer(1). 5 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T The slave oscillator mode: in this mode (see Fig.4), the oscillator circuit acts as a slave driven by a master system clock. The clock divider can be switched on or off using pin SHTCB. When the divider is not used, the duty cycle of the clock will depend on the master system clock duty cycle and the rising and falling edge times. This places a tolerance of 5% on the 50% duty cycle of the master system clock (see Chapter “AC characteristics”). ADDITIONAL INFORMATION The possible modes of operation are discussed in more detail in the “SAA7710T Dolby Pro Logic Programming Guide, Application Note AN95063”. This also includes which features are available for a given system clock frequency and sample frequency and the possible input configurations. Clock circuit and oscillator In order to be able to control the phase of the clock signal during testing the divider is skipped and the signal is directly fed to the circuit via the multiplexer in the TEST position. The chip has an on board crystal clock oscillator. The block schematic of this Pierce oscillator is shown in Figs 3 and 4. The active element needed to compensate for the loss resistance of the crystal is the amplifier Gm. This amplifier is placed between the XTAL (output) pin and the OSC (sense) pin. The gain of the oscillator is internally controlled by the automatic gain control. This prevents too much power loss in the crystal. The higher harmonics are then as low as possible. The signals on the OSC and XTAL pin are differentially amplified. SUPPLY OF THE CRYSTAL OSCILLATOR The power supply connections to the oscillator are separated from the other supply lines to minimise feedback from on-chip ground bounce to the oscillator circuit. Noise on the power supply affects the AGC operation so the power supply should be decoupled. The VSS_XTAL pin is used as ground supply and the VDD_XTAL as positive supply. The oscillator has these two modes of operation: The crystal oscillator mode: in this mode (see Fig.3), a quartz crystal oscillator is used to generate a clock signal which is subsequently divided by 2 to ensure that the final clock signal has a 50% duty cycle. The oscillator circuit components Rbias and C1, C2 depend on the crystal. In the case of an overtone oscillator, the ground harmonic is filtered out by L1 and C3. Pin SHTCB is held low so that the divided signal is selected. Only a quartz crystal should be used in this mode. 1998 Mar 13 6 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T handbook, full pagewidth DIVIDE BY 2 Gm AGC CLOCK BUFFER 0 1 TEST ON CHIP OFF CHIP 21 20 19 18 4 OSC XTAL VDD_XTAL VSS_XTAL SHTCB MGE752 =0 100 kΩ L1 4.7 µH Rbias C1 10 pF C3 1 nF C2 10 pF Fig.3 Block diagram crystal oscillator circuit. handbook, full pagewidth DIVIDE BY 2 Gm AGC CLOCK BUFFER 0 1 TEST ON CHIP OFF CHIP 21 20 19 18 4 OSC XTAL VDD_XTAL VSS_XTAL SHTCB =1 100 kΩ 40 pF 10 pF 10 nF slave input Fig.4 Block diagram slave oscillator circuit. 1998 Mar 13 7 MGE753 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T I2S-bus Interfaces and system clock I2S-BUS BASICS Tcy handbook, full pagewidth tLC≥0.35 T tHC≥0.35 T VIH (70%) SCK VIL (20%) tsr≥0.2 T SD thr≥0 VIH (70%) WS VIL (20%) SCK WS SD MSB LEFT MSB RIGHT MBH173 Fig.5 I2S-bus timing and format. For communication with external digital sources and or additional external processors the I2S-bus digital interface bus is used. It is a serial 3-line bus, with one line for data, one line for clock and one line for the word select. I2S-BUS INPUT CIRCUIT The I2S-bus input circuits can be configured in the following way using the SEL-IN1/IN2 bit (see Table 4): 1. I2S input 1 is master (SEL-IN1/IN2 bit = logic 0(default)) Figure 5 shows an excerpt of the Philips I2S-bus specification interface report regarding the general timing and format of I2S-bus. Word Select (WS) logic 0 means left channel word, logic 1 means right channel word. 2. I2S input 2 is master (SEL-IN1/IN2 bit = logic 1). The incoming bit-clock frequency defines the accuracy in terms of number of bits of the incoming data samples. The input circuit is designed to accept any number of bits per channel up to a maximum of 18 bits. The accepted data format is MSB-first. The serial data is transmitted in two’s complement with the MSB first. One clock period after the negative edge of the word select line the MSB of the left channel is transmitted. Data is synchronised with the negative edge of the clock and latched at the positive edge. 1998 Mar 13 8 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound Table 1 SAA7710T Data Accuracy in I2S-bus Interface I2S-BUS IN DATA WIDTH INCOMING DATA WIDTH I2S-BUS OUT DATA WIDTH A < 18 A A B ≥18 18 18 interface: I2S_WSOUT, I2S_BCKOUT. These two output signals can be 3-stated by setting the DIS_BCKWS bit (see Table 4). The 3-state output of the I2S_DATAOUT3 signal can be enabled by setting the ENA_I2S3 bit (see Table 4). THE I2S-BUS OUTPUT INTERFACE The I2S-bus data output interfaces (see Fig.1) I2S OUT 1, I2S OUT 2 and I2S OUT 3 use the same I2S-bus data signals which are selected by the input switch circuit. The I2S-bus WS and BCK output signals remain in phase with the external input signals at all times. The output data is 1/fs cycle delayed relative to the input data. The selected word-select and bit-clock are included as part of the output The timing diagram of the I2S-bus outputs is shown in Fig.6. The timing details can be found in Chapter “AC characteristics”. tLC handbook, full pagewidth I2S_BCKIN1, 2 I2S_BCKOUT CL tHC td1 tf tr tr tf I2S_WSIN1, 2 I2S_WSOUT WS ts2 DATA (in) td2 I2S_DATAIN1, 2 MSB DATA VALID td3 tr tf DATA (out) tacc MSB I2S_DATAOUT1, 2, 3 MGE755 Fig.6 Timing diagram of I2S-bus output interface. 1998 Mar 13 9 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T I2C-bus control and commands DATA TRANSFER CHARACTERISTICS OF THE I2C-BUS A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.9). The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the VDDX via a pull-up resistor when connected to the output stages of a microprocessor. Data transfer can only be initiated when the bus is not busy. ACKNOWLEDGE The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.10). BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 100 kHz (see Fig.7). START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Fig.8). handbook, full pagewidth SDA SCL data line stable data valid change of data allowed Fig.7 Bit transfer on the I2C-bus. 1998 Mar 13 10 MLC160 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T andbook, full pagewidth SDA SCL S P START condition STOP condition MLC161 Fig.8 START and STOP conditions. handbook, full pagewidth SDA MSB SCL 1 S acknowledgement signal from receiver acknowledgement signal from receiver byte complete interrupt within receiver clock line held LOW while interrupts are serviced 2 7 8 9 1 ACK START condition 2 3 to 8 9 P STOP condition MLC162 Fig.9 Data transfer on the I2C-bus. 1998 Mar 13 11 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T handbook, full pagewidth data output from transmitter not acknowledge data output from receiver acknowledge SCL from master 1 2 7 8 9 MLC163 S clock pulse for acknowledgement START condition Fig.10 Acknowledge on the I2C-bus. I2C-BUS FORMAT Write cycles Addressing The I2C-bus configuration for a write cycle is shown in Fig 12. The write cycle is used to write in the input selector control register and to initialise or update coefficient values. Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the START procedure. The data length is 2 bytes or 3 bytes depending of the accessed memory. If the Y-memory is addressed the data length is 2 bytes, in case of the X-memory the length is 3 bytes. The slave receiver detects the address and adjusts the bytes accordingly. Slave address (pin A0) The chip acts as a slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The chip slave address is shown in Table 2. Read cycles The I2C-bus configuration for a Read cycle is shown in Fig 13. The read cycle is used to read data values from XRAM or YRAM. The sub address bit A0 corresponds to the hardware address pin A0 which allows the device to have 1 of 2 different addresses. 1998 Mar 13 12 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T During the write cycle, the I2C-bus clock frequency must be reduced. I2C-BUS FUNCTION BITS Input selector control register The I2C-bus clock frequency has the following constraints: The write only, two byte, input selector control register is located on absolute address 0FFFH (4095) and consists of 16 bits, starting with bit 0 and ending with bit 15. fs > 2 × fIIC fs = I2S-bus sampling frequency fIIC = I2C-bus clock frequency. Deviation from the I2C-bus specification If this constraint cannot be met, a higher I2C-bus frequency can be obtained in the following way: 1. The data hold time (tHD;DAT) for this device (≥0 ns as stated in the I2C-bus specification) should be as follows: By making the I2C-bus master insert a delay (td) after the acknowledge pulse (see Fig.11). The delay should be larger than or equal to 1/fs where fs is the I2S-bus sampling frequency. a) For the crystal oscillator mode (SHTCB = 0): 6 ≥ --------- f xtal By not using the auto-increment feature. This means that each data word must be preceded by its intended destination address. b) For the slave oscillator mode (SHTCB = 0): 6 ≥ ------------- f slave c) For the slave oscillator mode (SHTCB = 1): 3 ≥ ------------- f slave handbook, full pagewidth SCL SDA ACKNOWLEDGE AFTER WORD auto-increment address register td Fig.11 Timing of reduced I2C-bus frequency. 1998 Mar 13 13 MGE756 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound Table 2 SAA7710T Slave address MSB LSB 0 Table 3 0 1 1 1 1 A0 R/W Location of input selector control register bits in I2C-bus serial transmission; note 1 MSB LSB DATAH 15 14 13 12 11 DATAL 10 9 8 A 7 6 5 4 3 2 1 0 A P Note 1. Explanation for the contents of the register bits: a) A = standard I2C-bus acknowledge. b) Number = bit number according to Table 4. c) P = standard I2C-bus STOP condition. Table 4 Input selector control bits SYMBOL FUNCTION NUMBER OF BITS ON RESET BIT NO SEL-IN1/IN2 I2S input 1 or I2S input 2 input 1 IN1(0) 5 DIS_BCKWS disable I2S_BCKOUT 1 enable(0) 7 ENA-I2S3 enable I2S_DATAOUT3 1 disable(0) 13 IMODE I flag resets/background tasking 1 resets(0) 15 and I2S_WSOUT XRAM format The XRAM block consists of 256 18-bit RAM locations 0 to 255 and is located on the absolute address range of 0000H to 00FFH. The I2C-bus transfer consists of 18 useful bits out of 24 bits. Table 5 Format XRAM bits; note 1 MSB LSB DATAH D D D D D DATAM D 17 16 A 15 14 13 12 11 10 Note 1. Explanation for the contents of the register bits: a) D = contents of I2C-bus data register bit is don’t care. b) A = standard I2C-bus acknowledge. c) Number = bit number being useful bit XRAM memory. d) P = standard I2C-bus STOP condition. 1998 Mar 13 14 DATAL 9 8 A 7 6 5 4 3 2 1 0 A P Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T YRAM format The YRAM block consists of 256 12-bit RAM locations 0 to 255 and is located on the absolute address range of 0800H to 08FFH. The I2C-bus transfer consists of 12 useful bits out of 16 bits. Table 6 Format YRAM bits; note 1 MSB LSB DATAH D D D D 11 DATAM 10 9 8 A 7 6 5 4 3 2 1 0 A P Note 1. Explanation for the contents of the register bits: a) D = contents of I2C-bus data register bit is don’t care. b) A = standard I2C-bus acknowledge. c) Number = bit number being useful bit XRAM memory. d) P = standard I2C-bus STOP condition. Error processing If a read action is done without first initialising the memory address the acknowledge after the read command will not be generated by the chip. This should be treated as an error message: Table 7 S Write ACK ADDRH ACK ADDRL ACK S Read Correct read sequence S Read NEG ACK Incorrect read sequence; address is not initialized 1998 Mar 13 15 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... K ADDR L A C K A C K DATA H DATA M A C K DATA L A C P K auto increment if repeated n-groups of 3 (2) bytes address MBH529 R/W Philips Semiconductors ADDR H Dolby* Pro Logic Surround; Incredible Sound 1998 Mar 13 A C K A S 0 0 1 1 1 1 A0 0 C Fig.12 Master transmitter writes to chip. 16 A S 0 0 1 1 1 1 A0 0 C K ADDR H A C K ADDR L A A C S 0 0 1 1 1 1 A0 1 C K K DATA H A C K DATA M A C K DATA L A C P K auto increment if repeated n-groups of 3 (2) bytes address R/W R/W Product specification SAA7710T Fig.13 Master transmitter reads from chip. MBH528 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T When the level on the DSP_RESET pin is HIGH, the DSP program starts to run. DSP_RESET The DSP_RESET pin is active LOW and has an internal pull-up resistor. To enable a proper switch-on of the supply voltage a capacitor should be connected between this pin and VSS. The capacitor value is such that the chip is in a reset state as long as the power supply is not stabilized. When the level on the DSP_RESET pin is low, the SDA pin is asynchronously set to a high-impedance state. In the absence of a clock and during the power-up reset, the SDA line is high-impedance. The DSP_RESET has the following functions: TEST MODE CONNECTIONS (TSCAN, RTCB AND SHTCB • The bits of the input selector control register are set to logic 0 (see Table 4) PINS) The TSCAN, RTCB and SHTCB pins are used to put the chip in test mode and to test the internal connections. Each pin has an internal pull-down resistor to ground. In the application these pins can be left open-circuit or connected to ground. • The program counter is set to address 0000H • The I2C-bus interface is initialised; the SDA pin is guaranteed high-impedance. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD DC supply voltage −0.5 +6.5 V ∆VDD voltage difference between two VDDx pins − 550 mV Vi(max) maximum input voltage −0.5 VDD + 0.5 V lIK DC input clamp diode current Vi < −0.5 V or Vi > VDD + 0.5 V − 10 mA lOK DC output clamp diode current output type 4 mA Vo < −0.5 V or Vo > VDD + 0.5 V − 20 mA lO DC output source or sink current output type 4 mA −0.5 V < Vo < VDD + 0.5 V − 20 mA lDD DC output source or sink current output type 4 mA −0.5 V < Vo < VDD + 0.5 V − 20 mA lDD DC VDD supply current per pin − 50 mA lSS DC VSS supply current per pin − 50 mA VESD ESD sensitivity for all pins human body model 100 pF; 1500 Ω 3000 − V machine model all pins except pin OSC 200 pF; 2.5 µH; 0 Ω 300 − V 200 pF; 2.5 µH; 0 Ω 250 − V CIC spec/test method 100 − mA machine model pin OSC LTCH latch-up protection Ptot total power dissipation − 700 mW Tamb operating ambient temperature −40 +85 °C Tstg storage temperature −65 +150 °C THERMAL CHARACTERISTICS SYMBOL Rth j-a 1998 Mar 13 PARAMETER thermal resistance from junction to ambient in free air 17 VALUE UNIT 57 K/W Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T DC CHARACTERISTICS VDD1 = VDD2 = VDD3 = VDD_XTAL = 4.5 to 5.5 V; Tamb = −40 to +85 °C; note 1; unless otherwise specified. SYMBOL PARAMETER VDDtot total DC supply voltage IDD(tot) total DC supply current Ptot CONDITIONS MIN. TYP. MAX. UNIT 4.5 5 5.5 V DSP frequency = 18 MHz; maximum activity DSP − 50 55 mA total power dissipation DSP frequency = 18 MHz; maximum activity DSP − 250 300 mW VIH HIGH level input voltage all digital inputs and I/Os pin types I1, I2 and I3 0.7VDDX − − V pin type I4 0.8VDDX − − V VIL LOW level input voltage all digital inputs and I/Os pin types I1, I2 and I3 − − 0.3VDDX V pin type I4 − − 0.2VDDX V Vhys hysteresis voltage pin type I4 − 0.33VDDX − V VOH HIGH level output voltage digital outputs VDDX = 4.5 V; Io = −4 mA; pin type O1 and O2 4.0 − − V VOL LOW level output voltage digital outputs VDDX = 4.5 V; Io = 4 mA; pin types I3, O1 and O2 − − 0.5 V ILI input leakage current Vi = 0 or VDDX voltage; pin type I1 − − 1 µA ILO output leakage current 3-state outputs Vo = 0 or VDDX voltage; pin type I3 and O2 − − 5 µA Rpu(VDDX)(int) internal pull-up resistor to VDDX pin type I4 17 − 134 kΩ Rpd(VSSD)(int) internal pull-down resistor to VSSD pin type I2 17 − 134 kΩ 4.5 5 5.5 V Crystal oscillator VDDX positive supply voltage crystal oscillator Note 1. VDDX = VDD_XTAL. 1998 Mar 13 18 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T AC CHARACTERISTICS VDD1 = VDD2 = VDD3 = VDD_XTAL = 4.5 to 5.5 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fxtal crystal frequency − − 36.864 MHz αf spurious frequency attenuation current through crystal at input voltage swing 0.2 V 20 − − 500 − − dB µA transconductance at start-up 4 8 − mS voltage across crystal load capacitance note 1 − − 500 25 − − mV pF allowed loss resistor of crystal Cp = 5 pF; C1 = 10 pF; C2 = 10 pF − 20 60 Ω no divider; see Fig.4 see Fig.4 0.1 to 0.9VDD_XTAL; note 2 0.1 to 0.9VDD_XTAL; note 2 − 3.75 − − − − − − 18.432 − 20 20 MHz V ns ns 0.1 to 0.9VDD SDA, SCL − − 5.7 − − 100 ns kHz CL = 30 pF; 0.1 to 0.9VDD CL = 30 pF; 0.1 to 0.9VDD − − 112 112 0 0 25 7.3 8.3 − − − − − − − − − − − − ns ns ns ns ns ns ns 0 − − − 5 5 + 0.5 × CL(3) ns ns CL = 30 pF; 0.1 to 0.9VDD CL = 30 pF; 0.1 to 0.9VDD − − 7.3 8.3 − − ns ns Ixtal gm(XTAL) Vxtal CL(XTAL) Rxtal see Fig.3 Slave oscillator fslave SLVOLT tr tf slave frequency slave drive voltage input rise times input fall times Timing I2C-BUS INPUTS/OUTPUT tf fi(max) fall time I2C-bus maximum input frequency I2S-BUS INPUTS/OUTPUTS td2 ts2 rise time I2S-bus (O2) fall time I2S-bus (O2) CL pulse width HIGH CL pulse width LOW WS out delay time data in hold time data in set-up time td3 tacc data out delay time data out access time tr tf tHC tLC td1 ALL OTHER OUTPUTS tr tf (O1) rise time fall time ALL OTHER INPUTS tr input rise times VDD = 5.5 V − 6 200 ns tf input fall times VDD = 5.5 V − 6 200 ns Notes 1. The load capacitance is the sum of the series connection of C1 and C2 (see Fig.3) and the parasitic parallel capacitor of the crystal Cp. 2. With a 50%, ±5% duty cycle on oscillator drive input (see Fig.4). 3. The value for the capitative load CL is given in pF. 1998 Mar 13 19 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T INTERNAL CIRCUITRY PIN SYMBOL PIN TYPE 7 DSP_IN1 I1 8 DSP_IN2 I1 16 SCL I1 22 I2S_BCKIN1 I1 23 I2S_WSIN1 I1 24 I2S_DATAIN1 I1 25 I2S_DATAIN2 I1 26 I2S_WSIN2 I1 27 I2S_BCKIN2 I1 17 DSP_RESET I4 DC VOLTAGE (V) INTERNAL CIRCUIT 7, 8, 16, 22, 23, 24, 25, 26, 27 MGE758 17 + MGE759 3 RTCB I2 4 SHTCB I2 13 TSCAN I2 14 A0 I1 3, 4, 13, 14 MGE760 1 I2S_WSOUT O2 2 I2S_BCKOUT O2 9 DSP_OUT1 O2 30 I2S_DATAOUT3 O2 1, 2, 9, 30 MGE761 1998 Mar 13 20 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound PIN 15 SYMBOL SDA PIN TYPE SAA7710T DC VOLTAGE (V) INTERNAL CIRCUIT I3 15 MGE762 10 DSP_OUT2 O1 28 I2S_DATAOUT1 O1 29 I2S_DATAOUT2 O1 10, 28, 29 MGE763 5 VDD1 tbf 6 VSS1 0 11 VSS2 0 12 VDD2 5 31 VSS3 0 32 VDD3 5 21 OSC tbf 20 XTAL tbf 19 VDD_XTAL 5 18 VSS_XTAL 0 19 20 21 18 MGE764 1998 Mar 13 21 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 220 Ω 220 Ω I2S_WSIN1 23 1 I2S_WSOUT I2S_BCKIN2 I2S input 2 I2S INPUT SWITCH CIRCUIT 27 data 1 I2S_WSIN2 26 DSP_RESET C DOLBY PRO LOGIC OR DOLBY 3 STEREO OR HALL/MATRIX OR INCREDIBLE SOUND 220 Ω 220 pF I2S outputs I2S OUT 1 L 220 pF 220 Ω 220 pF SURROUND CHANNEL DELAY LINE 220 Ω I2S_DATAIN2 25 220 Ω 220 Ω SAA7710T 220 pF 220 Ω 220 Ω S 220 Ω I2S_DATAIN1 24 220 pF 220 Ω 220 Ω 220 pF 220 pF 220 Ω 220 Ω R SW 28 I2S_DATAOUT1 220 Ω 220 pF 5-BAND PARAMETRIC EQUALIZER OR TONE CONTROL VARIABLE OUTPUT MATRIX I2S OUT 2 29 I2S_DATAOUT2 220 Ω 22 RTCB 220 Ω 220 pF I2S OUT 3 30 I2S_DATAOUT3 220 Ω 220 Ω 220 pF 5 VDD1 17 100 nF 470 pF TSCAN 220 Ω Philips Semiconductors I2S input 1 2 I2S_BCKOUT Dolby* Pro Logic Surround; Incredible Sound I2S_BCKIN1 22 220 pF APPLICATION INFORMATION 220 Ω handbook, full pagewidth 1998 Mar 13 220 Ω AUTO BALANCE FUNCTION 13 TEST 3 BLM32A07 +5 V 12 VDD2 + 100 nF + 32 VDD3 100 µF (6.3 V) 100 nF BLM32A07 +5 V 19 VDD_XTAL I2C BUS TRANSCEIVER FLAG TEST CONTROL 100 nF OSCILLATOR 100 µF (6.3 V) 18 VSS_XTAL 6 VSS1 11 VSS2 31 VSS3 8 7 9 15 10 16 SDA DSP_IN1 DSP_OUT1 DSP_IN2 DSP_OUT2 220 Ω SCL 10 220 kΩ Ω 14 21 20 4 A0 OSC XTAL SHTCB 10 kΩ 10 pF 10 pF 1 nF MGE757 Fig.14 Application diagram. Product specification 100 pF SAA7710T 100 pF 4.7 µH 100 kΩ +5 V +5 V Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.2 1.0 0.25 0.25 0.1 0.95 0.55 inches 0.10 0.012 0.096 0.004 0.086 0.01 0.02 0.01 0.011 0.007 0.81 0.80 0.30 0.29 0.050 0.419 0.394 0.055 0.043 0.016 0.047 0.039 0.01 0.01 0.004 0.037 0.022 θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-01-25 97-05-22 SOT287-1 1998 Mar 13 EUROPEAN PROJECTION 23 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all SO packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SO packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1998 Mar 13 24 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Mar 13 25 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T NOTES 1998 Mar 13 26 Philips Semiconductors Product specification Dolby* Pro Logic Surround; Incredible Sound SAA7710T NOTES 1998 Mar 13 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA57 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545102/1200/04/pp28 Date of release: 1998 Mar 13 Document order number: 9397 750 03268