CS4354 5 V Stereo DAC with 2 VRMS Ground-centered Output Features Description Advanced Multi-bit Delta-Sigma Modulator The CS4354 is a complete stereo digital-to-analog system including digital interpolation, third-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 VRMS line-level driver from a 5 V supply. 101 dB A-wt Dynamic Range -86 dB THD+N Single-ended Ground Centered Analog Architecture – No DC-blocking Capacitors Required – Integrated Inverting Charge Pump – Filtered Line-level Outputs – 2 VRMS Full-scale Output Low-latency Digital Filtering Supports Sample Rates up to 192 kHz 24-bit I²S Input +5 V Analog Supply with Integrated Inverting Charge Pump and Regulator for Core Logic, and +1.8 V to +5 V Interface Power Supplies 50 mW Power Consumption 14-pin SOIC, Lead-free Assembly The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The CS4354 is available in a 14-pin SOIC package in Commercial (-40°C to +85°C) grade. The CDB4354 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 23 for complete details. These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, Blu-Ray Disc® and DVD players, set-top boxes, digital TVs, and DAB/DMB devices. Interface Supply (VL) +1.8V to +5V Analog Supply (VA) +5 V 1.8V reg Inverting Charge Pump Power-On Reset I²S Serial Audio Input Level Shifter -VA Ground-Centered, 2 Vrms Line Level Outputs Left Channel PCM Serial Audio Port Interpolation Filters + HPF Multibit Modulator DAC Right Channel Auto Speed Mode Detect Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) JULY '10 DS895A2 CS4354 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ........................................................................................................................... 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 RECOMMENDED OPERATING CONDITIONS .................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5 DAC ANALOG CHARACTERISTICS .................................................................................................... 6 COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS ................................... 7 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ......................................................... 8 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 10 INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11 2.1 Digital I/O Pin Characteristics ........................................................................................................ 11 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12 4. APPLICATIONS ................................................................................................................................... 13 4.1 Ground-Centered Line Outputs ...................................................................................................... 13 4.2 Sample Rate Range/Operational Mode Detect .............................................................................. 13 4.3 System Clocking ............................................................................................................................ 13 4.4 Serial Clock .................................................................................................................................... 14 4.4.1 External Serial Clock Mode ................................................................................................... 14 4.4.2 Internal Serial Clock Mode .................................................................................................... 14 4.4.2.1 De-Emphasis Control ................................................................................................. 14 4.5 Internal High-Pass Filter ................................................................................................................ 15 4.6 Digital Interface Format .................................................................................................................. 15 4.7 Internal Power-On Reset ............................................................................................................... 15 4.8 Initialization .................................................................................................................................... 16 4.9 Recommended Power-Up and Power-Down Sequences .............................................................. 18 4.9.1 Power-Up Sequence ............................................................................................................. 18 4.9.2 Power-Down Sequence ......................................................................................................... 18 4.10 Grounding and Power Supply Arrangements .............................................................................. 18 4.10.1 Capacitor Placement ........................................................................................................... 18 5. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS .............................. 19 6. PARAMETER DEFINITIONS ................................................................................................................ 21 7. PACKAGE INFORMATION .................................................................................................................. 22 7.1 Dimensions .................................................................................................................................... 22 7.2 Thermal Characteristics ................................................................................................................. 22 8. ORDERING INFORMATION ................................................................................................................ 23 9. REVISION HISTORY ............................................................................................................................ 24 LIST OF FIGURES Figure 1. External Serial Clock Mode Input Timing ..................................................................................... 9 Figure 2. Internal Serial Clock Mode Input Timing ...................................................................................... 9 Figure 3. Internal Serial Clock Generation .................................................................................................. 9 Figure 4. Power-On Reset Threshold Sequence ...................................................................................... 10 Figure 5. Typical Connection Diagram ...................................................................................................... 12 Figure 6. CS4354 Data Format (I²S) ......................................................................................................... 14 Figure 7. De-Emphasis Curve, Fs = 44.1 kHz .......................................................................................... 15 Figure 8. Internal Power-On Reset Circuit ................................................................................................ 15 Figure 9. Initialization and Power-Down Sequence Diagram .................................................................... 17 Figure 10. Single-Speed Stopband Rejection ........................................................................................... 19 Figure 11. Single-Speed Transition Band ................................................................................................. 19 Figure 12. Single-Speed Transition Band (detail) ..................................................................................... 19 Figure 13. Single-Speed Passband Ripple ............................................................................................... 19 Figure 14. Double-Speed Stopband Rejection .......................................................................................... 19 2 DS895A2 CS4354 Figure 15. Double-Speed Transition Band ................................................................................................ 19 Figure 16. Double-Speed Transition Band (detail) .................................................................................... 20 Figure 17. Double-Speed Passband Ripple .............................................................................................. 20 Figure 18. Quad-Speed Stopband Rejection ............................................................................................ 20 Figure 19. Quad-Speed Transition Band .................................................................................................. 20 Figure 20. Quad-Speed Transition Band (detail) ...................................................................................... 20 Figure 21. Quad-Speed Passband Ripple ................................................................................................ 20 LIST OF TABLES Table 1. Power-On Reset Threshold Voltages .......................................................................................... 10 Table 2. Digital I/O Pin Characteristics ..................................................................................................... 11 Table 3. CS4354 Operational Mode Auto-Detect ...................................................................................... 13 Table 4. Common MCLK and LRCK Frequencies .................................................................................... 13 Table 5. Internal SCLK Frequencies ......................................................................................................... 14 DS895A2 3 CS4354 1. PIN DESCRIPTIONS Pin Name Pin # VL 1 14 -VFILT SDIN 2 13 FLYN MCLK 3 12 FLYP LRCK 4 11 VA SCLK/DEM 5 10 GND GND 6 9 AOUTB FILT+ 7 8 AOUTA Pin Description VL 1 Serial Audio Interface Power (Input) - Positive power for the serial audio interface. SDIN 2 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. LRCK 4 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. SCLK/DEM 5 Serial Clock (Input) - Serial clock for the serial audio interface. FILT+ 7 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. AOUTA AOUTB 8 9 Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteristics table. GND 6, 10 Ground (Input) - Ground reference. See Section 4.10 on page 18 for layout considerations. VA 11 Analog, Charge Pump, and Regulator Power (Input) - Positive power supply for the analog, inverting charge pump, and regulator for the digital core logic sections. FLYP FLYN 12 13 Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump’s flying capacitor. -VFILT 14 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers. 4 DS895A2 CS4354 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground.(Note 1) Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Analog power Interface power -CSZ Symbol Min Typ Max Units VA VL TA 4.75 1.4 -40 5.0 1.8, 3.3, 5.0 - 5.25 5.25 +85 V V °C Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Low Voltage Analog Power Interface Power Input Current, Any Pin Except Supplies Digital Input Voltage (Note 2) Ambient Operating Temperature (Power Applied) Storage Temperature Digital Interface Symbol Min Max Units VA VL Iin VIN-L TA Tstg -0.3 -0.3 -0.3 -55 -65 6.0 6.0 ±10 VL+ 0.4 +125 +150 V V mA V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin. DS895A2 5 CS4354 DAC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): TA = 25 °C; VA = 5 V, VL = 3.3 V; GND = 0 V; FILT+, -VFILT, and FLYP/N capacitors as shown in Figure 5 on page 12; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 20 Hz to 20 kHz. Parameter Symbol Min Typ Max Unit 95 92 - 101 98 96 93 - dB dB dB dB - -86 -78 -38 -86 -73 -33 -80 -72 -32 - dB dB dB dB dB dB Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 3, 5) Dynamic Range 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted Total Harmonic Distortion + Noise 24-bit 16-bit Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (A-wt) - 101 - dB (1 kHz) - 100 - dB 0.38•VA 0.40•VA 0.42•VA VRMS 1.07•VA 1.13•VA 1.19•VA Vpp - 0.1 - dB Analog Output (Note 4) Full Scale AOUTx Output Voltage (Notes 6, 7) Interchannel Gain Mismatch Output Offset - ±1 ±8 mV Gain Drift - 100 - ppm/°C ZOUT - 100 - Load Resistance RL 3 - - k Load Capacitance CL - - 100 pF Output Impedance Notes: 3. Measured at the output of the external low-pass filter on AOUTx as shown in Figure 5 on page 12. 4. Measured between the AOUTx and GND pins. 5. One LSB of triangular PDF dither is added to data. 6. Does not include attenuation due to ZOUT. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. 7. VPP is the controlling specification. VRMS specification valid for sine wave signals only. V pp Note that for sine wave signals: V RMS = ----------- 2 2 6 DS895A2 CS4354 COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Reference level (0 dB) is set at 997 Hz. (Note 11) Parameter Single-Speed Mode - 48 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation (Note 9) High Pass Filter Settling Time (input signal goes to 95% of its final value) Total Group Delay De-emphasis Error (Note 10)(Relative to 1 kHz) Fs = 44.1 kHz Min Typ Max Unit 1.796•10-4 1.947•10-5 -0.05 0.550 80 dB - 2.452•104/Fs 9.4/Fs - 0.470 0.500 +0.05 ±0.14 Fs Fs dB Fs dB s s dB 8.980•10-5 9.736•10-6 -0.05 0.583 82 dB - 4.903•104/Fs 7.0/Fs 0.290 0.500 +0.05 - Fs Fs dB Fs dB s s 4.490•10-5 4.868•10-6 -0.05 0.630 85 dB - 9.807•104/Fs 4.9/Fs 0.253 0.486 +0.05 - Fs Fs dB Fs dB s s Double-Speed Mode - 96 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation (Note 9) High Pass Filter Settling Time (input signal goes to 95% of its final value) Total Group Delay Quad-Speed Mode - 192 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation (Note 9) High Pass Filter Settling Time (input signal goes to 95% of its final value) Total Group Delay Notes: 8. Response is clock-dependent and will scale with Fs. 9. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 10. De-emphasis is available only in Single-Speed Mode. 11. Amplitude vs. frequency plots of this data are available in “Combined Digital and On-chip Analog Filter Response Plots” on page 19. DS895A2 7 CS4354 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters Symbol MCLK Frequency MCLK Duty Cycle Input Sample Rate (Note 12) All MCLK/LRCK ratios combined (SSM) 256x, 384x, 512x, 768x, 1024x (DSM) 128x, 192x, 256x, 384x, 512x (QSM) 128x, 192x, 256x Fs Min Typ Max Units 7.6 - 55.3 MHz 45 - 55 % 30 30 84 170 - 216 54 108 216 kHz kHz kHz kHz 45 - 55 % 20 - - ns External SCLK Mode LRCK Duty Cycle SCLK Pulse Width Low tsclkl SCLK Pulse Width High tsclkh SCLK Duty Cycle 20 - - ns 45 - 55 % SCLK rising to LRCK edge delay tslrd 20 - - ns LRCK edge to SCLK rising delay tslrs 20 - - ns SDIN valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDIN hold time tsdh 20 - - ns 1 50% – ---------------------------2 MCLK - 1 50% + ---------------------------2 MCLK - tsclkw 10 9 ---------------SCLK - - ns MCLK falling to LRCK edge tmclkf - LRCK edge to SCLK rising tsclkr – 10 9 --------------------------4 MCLK - SDIN valid to SCLK rising setup time tsdlrs Internal SCLK Mode LRCK Duty Cycle SCLK Period (Note 13) SCLK rising to SDIN hold time MCLK / LRCK = 1024, 512, 256, 128 tsdh MCLK / LRCK = 768, 384, 192 10 9 --------------------------4 MCLK ns (Note 14) - ns 10 9 ----------------------- + 10 512 Fs - - ns 10 9 ----------------------- + 15 512 Fs - - 10 9 ----------------------- + 15 384 Fs - ns - 12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample Rate Range/Operational Mode Detect” on page 13 for supported ratios and frequencies. SSM = Single-Speed Mode, DSM = Double-Speed Mode, QSM = Quad-Speed Mode. 13. SCLK period is defined by the SCLK / LRCK ratio. The SCLK / LRCK ratio may be either 32, 48, or 64. See Table 5 on page 14. 9 t sclkw 10 14. t sclkr = ----------------+ --------------------------- + t mclkf 2 2 MCLK 8 DS895A2 CS4354 LRCK t sclkh t slrs t slrd t sclkl SCLK t sdh t sdlrs SDIN Figure 1. External Serial Clock Mode Input Timing MCLK t mclkf LRCK t sclkr SDIN t sdlrs t sdh * INTERNAL SCLK t sclkw The SCLK pulses shown are internal to the CS4354. Figure 2. Internal Serial Clock Mode Input Timing LRCK MCLK 1 N 2 N *INTERNAL SCLK SDIN * The SCLK pulses shown are internal to the CS4354. N equals MCLK divided by SCLK Figure 3. Internal Serial Clock Generation DS895A2 9 CS4354 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground. Parameters 1.8 V <VL 5.0 V 1.8 V <VL 5.0 V High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Symbol Min Typ Max Units VIH VIL Iin 0.7xVL - 8 0.3xVL ±10 - V V A pF INTERNAL POWER-ON RESET THRESHOLD VOLTAGES Test conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground. Symbol Min Typ Max Units Internal Reset Asserted at Power-On Parameters Von1 - 0.2 - V Internal Reset Released at Power-On Von2 - 3.6 - V Internal Reset Asserted at Power-Off Voff - 3.1 - V Table 1. Power-On Reset Threshold Voltages VA Voff Von2 Von1 GND reset (internal) HI LO reset No Power undefined reset active DAC Ready reset active Figure 4. Power-On Reset Threshold Sequence 10 DS895A2 CS4354 DC ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise specified): VA = 5 V, VL = 3.3 V; GND = 0 V; SDIN = 0; all voltages with respect to ground. Parameters Symbol Min Typ Max Units IVA IVL IVA IVL - 10 0.1 0.5 1 50 2.5 60 60 13 0.2 65 - mA mA mA A mW mW dB dB - 3.5 4.9 4.7 - V V V Power Supplies Power Supply Current (Note 15) Normal Operation (Note 16) Power-Down (Note 17) Power Dissipation (All Supplies) Normal Operation (Note 16) (Note 15) Power-Down (Note 17) Power Supply Rejection Ratio (Note 18) (1 kHz) (60 Hz) PSRR DC Output Voltages Pin Voltage FILT+ to GND FLYP to FLYN GND to -VFILT Notes: 15. Power supply current increases with increasing sample rate and increasing MCLK frequency. Typical values are based on Fs = 48 kHz and MCLK = 12.288 MHz. Maximum values are based on highest sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface. Variance between speed modes is small. 16. During normal operation, SDIN = 997 Hz sine wave at 0 dBFS with load resistance RL = 3 k. 17. Power-down is defined as all clock and data lines held static low. All digital inputs have a weak pulldown (approximately 50 k) which is only present during power on reset. Opposing this pull-down will increase the power-down current. 18. Valid with the recommended capacitor values as shown in the typical connection diagram in Section 5. 2.1 Digital I/O Pin Characteristics Input and output levels and associated power supply voltage are shown in Table 2. Logic levels should not exceed the corresponding power supply voltage. Pin Name MCLK LRCK SCLK SDIN Power Supply VL VL VL VL I/O Input Input Input Input Driver - Receiver 1.8 V - 5 V 1.8 V - 5 V 1.8 V - 5 V 1.8 V - 5 V Table 2. Digital I/O Pin Characteristics DS895A2 11 CS4354 3. TYPICAL CONNECTION DIAGRAM +5 V 2.2 µF + 0.1 µF VA 11 FILT+ 7 + 2.2 µF CS4354 Digital Audio Processor +1.8 V to +5 V 3 MCLK 5 SCLK/DEM 4 LRCK 2 SDIN 1 Line Level Out Left & Right AOUTA 470 8 2.2 nF Rext Rext 2.2 nF AOUTB 9 FLYP 12 470 Note 1 VL 10 FLYN 13 -VFILT 14 G ND G ND 0.1 µF + + 2.2 µF Note 1: Capacitors must be C0G or equivalent. 2.2 µF 6 Figure 5. Typical Connection Diagram 12 DS895A2 CS4354 4. APPLICATIONS 4.1 Ground-Centered Line Outputs An on-chip charge pump creates a negative supply which allows the full-scale output swing to be centered around ground. This eliminates the need for large DC-blocking capacitors which create audible pops at power-on and provides improved low frequency response. See the DAC Analog Characteristics table for the complete specifications of the full-scale output voltage. It should be noted that external output impedance between the AOUTx pin and the load will lower the voltage delivered to the load. 4.2 Sample Rate Range/Operational Mode Detect The CS4354 operates in one of three operational modes. The device will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 3. Sample rates outside the specified range for each mode are not supported. In addition to a valid LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device for speed mode auto-detection; see Figure 9. Input Sample Rate (Fs) Mode 30 kHz - 54 kHz 84 kHz - 108 kHz 170 kHz - 216 kHz Single-Speed Mode Double-Speed Mode Quad-Speed Mode Table 3. CS4354 Operational Mode Auto-Detect 4.3 System Clocking The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Table 4 on page 13. Refer to Section 4.6 for the required SCLK timing associated with the selected Digital Interface Format and to “Switching Specifications - Serial Audio Interface” on page 8 for the maximum allowed clock frequencies. LRCK (kHz) 32 44.1 48 88.2 96 176.4 192 Mode 128x 11.2896 12.2880 22.5792 24.5760 192x 16.9344 18.4320 33.8688 36.8640 QSM 256x 8.1920 11.2896 12.2880 22.5792 24.5760 45.1584 49.1520 MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 33.8688 45.1584 36.8640 49.1520 DSM 768x 24.5760 33.8688 36.8640 - 1024x 32.7680 45.1580 49.1520 SSM Table 4. Common MCLK and LRCK Frequencies DS895A2 13 CS4354 4.4 Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4354 supports both external and internal serial clock generation modes. Refer to Figure 6 for a diagram of the I²S data format. Left C ha nnel LR C K R ig ht C ha n nel SCLK SDIN MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 6. CS4354 Data Format (I²S) In order to support selectable de-emphasis without a dedicated pin, pin 5 (SCLK/DEM) functions both as a serial clock input and a de-emphasis select. In typical applications where de-emphasis is not required, the SCLK/DEM pin is the input for an external serial clock - this is known as the External Serial Clock Mode. To enable de-emphasis selection, the Internal Serial Clock Mode has to be used. Sections 4.4.1 and 4.4.2 describe this feature in detail. 4.4.1 External Serial Clock Mode The CS4354 will enter the External Serial Clock Mode when 16 low to high transitions are detected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock Mode and de-emphasis filter are disabled (see Figure 9 for flow diagram). In the External Serial Clock Mode, the CS4354 will support I²S data up to 24-bit, with data valid on the rising edge of SCLK. 4.4.2 Internal Serial Clock Mode The CS4354 will switch to Internal Serial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames of LRCK (see Figure 9 for flow diagram). In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending on the speed mode and MCLK frequency. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Table 5 for details (all frequencies listed as multiples of LRCK frequency). Speed Mode SSM DSM QSM MCLK = 128x - 192x 48x 32x 256x 64x 32x 384x 48x - 512x 64x - 768x 64x - 1024x 64x - Table 5. Internal SCLK Frequencies 4.4.2.1 De-Emphasis Control The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs. The de-emphasis error will increase for sample rates other than 44.1 kHz. When the SCLK/DEM pin is connected to VL (internal SCLK mode), the 44.1 kHz de-emphasis filter is activated. When the SCLK/DEM pin is connected to GND, the de-emphasis filter is disabled. For more information see “Internal Serial Clock Mode” on page 14. 14 DS895A2 CS4354 De-emphasis selection is disabled in the external SCLK mode. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 7. De-Emphasis Curve, Fs = 44.1 kHz Note: 4.5 De-emphasis is only available in Single-Speed Mode. Internal High-Pass Filter The CS4354 includes an internal digital high-pass filter. This filter prevents a constant digital offset from creating a DC voltage on the analog output pins. The filter’s corner frequency is well below the audio band; see “Switching Specifications - Serial Audio Interface” on page 8 for filter specifications. 4.6 Digital Interface Format The device accepts audio samples in the industry standard I²S format only. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figure 6 on page 14. SDIN is valid on the rising edge of SCLK. For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com. 4.7 Internal Power-On Reset The CS4354 features an internal power-on reset (POR) circuit. This circuit monitors the VA supply and automatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches defined thresholds (see “Internal Power-On Reset Threshold Voltages” on page 10). No external clocks are required for the POR circuit to function. VA GND Power-On Reset Circuit reset (internal) Figure 8. Internal Power-On Reset Circuit When power is first applied, the POR circuit monitors the VA supply voltage to determine when it reaches a defined threshold, Von1. At this time, the POR circuit asserts the internal reset low, resetting all of the DS895A2 15 CS4354 digital circuitry. Once the VA supply reaches the secondary threshold, Von2, the POR circuit releases the internal reset. When power is removed and the VA voltage reaches a defined threshold, Voff, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. Note: 4.8 For correct operation of the internal POR circuit, the voltage on VL must rise before or simultaneously with VA. Initialization When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization sequence. In this state, the AOUTx pins are weakly pulled to ground and FILT+ is connected to GND. The device will remain in the reset state until VON2 is reached. Once VON2 is reached, the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charges the capacitors for the negative voltage supply. Once LRCK is valid, the number of MCLK cycles is counted relative to the LRCK period to determine the MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpolation filters and delta-sigma modulators are turned on, the internal voltage reference, FILT+, powers up to normal operation, the analog output pull-down resistors are removed, and power is applied to the output amplifiers. If a valid SCLK is applied, the device will clock in data according to the applied SCLK. If no SCLK is present, the device will clock in data using the derived internal SCLK (see Figure 3 on page 9) and will apply the deemphasis filter according to Section 4.4.2.1 on page 14. After this power-up state sequence is complete, normal operation begins and analog output is generated. If valid MCLK, LRCK, and SCLK are applied to the DAC before VON2 is reached, the total time from VON2 to the analog audio output from AOUTx is less than 50 ms. See Figure 9 for a diagram of the device’s states and transition conditions. 16 DS895A2 CS4354 U S E R: A pply P ow er P ow er-O n R eset S tate U S ER : R em ove M C LK P ow er-D ow n State U S ER : A pply M C LK Initialization S tate U S ER : Apply LR C K M C LK/LR C K R atio D etection U S E R : C hange M C LK /LR C K ratio V alid M C LK/LR C K R atio P ow er-U p S tate O utputs M uted U S E R: N o SC LK U S E R : A pplied S C LK S C LK m ode = internal SC LK m ode = external N orm al O peration D e-em phasis Is S electable N orm al O peration D e-em phasis Is D isabled A nalog O utput is G enerated V alid M C LK/LR C K R atio U S E R : C hange M C LK /LR C K ratio M ute State Figure 9. Initialization and Power-Down Sequence Diagram DS895A2 17 CS4354 4.9 4.9.1 Recommended Power-Up and Power-Down Sequences Power-Up Sequence Follow the power-up sequence below: 1. Apply power. 2. After the power supplies are stable, provide the correct MCLK, LRCK, and SCLK (only in External Serial Clock Mode) signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure 9. Please refer to Section 4.4 on page 14 for common clock frequencies in the External Serial Clock Mode, and supported modes in the Internal Serial Clock Mode. The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid clocks are applied. 4.9.2 Power-Down Sequence Follow the power-down sequence below: 1. For minimal pops, set the input digital data (SDIN) to zero for at least 8192 consecutive samples. 2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin. 3. Remove the power supply voltages. Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page 8. 4.10 Grounding and Power Supply Arrangements As with any high-resolution converter, the CS4354 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. The “Typical Connection Diagram” on page 12 shows the recommended power arrangements with VA and VL connected to clean supplies. It is strongly recommended that a single ground plane be used with the GND pins connected to the common plane; this is important because both pin 6 and pin 10 provide analog ground reference to the CS4354. Should it be necessary to split the ground planes, the CS4354 should be placed entirely in the analog plane. In this configuration, it is critical that the digital and analog ground planes be tied together with a low-impedance connection, ideally a strip of copper on the printed circuit board, at a single point near the CS4354. All signals, especially clocks, should be kept away from the FILT+ pin in order to avoid unwanted coupling into the DAC. 4.10.1 Capacitor Placement Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same PCB layer as the device. See DC Electrical Characteristics for the voltage present across pin pairs. This is useful for choosing appropriate capacitor voltage ratings and orientation if electrolytic capacitors are used. The CDB4354 evaluation board demonstrates the optimum layout and power supply arrangements. 18 DS895A2 CS4354 5. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS Single−Speed Transition Band 0 0 −20 −20 −40 −40 Amplitude(dB) Amplitude(dB) Single−Speed Stopband Rejection −60 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 −120 0.4 1 Figure 10. Single-Speed Stopband Rejection 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 11. Single-Speed Transition Band Single−Speed Passband Ripple Single−Speed Transition Band Detail 0.06 0 −1 0.04 −2 −3 Amplitude(dB) Amplitude(dB) 0.02 −4 −5 0 −6 −0.02 −7 −8 −0.04 −9 −10 0.45 −0.06 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0 Figure 12. Single-Speed Transition Band (detail) 0.05 0.1 0.15 −20 −20 −40 −40 Amplitude(dB) Amplitude(dB) 0 −60 −80 −100 −100 0.7 0.8 Frequency(normalized to Fs) 0.9 Figure 14. Double-Speed Stopband Rejection DS895A2 0.45 0.5 −60 −80 0.6 0.4 Double−Speed Transition Band 0 0.5 0.35 Figure 13. Single-Speed Passband Ripple Double−Speed Stopband Rejection −120 0.4 0.2 0.25 0.3 Frequency(normalized to Fs) 1 −120 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 15. Double-Speed Transition Band 19 CS4354 Double−Speed Passband Ripple Double−Speed Transition Band Detail 0.2 0 −1 0.15 −2 0.1 −3 Amplitude(dB) Amplitude(dB) 0.05 −4 −5 −6 0 −0.05 −7 −0.1 −8 −0.15 −9 −10 0.45 −0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0 Figure 16. Double-Speed Transition Band (detail) 0.05 0.1 0.15 Frequency(normalized to Fs) Quad−Speed Transition Band 0 −20 −20 −40 −40 Amplitude(dB) Amplitude(dB) 0 −60 −60 −80 −80 −100 −100 0.3 0.4 0.25 Figure 17. Double-Speed Passband Ripple Quad−Speed Stopband Rejection −120 0.2 0.2 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 −120 0.2 1 Figure 18. Quad-Speed Stopband Rejection 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 19. Quad-Speed Transition Band Quad−Speed Transition Band Detail Quad−Speed Passband Ripple 0 0.2 −1 0.15 −2 0.1 0.05 −4 Amplitude(dB) Amplitude(dB) −3 −5 −6 0 −0.05 −7 −0.1 −8 −0.15 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 Figure 20. Quad-Speed Transition Band (detail) 20 0.55 −0.2 0 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.35 0.4 Figure 21. Quad-Speed Passband Ripple DS895A2 CS4354 6. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS895A2 21 CS4354 7. PACKAGE INFORMATION 7.1 Dimensions 14L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE A L e DIM A A1 b C D E e H L MIN 0.0590 0.0040 0.0138 0.0075 0.3380 0.1520 0.2300 0.0160 0° A1 INCHES NOM 0.050 BSC - MAX 0.0708 0.0098 0.0200 0.0098 0.3440 0.1574 0.2440 0.0350 8° MILLIMETERS NOM 1.270 BSC - MIN 1.397 0.102 0.351 0.190 8.585 3.861 5.842 0.406 0° MAX 1.549 0.249 0.508 0.250 8.738 3.998 6.198 0.889 8° JEDEC #: MS-012 Controling Dimension is Millimeters 7.2 Thermal Characteristics Parameter Junction to Ambient Thermal Impedance 22 2 Layer Board 4 Layer Board Symbol Min Typ Max Units JA - 110 86 - °C/Watt DS895A2 CS4354 8. ORDERING INFORMATION Product Description Package 5 V Stereo Audio DAC 14-pin CS4354 with 2 VRMS Line Output SOIC CDB4354 CS4354 Evaluation Board DS895A2 Pb-Free Grade Temp Range YES Commercial -40° to +85° C - - - Container Rail Tape & Reel - Order # CS4354-CSZ CS4354-CSZR CDB4354 23 CS4354 9. REVISION HISTORY Release A1 (Sept ‘09) Changes – – – – – – – – – – – – – A2 (July ‘10) – – – – – – – – – – 24 Initial release. Updated THD+N specification in DAC Analog Characteristics. Updated dynamic range specification in DAC Analog Characteristics. Updated idle channel noise/SNR specification in DAC Analog Characteristics. Updated front page dynamic range and THD+N performance to match updated specifications. Updated frequency response specification description in Combined Digital and On-Chip Analog Filter Characteristics so that frequency response limits are measured relative to 1 kHz. Updated Power On Reset threshold values in Internal Power-On Reset Threshold Voltages. Removed typical specification for LRCK and SCLK in Switching Specifications - Serial Audio Interface. Updated power supply current specifications in DC Electrical Characteristics. Updated pin voltage specification in DC Electrical Characteristics. Corrected MCLK frequency in Table 4 from 33.8680 MHz to 33.8688 MHz. Updated test condition bandwidth in DAC Analog Characteristics from 10 Hz - 20kHz to 20 Hz - 20kHz Removed MCLK = 1152x LRCK mode support (per Rev B0 silicon). Updated specifications (LRCK min and corresponding MCLK min) in Switching Specifications - Serial Audio Interface, and applications information in Table 4 and Table 5. Added (Note 16) to DC Electrical Characteristics. Updated FILT+ description in Initialization. Updated interchannel isolation specification in DAC Analog Characteristics. Updated Table 3 to match specifications in Switching Specifications - Serial Audio Interface. Removed High Pass Filter Characteristics section; appended updated specifications to Combined Digital and On-Chip Analog Filter Characteristics. Updated passband and stopband specifications in Combined Digital and On-Chip Analog Filter Characteristics to reflect Rev B0 silicon. Updated title and plots in Combined Digital and On-chip Analog Filter Response Plots to reflect Rev B0 silicon. Updated typical output offset in DAC Analog Characteristics. Updated timing diagram Figure 2 to reflect internal SCLK generation as shown in Figure 3. Updated Typical Connection Diagram; VL capacitor now recommended by default. DS895A2 CS4354 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). 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