SSM4575M
COMPLEMENTARY N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Simple drive requirement
N-Ch
D2
BV
D2
Low on-resistance
D1
D1
Fast switching performance
SO-8
S1
G1
Description
G2
S2
60V
DSS
R DS(ON)
36mΩ
ID
6A
-60V
72mΩ
-4.2A
P-Ch BV DSS
RDS(ON)
ID
Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and costeffectiveness.
D2
D1
The SO-8 package is widely preferred for commercial and
industrial surface mount applications and is well suited for
low-voltage applications such as DC/DC converters.
G2
G1
S2
S1
Absolute Maximum Ratings
Symbol
Parameter
Rating
N-channel
Units
P-channel
VDS
Drain-Source Voltage
60
-60
V
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
±20
±20
V
Continuous Drain
Current3
6
-4.2
A
Continuous Drain
Current3
4.7
-3.3
A
30
-30
A
1
IDM
Pulsed Drain Current
PD @ TA=25°C
Total Power Dissipation
2.0
Linear Derating Factor
0.016
W
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-a
Rev.1.01 7/05/2004
Parameter
Thermal Resistance Junction-ambient
3
Max.
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Value
Unit
62.5
°C/W
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SSM4575M
N-channel Electrical Characteristics @ T j=25oC(unless otherwise specified)
Symbol
Parameter
Test Conditions
Typ.
Max. Units
60
-
-
V
BVDSS
Drain-Source Breakdown Voltage
∆ BVDSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C,ID=1mA
-
0.04
-
V/°C
RDS(ON)
Static Drain-Source On-Resistance 2
VGS=10V, ID=5A
-
-
36
mΩ
VGS=4.5V, ID=3A
-
-
42
mΩ
VDS=VGS, ID=250uA
1
-
3
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=10V, ID=5A
-
8
-
S
o
VDS=60V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=48V, VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS=±20V
-
-
±100
nA
ID=5A
-
18
29
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
Min.
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=48V
-
5
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
10
-
nC
2
td(on)
Turn-on Delay Time
VDS=30V
-
10
-
ns
tr
Rise Time
ID=1A
-
6
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω ,VGS=10V
-
32
-
ns
tf
Fall Time
RD=30Ω
-
10
-
ns
Ciss
Input Capacitance
VGS=0V
-
1670 2670
pF
Coss
Output Capacitance
VDS=25V
-
160
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
117
-
pF
Min.
Typ.
IS=1.7A, VGS=0V
-
-
1.2
V
Source-Drain Diode
Symbol
VSD
Parameter
Forward On Voltage
2
2
Test Conditions
Max. Units
trr
Reverse Recovery Time
IS=5A, VGS=0V
-
34
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
48
-
nC
Rev.1.01 7/05/2004
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2 of 7
SSM4575M
P-channel Electrical Characteristics @ T j=25oC(unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
-60
-
-
V
-
-0.04
-
V/°C
VGS=-10V, ID=-4A
-
-
72
mΩ
VGS=-4.5V, ID=-3A
-
-
88
mΩ
VDS=VGS, ID=-250uA
-1
-
-3
V
BVDSS
Drain-Source Breakdown Voltage
∆ BVDSS/∆Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C,ID=-1mA
RDS(ON)
2
Static Drain-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
IGSS
VGS=0V, ID=-250uA
Max. Units
VDS=-10V, ID=-4A
-
6
-
S
o
VDS=-60V, VGS=0V
-
-
-1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=-48V, VGS=0V
-
-
-25
uA
Gate-Source Leakage
VGS=±20V
-
-
±100
nA
Drain-Source Leakage Current (Tj=25 C)
2
Qg
Total Gate Charge
ID=-4A
-
21
34
nC
Qgs
Gate-Source Charge
VDS=-48V
-
5
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=-4.5V
-
9
-
nC
VDS=-30V
-
12
-
ns
-
6
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=-1A
td(off)
Turn-off Delay Time
RG=3.3Ω ,VGS=-10V
-
82
tf
Fall Time
RD=30Ω
-
36
Ciss
Input Capacitance
VGS=0V
-
1780 2850
pF
Coss
Output Capacitance
VDS=-25V
-
157
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
130
-
pF
ns
-
ns
Source-Drain Diode
Symbol
VSD
Parameter
Test Conditions
Forward On Voltage2
2
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Min.
Typ.
IS=-1.7A, VGS=0V
-
-
Max. Units
-1.2
V
IS=-4A, VGS=0V
-
43
-
ns
dI/dt=-100A/µs
-
87
-
nC
Notes:
1.Pulse width limited by max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on min. copper pad.
Rev.1.01 7/05/2004
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3 of 7
SSM4575M
N-channel
50
60
T A = 25 o C
40
40
ID , Drain Current (A)
ID , Drain Current (A)
50
10V
7.0V
5.0V
4.5V
TA=150oC
10V
7.0V
5.0V
4.5V
30
20
30
20
V G =3.0V
V G =3.0V
10
10
0
0
0
1
2
3
4
5
6
7
0
V DS , Drain-to-Source Voltage (V)
2
3
4
5
6
7
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
38
1.8
ID=3A
36
I D =5A
V G =10V
1.6
o
Normalized RDS(ON)
T A =25 C
34
RDS(ON) (mΩ )
1
32
1.4
1.2
1.0
30
0.8
28
0.6
2
4
6
8
10
-50
0
50
100
150
T j , Junction Temperature ( o C)
V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
1.5
5
1.3
Normalized VGS(th) (V)
4
IS(A)
3
T j =150 o C
T j =25 o C
2
1.1
0.9
0.7
1
0.5
0.3
0
0
0.2
0.4
0.6
0.8
1
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Rev.1.01 7/05/2004
1.2
-50
0
50
T j ,Junction Temperature (
100
o
150
C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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SSM4575M
N-channel
f=1.0MHz
10000
I D =5A
V DS =48V
12
10
C iss
C (pF)
VGS , Gate to Source Voltage (V)
14
8
1000
6
4
2
C oss
C rss
0
100
0
5
10
15
20
25
30
35
1
5
9
Fig 7. Gate Charge Characteristics
17
21
25
29
Fig 8. Typical Capacitance Characteristics
100
Normalized Thermal Response (Rthja)
1
10
ID (A)
13
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
1ms
1
10ms
100ms
T A =25 o C
Single Pulse
0.1
1s
Duty factor=0.5
0.2
0.1
0.1
0.05
0.02
0.01
PDM
t
0.01
Single Pulse
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja =135o C/W
DC
0.01
0.001
0.1
1
10
100
1000
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
Rev.1.01 7/05/2004
Charge
Q
Fig 12. Gate Charge Waveform
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5 of 7
SSM4575M
P-channel
40
40
T A = 25 C
30
TA=150oC
35
-ID , Drain Current (A)
-ID , Drain Current (A)
-10V
-7.0V
-5.0V
-4.5V
o
35
25
20
15
V G =-3.0V
10
25
20
15
V G =-3.0V
10
5
5
0
0
0
1
2
3
4
5
6
0
7
-V DS , Drain-to-Source Voltage (V)
1
2
3
4
5
6
7
8
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
80
1.8
ID=-3A
ID=-4A
V G =-10V
1.6
T A =25°C
Normalized R DS(ON)
75
RDS(ON) (mΩ )
-10V
-7.0V
-5.0V
-4.5V
30
70
1.4
1.2
1.0
65
0.8
0.6
60
2
4
6
8
-50
10
0
50
100
150
o
-V GS ,Gate-to-Source Voltage (V)
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
4
1.6
1.3
T j =150 o C
2
Normalized -VGS(th) (V)
-IS(A)
3
T j =25 o C
1.1
0.8
1
0.6
0.3
0
0
0.2
0.4
0.6
0.8
1
-V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Rev.1.01 7/05/2004
1.2
-50
0
50
100
150
o
T j , Junction Temperature ( C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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6 of 7
SSM4575M
P-channel
f=1.0MHz
10000
I D =-4A
V DS =-48V
12
C (pF)
-VGS , Gate to Source Voltage (V)
16
8
C iss
1000
4
C oss
C rss
100
0
0.0
10.0
20.0
30.0
40.0
50.0
1
60.0
5
9
13
17
21
25
29
-V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100
Normalized Thermal Response (Rthja)
Duty factor=0.5
10
-ID (A)
1ms
1
10ms
100ms
0.1
o
T A =25 C
Single Pulse
1s
DC
0.2
0.1
0.1
0.05
0.02
0.01
PDM
0.01
t
Single Pulse
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=135oC/W
0.001
0.01
0.1
1
10
100
1000
0.0001
0.001
0.01
-V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
VDS
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
Charge
Q
Fig 12. Gate Charge Waveform
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.1.01 7/05/2004
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