SSM4502GM N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY N-CH BVDSS D2 D2 Simple Drive Requirement Low Gate Charge Fast Switching Performance 20V RDS(ON) D1 D1 18mΩ ID SO-8 S1 S2 G1 8.3A P-CH BVDSS G2 -20V RDS(ON) DESCRIPTION 45mΩ ID -5A The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is widly preferred for commercial-industrial surface mount applications and suited for low voltage applications such as DC/DC converters. Pb-free; RoHS-compliant D2 D1 G2 G1 S2 S1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating N-channel VDS Drain-Source Voltage VGS Gate-Source Voltage ID@TA=25℃ ID@TA=70℃ Units P-channel 20 -20 V ±12 ±12 V 3 8.3 -5 A 3 6.5 -4 A 30 -20 A Continuous Drain Current Continuous Drain Current 1 IDM Pulsed Drain Current PD@TA=25℃ Total Power Dissipation 2.0 Linear Derating Factor 0.016 W W/℃ TSTG Storage Temperature Range -55 to 150 ℃ TJ Operating Junction Temperature Range -55 to 150 ℃ THERMAL DATA Symbol Rthj-a 02/13/2008 Rev.1.00 Parameter Maximum Thermal Resistance, Junction-ambient 3 www.SiliconStandard.com Value Unit 62.5 ℃/W 1 SSM4502GM N-CH Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS RDS(ON) Parameter Min. Typ. 20 - - V VGS=10V, ID=9A - - 16 mΩ VGS=4.5V, ID=8.3A - - 18 mΩ VGS=2.5V, ID=5.2A - - 30 mΩ VDS=VGS, ID=250uA 0.5 - - V VDS=10V, ID=8.3A - 8.3 - S Drain-Source Leakage Current (Tj=25 C) VDS=20V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=70oC) VDS=16V ,VGS=0V - - 25 uA Gate-Source Leakage VGS=±12V - - ±100 nA ID=8A - 22 - nC Drain-Source Breakdown Voltage Static Drain-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS Test Conditions o IGSS 2 VGS=0V, ID=250uA 2 Max. Units Qg Total Gate Charge Qgs Gate-Source Charge VDS=16V - 3 - nC Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 9 - nC VDS=10V - 11 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=1A - 13 - ns td(off) Turn-off Delay Time RG=3.3Ω,VGS=5V - 30 - ns tf Fall Time RD=10Ω - 14 - ns Ciss Input Capacitance VGS=0V - 1350 - pF Coss Output Capacitance VDS=20V - 325 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 255 - pF Min. Typ. IS=1.8A, VGS=0V - - 1.2 V SOURCE-DRAIN DIODE Symbol VSD Parameter 2 Forward On Voltage 2 Test Conditions Max. Units trr Reverse Recovery Time IS=8A, VGS=0V, - 32 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 24 - nC 02/13/2008 Rev.1.00 www.SiliconStandard.com 2 SSM4502GM P-CH Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS RDS(ON) Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS Test Conditions Typ. -20 - - V VGS=-10V, ID=-6A - - 40 mΩ VGS=-4.5V, ID=-5A - - 45 mΩ VGS=-2.5V, ID=-4A - - 80 mΩ VDS=VGS, ID=-250uA -0.5 - - V VGS=0V, ID=-250uA 2 Max. Units VDS=-10V, ID=-2.2A - 2.2 - S o VDS=-20V, VGS=0V - - -1 uA o Drain-Source Leakage Current (Tj=70 C) VDS=-16V, VGS=0V - - -25 uA Gate-Source Leakage VGS=±12V - - ±100 nA ID=-5A - 13 - nC Drain-Source Leakage Current (Tj=25 C) IGSS Min. 2 Qg Total Gate Charge Qgs Gate-Source Charge VDS=-16V - 1.5 - nC Qgd Gate-Drain ("Miller") Charge VGS=-4.5V - 4.5 - nC VDS=-10V - 8 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=-1A - 17 - ns td(off) Turn-off Delay Time RG=3.3Ω,VGS=-5V - 24 - ns tf Fall Time RD=10Ω - 36 - ns Ciss Input Capacitance VGS=0V - 920 - pF Coss Output Capacitance VDS=-20V - 90 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 85 - pF Min. Typ. Max. 30 SOURCE-DRAIN DIODE Symbol Parameter Test Conditions 2 VSD Forward On Voltage IS=-1.8A, VGS=0V - - -1.2 V trr Reverse Recovery Time IS=-5A, VGS=0V, - 28 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 16 - nC Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse test 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135 ℃/W when mounted on Min. copper pad. THIS PRODUCT IS AN ELECTROSTATIC SENSITIVE, PLEASE HANDLE WITH CAUTION. THIS PRODUCT HAS BEEN QUALIFIED FOR CONSUMER MARKET. APPLICATIONS OR USES AS CRITERIAL COMPONENT IN LIFE SUPPORT DEVICE OR SYSTEM ARE NOT AUTHORIZED. 02/13/2008 Rev.1.00 www.SiliconStandard.com 3 SSM4502GM N-Channel 30 30 5.0V 4.5V 3.5V 2.5V 20 V G = 2.0 V 10 20 V G =2.0V 10 0 0 0 1 2 0 3 1 2 3 4 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1.8 34 I D = 5.2A I D =8.3A V G =10V T A = 25 o C Normalized R DS(ON) 30 RDS(ON0 (mΩ) 5.0V 4.5V 3.5V 2.5V T A =150 ℃ ID , Drain Current (A) ID , Drain Current (A) T A =25 ℃ 26 22 18 1.4 1.0 30 14 10 -30 0.6 1 2 3 4 5 -50 Fig 3. On-Resistance v.s. Gate Voltage 02/13/2008 Rev.1.00 0 50 100 150 T j , Junction Temperature ( o C) V GS , Gate-to-Source Voltage (V) Fig 4. Normalized On-Resistance v.s. Junction Temperature www.SiliconStandard.com 4 SSM4502GM N-Channel 2.0 8 1.6 Normalized VGS(th) (V) 10 IS(A) 6 T j =150 o C T j =25 o C 4 2 1.2 0.8 0.4 0 0.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 V SD , Source-to-Drain Voltage (V) 02/13/2008 Rev.1.00 50 100 150 o T j , Junction Temperature ( C) Fig 5. Forward Characteristic of Reverse Diode 0 Fig 6. Gate Threshold Voltage v.s. Junction Temperature www.SiliconStandard.com 5 SSM4502GM N-Channel f=1.0MHz 10000 10 ID=8A V DS = 10 V C iss 1000 8 C (pF) VGS , Gate to Source Voltage (V) 12 6 C oss C rss 100 4 2 10 0 0 10 20 30 40 1 50 5 9 13 17 21 25 V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (R thja) Duty factor=0.5 100us 10 ID (A) 1ms 10ms 1 100ms 1s 0.1 o T A =25 C Single Pulse DC 0.01 0.2 0.1 0.1 0.05 0.02 0.01 PDM 0.01 t T Single Pulse 30 Duty factor = t/T Peak Tj = PDM x Rthja + Ta -30 Rthja=135 oC/W 0.001 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 02/13/2008 Rev.1.00 www.SiliconStandard.com 6 SSM4502GM N-Channel VDS VG 90% QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Fig 11. Switching Time Waveform 02/13/2008 Rev.1.00 Q Fig 12. Gate Charge Waveform www.SiliconStandard.com 7 SSM4502GM P-Channel 20 20 T A = 150 o C - 5.0 V - 4.5 V - 3.5 V - 2.5 V V G = - 1.5 V T A =25 o C 16 -ID , Drain Current (A) -ID , Drain Current (A) 16 -5.0 V - 4.5 V - 3.5 V - 2.5 V 12 8 4 12 V G = - 1.5 V 8 4 0 0 0 1 2 3 4 5 0 1 -V DS , Drain-to-Source Voltage (V) 2 3 4 -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1.4 60 I D = -5.7 A I D = -5.7 A V G = - 10V T A =25 o C 56 Normalized R DS(ON) RDS(ON) (mΩ) 1.2 52 48 1.0 0.8 44 30 -30 0.6 40 1 2 3 4 5 -50 -V GS , Gate-to-Source Voltage (V) 50 100 150 o T j , Junction Temperature ( C) Fig 3. On-Resistance v.s. Gate Voltage 02/13/2008 Rev.1.00 0 Fig 4. Normalized On-Resistance v.s. Junction Temperature www.SiliconStandard.com 8 SSM4502GM P-Channel 8 1.2 Normalized -VGS(th) (V) -IS(A) 6 4 T j =150 o C T j =25 o C 1.0 0.8 2 0 0.6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 -V SD , Source-to-Drain Voltage (V) Fig 5. Forward Characteristic of Reverse Diode 02/13/2008 Rev.1.00 0 50 100 150 T j , Junction Temperature ( o C) Fig 6. Gate Threshold Voltage v.s. Junction Temperature www.SiliconStandard.com 9 SSM4502GM P-Channel f=1.0MHz 10000 9 I D = -5A V DS = -16V 1000 C iss C (pF) -VGS , Gate to Source Voltage (V) 12 6 C oss C rss 100 3 10 0 0.0 5.0 10.0 15.0 20.0 25.0 1 30.0 5 13 17 21 25 -V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1 Normalized Thermal Response (R thja) 100 10 -ID (A) 9 100us 1ms 1 10ms 100ms 1s 0.1 T A =25 o C Single Pulse DC Duty factor=0.5 0.2 0.1 0.1 0.05 PDM t T 0.02 30 Duty factor = t/T Peak Tj = PDM x Rthja + Ta -30 0.01 Rthja=135 oC/W Single Pulse 0.01 0.01 0.1 1 10 100 0.0001 -V DS , Drain-to-Source Voltage (V) Fig 9. Maximum Safe Operating Area 02/13/2008 Rev.1.00 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Fig 10. Effective Transient Thermal Impedance www.SiliconStandard.com 10 SSM4502GM P-Channel VG VDS 90% QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching Time Waveform 02/13/2008 Rev.1.00 Charge Q Fig 12. Gate Charge Waveform www.SiliconStandard.com 11 SSM4502GM Package Outline : SO-8 D 8 7 Millimeters 6 5 E1 1 2 3 E 4 e SYMBOLS MIN NOM MAX A 1.35 1.55 1.75 A1 0.10 0.18 0.25 B 0.33 0.41 0.51 C 0.19 0.22 0.25 D 4.80 4.90 5.00 E1 3.80 3.90 4.00 E 5.80 6.15 6.50 L 0.38 0.71 1.27 θ 0 4.00 8.00 e B 1.27 TYP A A1 DETAIL A L θ 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. c DETAIL A 02/13/2008 Rev.1.00 www.SiliconStandard.com 12 SSM4502GM Part Marking Information & Packing : SO-8 Part Number Package Code meet Rohs requirement 4502GM YWWSSS Date Code (YWWSSS) Y:Last Digit Of The Year WW:Week SSS:Sequence Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 02/13/2008 Rev.1.00 www.SiliconStandard.com 13