FAIRCHILD 74ACT646

Revised December 1998
74AC646 • 74ACT646
Octal Transceiver/Register with 3-STATE Outputs
General Description
Features
The AC/ACT646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental data handling
functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4.
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data transfers
■ 3-STATE outputs
■ 300 mil dual-in-line package
■ Outputs source/sink 24 mA
■ ACT646 has TTL compatible inputs
Ordering Code:
Order Number
Package Number
74AC646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Description
74AC646SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
74ACT646SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
IEEE/IEC
Pin Descriptions
Pin Names
A0–A7
Description
Data Register A Inputs
Data Register A Outputs
B0–B7
Data Register B Inputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Transmit/Receive Inputs
G
Output Enable Input
DIR
Direction Control Input
Data Register B Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010132.prf
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74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs
November 1988
74AC646 • 74ACT646
Function Table
Inputs
G
DIR
H
X
H or L
Data I/O (Note 1)
CPAB CPBA SAB
H or
L
X
SBA
A0–A7
Function
B0–B7
X
Isolation
H
X
X
X
X
X
H
X
X
Clock Bn Data into B Register
L
H
X
X
L
X
An to Bn—Real Time (Transparent Mode)
X
L
X
H or L
X
H
X
A Register to Bn (Stored Mode)
X
H
X
Clock An Data into A Register and Output to Bn
X
X
L
Bn to An —Real Time (Transparent Mode)
L
H
L
H
L
H
L
L
X
L
L
X
L
L
X
L
L
X
X
H or L
Input
Input
Input
Output
Output
Input
Clock An Data into A Register
Clock An Data into A Register
X
L
X
H
B Register to An (Stored Mode)
Clock Bn Data into B Register
X
H
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Storage from
Bus to Register
Real Time Transfer
A-Bus to B-Bus
FIGURE 3.
FIGURE 1.
Transfer from
Register to Bus
Real Time Transfer
B-Bus to A-Bus
FIGURE 4.
FIGURE 2.
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2
74AC646 • 74ACT646
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74AC646 • 74ACT646
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
−20 mA
VO = VCC + 0.5V
+20 mA
DC Output Voltage (VO)
4.5V to 5.5V
Input Voltage (VI)
0V to VCC
Output Voltage (VO)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
−0.5V to VCC + 0.5V
AC Devices
VIN from 30% to 70% of VCC
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
DC VCC or Ground Current
125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
±50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
2.0V to 6.0V
ACT
Minimum Input Edge Rate (∆V/∆t)
DC Output Source
or Sink Current (IO)
AC
ACT Devices
−65°C to +150°C
VIN from 0.8V to 2.0V
Junction Temperature (TJ)
VCC @ 4.5V, 5.5V
PDIP
140°C
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
Parameter
Minimum HIGH Level
Input Voltage
VIL
VOH
VCC
TA = +25°C
(V)
Typ
3.0
1.5
TA = −40°C to +85°C
Guaranteed Limits
2.1
Units
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Conditions
VOUT = 0.1V
2.1
V
or VCC − 0.1V
VOUT = 0.1V
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
IOH = −24 mA (Note 3)
IOUT = 50 µA
V
or VCC − 0.1V
IOUT = −50 µA
V
VIN = VIL or VIH
VOL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
0.36
0.44
IOH = −12 mA
V
IOH = −24 mA
V
VIN = VIL or VIH
3.0
4.5
0.36
0.44
5.5
0.36
0.44
± 0.1
IOH = 12 mA
V
IOL = 24 mA
IOH = 24 mA (Note 3)
IIN (Note 5)
Maximum Input Leakage Current
5.5
± 1.0
µA
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 4)
5.5
−75
mA
VOHD = 3.85V Min
ICC (Note 5)
Maximum Quiescent Supply Current
5.5
8.0
80.0
µA
VIN = VCC or GND
IOZT
Maximum I/O
5.5
±0.6
±6.0
µA
VI = VCC, GND
Leakage Current
VI = VCC, GND
VI (OE) = VIL, VIH
VO = VCC, GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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4
Symbol
Parameter
(V)
VIH
VIL
VOH
TA = +25°C
VCC
Typ
TA = −40°C to +85°C
Units
Conditions
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
V
VOUT = 0.1V
or VCC − 0.1V
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
V
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
3.86
3.76
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
V
IOH= −24 mA
V
IOUT = 50 µA
V
IOL= 24 mA
VIN = VIL or VIH
4.5
5.5
VOL
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
0.36
0.44
IOH= −24 mA (Note 6)
VIN = VIL or VIH
4.5
Maximum Input
Leakage Current
Maximum
ICC/Input
5.5
0.36
0.44
5.5
± 0.1
± 1.0
µA
VI = VCC, GND
1.5
mA
VI = VCC − 2.1V
5.5
0.6
IOL = 24 mA (Note 6)
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 7)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent
5.5
80.0
µA
VIN = VCC
8.0
Supply Current
IOZT
or GND
VI (OE) = VIL, VIH
Maximum I/O
Leakage Current
±0.6
5.5
±6.0
µA
VI = VCC, GND
VO = VCC, GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 8)
Min
Typ
Max
Min
Max
Propagation Delay
3.3
4.0
10.5
16.5
3.0
18.5
Clock to Bus
5.0
2.5
7.5
12.0
2.0
13.0
Propagation Delay
3.3
3.0
9.5
14.5
2.5
16.0
Clock to Bus
5.0
2.0
6.5
10.5
1.5
11.5
Propagation Delay
3.3
2.5
7.5
12.0
2.0
13.5
Bus to Bus
5.0
1.5
5.0
8.0
1.0
9.0
Propagation Delay
3.3
1.5
7.5
12.5
1.5
13.5
Bus to Bus
5.0
1.5
5.0
9.0
1.0
9.5
Propagation Delay
3.3
2.0
8.5
13.5
1.5
15.5
SBA or SAB to An or Bn
5.0
1.5
6.0
10.0
1.5
11.0
Propagation Delay
3.3
1.5
8.5
13.5
1.5
15.0
SBA or SAB to An or Bn
5.0
1.5
6.0
10.0
1.5
11.0
ns
Enable Time
3.3
2.5
7.0
11.5
2.0
12.5
ns
G to An or Bn
5.0
1.5
5.0
8.5
1.5
9.0
ns
ns
ns
ns
ns
(w/ An or Bn HIGH or LOW)
tPHL
(w/ An or Bn HIGH or LOW)
tPZH
5
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74AC646 • 74ACT646
DC Electrical Characteristics for ACT
74AC646 • 74ACT646
AC Electrical Characteristics for AC
Symbol
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Parameter
(Continued)
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
(Note 8)
Min
Typ
Max
Min
Max
Enable Time
3.3
2.5
7.5
12.5
2.0
14.0
G to An or Bn
5.0
1.5
5.5
9.0
1.5
10.0
Disable Time
3.3
3.0
8.0
12.5
2.5
13.5
G to An or Bn
5.0
2.0
6.5
10.0
2.0
11.0
Disable Time
3.3
2.0
7.5
12.0
2.0
13.5
G to An or Bn
5.0
1.5
6.0
9.5
1.5
10.5
Enable Time
3.3
2.0
6.5
11.0
1.5
12.0
DIR to An or Bn
5.0
1.5
5.0
7.5
1.0
8.5
Enable Time
3.3
2.5
7.0
11.5
2.0
13.0
DIR to An or Bn
5.0
1.5
5.0
8.0
1.0
9.0
Disable Time
3.3
2.5
7.5
11.5
1.5
12.5
DIR to An or Bn
5.0
1.5
5.5
9.5
1.5
10.0
Disable Time
3.3
1.5
7.5
12.0
1.5
13.5
DIR to An or Bn
5.0
1.5
5.5
9.5
1.5
10.5
Units
ns
ns
ns
ns
ns
ns
ns
Note 8: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements for AC
Symbol
tS
tH
tW
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
(Note 9)
Typ
Setup Time, HIGH or LOW
3.3
2.0
5.0
5.5
Bus to Clock
5.0
1.5
4.0
4.5
Hold Time, HIGH or LOW
3.3
−1.5
0
0
Bus to Clock
5.0
−0.5
0.5
1.0
Clock Pulse Width
3.3
2.0
3.5
4.5
HIGH or LOW
5.0
2.0
3.5
3.5
Note 9: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
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6
Units
Guaranteed Minimum
ns
ns
ns
Symbol
tPLH
Parameter
Propagation Delay
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 10)
Min
Typ
Max
Min
Max
5.0
3.5
12.0
14.5
3.0
16.0
ns
5.0
4.0
12.0
14.5
3.5
16.0
ns
5.0
3.0
8.5
10.5
2.5
11.5
ns
5.0
2.5
8.5
10.5
2.0
11.5
ns
5.0
3.0
9.5
11.5
2.5
12.5
ns
5.0
3.0
9.5
11.5
2.5
12.5
ns
5.0
2.0
9.0
11.0
1.5
12.0
ns
5.0
3.5
9.0
11.0
3.0
12.0
ns
5.0
5.0
10.5
13.0
4.5
14.5
ns
5.0
3.5
10.0
12.5
3.0
14.0
ns
5.0
2.0
6.5
10.5
1.5
11.5
ns
5.0
3.5
6.5
10.5
3.0
11.5
ns
5.0
5.0
8.5
12.5
4.5
13.5
ns
5.0
3.5
8.5
12.5
3.0
13.5
ns
Clock to Bus
tPHL
Propagation Delay
Clock to Bus
tPLH
Propagation Delay
Bus to Bus
tPHL
Propagation Delay
Bus to Bus
tPLH
Propagation Delay
SBA or SAB to An to Bn
(w/An or Bn
HIGH or LOW)
tPHL
Propagation Delay
SBA or SAB to An to Bn
(w/An or Bn
HIGH or LOW)
tPZH
Enable Time
G to An or Bn
tPZL
Enable Time
G to An or Bn
tPHZ
Disable Time
G to An or Bn
tPLZ
Disable Time
G to An or Bn
tPZH
Enable Time
DIR to An or Bn
tPZL
Enable Time
DIR to An or Bn
tPHZ
Disable Time
DIR to An or Bn
tPLZ
Disable Time
DIR to An or Bn
Note 10: Voltage Range 5.0 is 5.0V ±0.5V
7
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74AC646 • 74ACT646
AC Electrical Characteristics for ACT
74AC646 • 74ACT646
AC Operating Requirements for ACT
Symbol
Parameter
Setup Time, HIGH or LOW
tS
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 11)
Typ
Guaranteed Minimum
5.0
2.5
7.0
8.0
ns
5.0
0
2.5
2.5
ns
5.0
4.5
7.0
8.0
ns
BUS to Clock
tH
Hold Time, HIGH or LOW
Bus to Clock
tW
Clock Pulse Width
HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC = OPEN
CI/O
Input/Output Capacitance
15.0
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
60.0
pF
VCC = 5.0V
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8
Conditions
74AC646 • 74ACT646
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
9
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74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Package Number N24C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.