1.5 A, Step−Up/Down/ Inverting Switching Regulators PDIP−8 8 1 The STC 34063 Series is a monolithic control circuit containing the primary functions required for DC−to−DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in Step−Down and Step−Up and Voltage−Inverting applications with a minimum number of external components. • • • • • • • Operation from 2.5 V to 30 V Input Low Standby Current Current Limiting Output Switch Current to 1.5 A Output Voltage Adjustable from 1.25 to 30V Frequency Operation from 100Hz to 100 kHz Precision 1%Reference SO−8 8 1 PIN CONNECTIONS Switch Collector 1 8 Driver Collector Switch Emitter 2 7 Ipk Sense Timing Capacitor 3 6 VCC GN D 4 5 Comparator Inverting Input (Top View) 1 Drive 8 Collector Q2 S Q Ipk Sense Q1 R 7 100 2 Ipk Oscillator CT 6 VCC 3 Comparator + − Switch Collector Switch Emitter Timing Capacitor 1.25 V Reference Regulator Comparator 5 Inverting Input 4 GN D (Bottom View) This device contains 51 active transistors. Figure 1. Representative Schematic Diagram 1 S34063 S34063 MAXIMUM RATINGS Symbol Value Unit Power Supply Voltage Rating VCC 40 Vdc Comparator Input Voltage Range VIR −0.3 to + 40 Vdc Switch Collector Voltage VC(switch) 40 Vdc Switch Emitter Voltage (VPin 1 = 40 V) VE(switch) 40 Vdc Switch Collector to Emitter Voltage VCE(switch) 40 Vdc Driver Collector Voltage VC(driver) 40 Vdc Driver Collector Current (Note 1) IC(driver) 100 mA ISW 1.5 A PD RJA 1.25 100 W °C/W PD RJA 625 160 mW °C/W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature Range TAS Switch Current Power Dissipation and Thermal Characteristics Plastic Package, P, P1 Suffix TA = 25°C Thermal Resistance SOIC Package, D Suffix TA = 25°C Thermal Resistance 0 to +70 S3406 Storage Temperature Range Tstg °C −65 to +150 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = Tlow to Thigh [Note 4], unless otherwise specified.) Symbol Min Typ Max Unit Frequency (VPin 5 = 0 V, CT = 1.0 nF, TA = 25°C) fosc 24 33 42 kHz Charge Current (VCC = 5.0 V to 40 V, TA = 25°C) Ichg 24 35 42 A Idischg 140 220 260 A Discharge to Charge Current Ratio (Pin 7 to VCC, TA = 25°C) Idischg/Ichg 5.2 6.5 7.5 − Current Limit Sense Voltage (Ichg = Idischg, TA = 25°C) Vipk(sense) 250 300 350 mV Saturation Voltage, Darlington Connection ( ISW = 1.0 A, Pins 1, 8 connected) VCE(sat) − 1.0 1.3 V Saturation Voltage (Note 6) (ISW = 1.0 A, RPin 8 = 82 to VCC, Forced 20) VCE(sat) − 0.45 0.7 V hFE 50 75 − − IC(off) − 0.01 100 A 1.225 1.21 1.25 − 1.275 1.29 − − 1.4 1.4 5.0 6.0 IIB − −20 −400 nA ICC − − 4.0 mA Characteristics OSCILLATOR Discharge Current (VCC = 5.0 V to 40 V, TA = 25°C) OUTPUT SWITCH (Note 5) DC Current Gain (ISW = 1.0 A, VCE = 5.0 V, TA = 25°C) Collector Off−State Current (VCE = 40 V) COMPARATOR Threshold Voltage TA = 25°C TA = Tlow to Thigh Vth Threshold Voltage Line Regulation (VCC = 5.0 V to 40 V) S34063 S33063 V Regline Input Bias Current (Vin = 0 V) mV TOTAL DEVICE Supply Current (VCC = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = VCC, VPin 5 > Vth, Pin 2 = GND, remaining pins open) 2 1000 VCC = 5.0 V Pin 7 = VCC Pin 5 = GND TA = 25°C 200 100 50 ton 20 10 5.0 toff 2.0 200 mV/DIV 500 V OSC, OSCILLATOR VOLTAGE (V) t on−off , OUTPUT SWITCH ON-OFF TIME ( µs) S34063 1.0 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 CT, OSCILLATOR TIMING CAPACITOR (nF) 5.0 10 10 s/DIV Figure 2. Output Switch On−Off Time versus Oscillator Timing Capacitor Figure 3. Timing Capacitor Waveform VCE(sat), SATURATION VOLTAGE (V) VCE(sat), SATURATION VOLTAGE (V) 1.8 1.7 1.6 1.5 1.4 1.3 VCC = 5.0 V Pins 1, 7, 8 = VCC Pins 3, 5 = GND TA = 25°C (See Note 7) 1.2 1.1 1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 IE, EMITTER CURRENT (A) 1.4 1.1 1.0 0.9 0.7 0.6 0.4 0.3 0.2 Forced = 20 0.1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 IC, COLLECTOR CURRENT(A) 1.4 1.6 Figure 5. Common Emitter Configuration Output Switch Saturation Voltage versus Collector Current 3.6 380 3.2 I CC, SUPPLY CURRENT (mA) VCC = 5.0 V Ichg = Idischg 320 300 280 260 240 220 200 −55 VCC = 5.0 V Pin 7 = VCC Pins 2, 3, 5 = GND TA = 25°C (See Note 7) 0.5 1.6 400 360 340 Darlington Connection 0.8 Figure 4. Emitter Follower Configuration Output Saturation Voltage versus Emitter Current VIPK(sense), CURRENT LIMIT SENSE VOLTAGE (V) Pins 1, 5, 8 = Open CT = 1.0 nF TA = 25°C VCC = 5.0 V Pin 7 = VCC Pin 2 = GND 2.8 2.4 2.0 1.6 1.2 CT = 1.0 nF Pin 7 = VCC Pin 2 = GND 0.8 0.4 0 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 0 125 Figure 6. Current Limit Sense Voltage versus Temperature 5.0 10 15 20 25 30 VCC, SUPPLY VOLTAGE (V) 35 Figure 7. Standby Supply Current versus Supply Voltage 7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. 3 40 170 H S34063 L 1 8 180 S Q Q2 R Q1 7 2 1N5819 Ipk Rsc 0.22 Vin 12 V OSC 6 + CT 3 CT VCC 100 + − Comp. 1.25 V Ref Reg 1500 pF 5 4 1.0 H R2 R1 Vout 28 V/175 mA 47 k 2.2 k Vout + 330 + CO 100 Optional Filter Test Conditions Results Line Regulation Vin = 8.0 V to 16 V, IO = 175 mA 30 mV = ±0.05% Load Regulation Vin = 12 V, IO = 75 mA to 175 mA 10 mV = ±0.017% Output Ripple Vin = 12 V, IO = 175 mA 400 mVpp Efficiency Vin = 12 V, IO = 175 mA 87.7% Output Ripple With Optional Filter Vin = 12 V, IO = 175 mA 40 mVpp Figure 8. Step−Up Converter 8 1 7 R Vout 8 7 2 Rsc Vin 1 Vout 2 Rsc Vin 6 6 R 0 for constant Vin Figure 9. External Current Boost Connections for IC Peak Greater than 1.5 A 9a. External NPN Switch 9b. External NPN Saturated Switch (See Note 8) 8. If the output switch is driven into hard saturation (non−Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents (≥ 30 mA), it may take up to 2.0 s to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is magnified at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a non−Darlington configuration is used, the following output drive condition is recommended. 4 S34063 1 8 S Q Q2 Q1 R 7 2 Ipk Rsc 0.33 Vin 25 V OSC 6 100 + CT 1N5819 3 L CT VCC + − 1.25 V Ref Reg Comp. 220 H 470 pF 5 4 3.6 k R1 1.0 H Vout 5.0 V/500 mA R2 + 1.2 k 470 + CO Vout 100 Optional Filter Test Conditions Results Line Regulation Vin = 15 V to 25 V, IO = 500 mA 12 mV = ±0.12% Load Regulation Vin = 25 V, IO = 50 mA to 500 mA 3.0 mV = ±0.03% Output Ripple Vin = 25 V, IO = 500 mA 120 mVpp Short Circuit Current Vin = 25 V, RL = 0.1 1.1 A Efficiency Vin = 25 V, IO = 500 mA 83.7% Output Ripple With Optional Filter Vin = 25 V, IO = 500 mA 40 mVpp Figure 10. Step−Down Converter 8 1 1 V 8 7 Vout Rsc Vin 7 2 2 Rsc 6 Vin 6 Figure 11. External Current Boost Connections for IC Peak Greater than 1.5 A 11a. External NPN Switch 11b. External PNP Saturated Switch 5 S34063 1 8 S Q Q2 R Q1 7 2 Ipk Rsc 0.24 OSC 6 Vin 4.5 V to 6.0 V 88 H L CT VCC 3 + 100 + − Comp. + 1.25 V Ref Reg 5 1500 pF 1N5819 4 1.0 H R1 Vout −12 V/100 mA 953 R2 1000 f 8.2 k + Vout CO + 100 Optional Filter Test Conditions Results Line Regulation Vin = 4.5 V to 6.0 V, IO = 100 mA 3.0 mV = ± 0.012% Load Regulation Vin = 5.0 V, IO = 10 mA to 100 mA 0.022 V = ± 0.09% Output Ripple Vin = 5.0 V, IO = 100 mA 500 mVpp Short Circuit Current Vin = 5.0 V, RL = 0.1 910 mA Efficiency Vin = 5.0 V, IO = 100 mA 62.2% Output Ripple With Optional Filter Vin = 5.0 V, IO = 100 mA 70 mVpp Figure 12. Voltage Inverting Converter 8 1 1 Vout 8 7 2 7 Vout Vin 6 Vin 2 6 Figure 13. External Current Boost Connections for IC Peak Greater than 1.5 A 13a. External NPN Switch 13b. External PNP Saturated Switch 6