THC63LVD103 _Rev2.2 THC63LVD103 135MHz 30Bits COLOR LVDS Transmitter General Description Features The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmitted at an effective rate of 945Mbps per LVDS channel. • Wide dot clock range: 8-135MHz suited for NTSC, VGA, SVGA, XGA,SXGA and SXGA+ • • • • • • • • • PLL requires no external components Supports spread spectrum clock generator On chip jitter filtering Clock edge selectable Supports reduced swing LVDS for low EMI Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward compatible with THC63LVDM63R(18bits) / M83R(24bits) Block Diagram CMOS/TTL INPUT TC0-6 TD0-6 TE0-6 7 7 7 7 CLK IN (8 to135MHz) PARALLEL TO SERIAL 7 TA0-6 TB0-6 LVDS OUTPUT TA +/- TB +/- TC +/- TD +/- TE +/- PLL TCLK +/(8 to 135MHz) RS R/F /PDWN Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 1 THine Electronics, Inc. THC63LVD103 _Rev2.2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TB5 GND TB4 TB3 TB2 RS TB1 TB0 TA6 GND TA5 TA4 TA3 TA2 TA1 TA0 Pin Out 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ TDTD+ TETE+ LVDS GND TD5 GND TD6 TE0 TE1 TE2 VCC TE3 TE4 GND TE5 CLK IN /PDWN PLL GND PLL VCC TE6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TB6 TC0 VCC TC1 TC2 TC3 TC4 GND TC5 TC6 TD0 R/F TD1 TD2 TD3 TD4 Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 2 THine Electronics, Inc. THC63LVD103 _Rev2.2 Pin Description Pin Name Pin # Type Description TA+, TA- 30, 31 LVDS OUT TB+, TB- 28, 29 LVDS OUT TC+, TC- 24, 25 LVDS OUT TD+, TD- 20, 21 LVDS OUT TE+,TE- 18, 19 LVDS OUT TCLK+, TCLK- 22, 23 LVDS OUT TA0 ~ TA6 33,34,35,36,37,38,40 IN TB0 ~ TB6 41,42,44,45,46,48,49 IN TC0 ~ TC6 50,52,53,54,55,57,58 IN TD0 ~ TD6 59,61,62,63,64,1,3 IN TE0 ~ TE6 4,5,6,8,9,11,16 IN /PDWN 13 IN LVDS Data Out. LVDS Clock Out. Pixel Data Inputs. H: Normal operation, L: Power down (all outputs are Hi-Z) LVDS swing mode, VREF select. RS 43 IN RS LVDS Swing Small Swing Input Support VCC 350mV N/A 0.6 ~ 1.4V 350mV RS=VREFa GND 200mV N/A a. VREF is Input Reference Voltage. Input Clock Triggering Edge Select. R/F 60 IN VCC 51, 7 Power CLKIN 12 IN GND 2, 10, 39, 47, 56 Ground Ground Pins for TTL inputs and digital circuitry. LVDS VCC 27 Power Power Supply Pins for LVDS Outputs. LVDS GND 17, 26, 32 Ground Ground Pins for LVDS Outputs. PLL VCC 15 Power Power Supply Pin for PLL circuitry. PLL GND 14 Ground Ground Pins for PLL circuitry. Copyright 2001-2006 THine Electronics, Inc. All rights reserved. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in. 3 THine Electronics, Inc. THC63LVD103 _Rev2.2 Absolute Maximum Ratings 1 Supply Voltage (VCC) -0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V) CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V) LVDS Driver Output Voltage -0.3V ~ (VCC + 0.3V) Junction Temperature +125 °C Storage Temperature Range -55 °C ~ +150 °C Resistance to soldering heat +260 °C /10sec Maximum Power Dissipation @+25 °C 1.0W 1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 4 THine Electronics, Inc. THC63LVD103 _Rev2.2 Electrical Characteristics CMOS/TTL DC Specifications VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter VIH High Level Input Voltage RS=VCC or GND 2.0 VCC V VIL Low Level Input Voltage RS=VCC or GND GND 0.8 V 1.2 2.8 V VDDQ1 Conditions Min. Small Swing Voltage Typ. Max. VREF Input Reference Voltage Small Swing (RS=VDDQ/2) VSH2 Small Swing High Level Input Voltage VREF = VDDQ/2 VSL2 Small Swing Low Level Input Voltage VREF = VDDQ/2 VDDQ/2 -100mV IINC Input Current 0V ≤ V IN ≤ V CC ± 10 Units VDDQ/2 VDDQ/2 +100mV V V μA Notes: 1VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage. 2 Small swing signal is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0] and CLKIN. LVDS Transmitter DC Specifications VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter Conditions Min. Normal swing VOD Differential Output Voltage RL=100Ω RS=VCC Reduced swing RS=GND ΔVOD VOC Typ. RL=100Ω ΔVOC Change in VOC between complementary output states IOS Output Short Circuit Current IOZ Output TRI-STATE Current Units 250 350 450 mV 100 200 300 mV 35 mV Change in VOD between complementary output states Common Mode Voltage Max. 1.125 1.25 VOUT=0V, RL=100Ω /PDWN=0V, VOUT=0V to VCC 1.375 V 35 mV -24 mA ± 10 μA Supply Current VCC = 3.0V ~ 3.6V, Ta =0 °C ~ +70 °C Symbol Parameter Conditions RL=100Ω,CL=5pF VCC=3.3V, RS=VCC ITCCG Transmitter Supply Gray Scale Pattern Current RL=100Ω,CL=5pF VCC=3.3V, RS=GND Gray Scale Pattern Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 5 Typ. Max. Units f=85MHz 58 64 mA f=135MHz 70 76 mA f=85MHz 44 50 mA f=135MHz 56 62 mA THine Electronics, Inc. THC63LVD103 _Rev2.2 Gray Scale Pattern CLKOUT Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6 x=A,B,C,D,E Worst Case Pattern CLKOUT Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6 x=A,B,C,D,E Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 6 THine Electronics, Inc. THC63LVD103 _Rev2.2 Symbol Parameter Conditions RL=100Ω,CL=5pF VCC=3.3V, RS=VCC ITCCW Transmitter Supply Worst Case Pattern Current RL=100Ω,CL=5pF VCC=3.3V, RS=GND Worst Case Pattern ITCCS Transmitter Power Down Supply Current /PDWN = L Typ. Max. Units f=85MHz 69 75 mA f=135MHz 87 93 mA f=85MHz 55 61 mA f=135MHz 73 79 mA 10 μA . Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 7 THine Electronics, Inc. THC63LVD103 _Rev2.2 Switching Characteristics VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter Min. Typ. Max. Units 5.0 ns 125.0 ns tTCIT CLK IN Transition time tTCP CLK IN Period tTCH CLK IN High Time 0.35tTCP 0.5tTCP 0.65tTCP ns tTCL CLK IN Low Time 0.35tTCP 0.5tTCP 0.65tTCP ns tTCD CLK IN to TCLK+/- Delay tTS TTL Data Setup to CLK IN tTH TTL Data Hold from CKL IN tLVT LVDS Transition Time tTOP1 Output Data Position0 tTOP0 Output Data Position1 t TCP ----------- – 0.2 7 t TCP ---------7 t TCP ---------- + 0.2 7 ns tTOP6 Output Data Position2 t TCP 2 ---------- – 0.2 7 t TCP 2 ---------7 t TCP 2 ---------- + 0.2 7 ns tTOP5 Output Data Position3 t TCP 3 ---------- – 0.2 7 t TCP 3 ---------7 t TCP 3 ---------- + 0.2 7 ns tTOP4 Output Data Position4 t TCP 4 ---------- – 0.2 7 t TCP 4 ---------7 t TCP 4 ---------- + 0.2 7 ns tTOP3 Output Data Position5 t TCP 5 ---------- – 0.2 7 t TCP 5 ---------7 t TCP 5 ---------- + 0.2 7 ns tTOP2 Output Data Position6 t TCP - – 0.2 6 ---------7 t TCP 6 ---------7 t TCP 6 ---------- + 0.2 7 ns tTPLL Phase Lock Loop Set 10.0 ms 7.4 3tTCP ns 2.5 ns 0 ns -0.2 0.6 1.5 ns 0.0 +0.2 ns AC Timing Diagrams TTL Input 90% 90% CLK IN 10% 10% tTCIT tTCIT LVDS Output Vdiff=(TA+)-(TA-) 80% 80% Vdiff TA+ 5pF 100Ω 20% 20% TALVDS Output Load Copyright 2001-2006 THine Electronics, Inc. All rights reserved. tLVT 8 tLVT THine Electronics, Inc. THC63LVD103 _Rev2.2 AC Timing Diagrams tTCP TTL Inputs tTCH CLK IN VCC/2 VCC/2 VCC/2 tTCL tTS Tx0-Tx6 tTH VCC/2 VCC/2 tTCD TCLK+ VOC TCLK- Note: CLK IN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line Small Swing Inputs tTCP tTCH VDDQ CLK IN VDDQ/2 VDDQ/2 VDDQ/2 tTCL tTS VREF GND tTH VDDQ Tx0-Tx6 VDDQ/2 VDDQ/2 VREF GND tTCD TCLK+ VOC TCLK- Note: CLK IN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 9 THine Electronics, Inc. THC63LVD103 _Rev2.2 AC Timing Diagrams LVDS Output Vdiff = 0V Vdiff = 0V TCLK OUT (Differential) TA+/- TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB+/- TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC+/- TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD+/- TD6 TD5 TD4 TD3 TD2 TD1 TD0 TE+/- TE6 TE5 TE4 TE3 TE2 TE1 TE0 Previous Cycle Next Cycle tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 Phase Lock Loop Set Time /PDWN 2.0V 3.6V VCC 3.0V tTPLL CLKIN Vdiff = 0V TCLKx+/- Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 10 THine Electronics, Inc. THC63LVD103 _Rev2.2 Package 33 10.0TYP THC63LVD103 “P” PIN No.1 16 17 64 INDEX Δ 1.2MAX 1.00TYP 12.0TYP 32 49 THine 0.22 0.5TYP 48 64 Pin TQFP ,JEDEC UNITS: mm Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 11 THine Electronics, Inc. THC63LVD103 _Rev2.2 Notes to Users: 1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. EVEN IF THERE ARE INCORRECT DESCRIPTIONS, THINE IS NOT RESPOSIBLE FOR ANY PROBLEM DUE TO THEM. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. THine’s copyright, know-how and other intellectual property rights are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without THine’s prior written permission. 4. THINE IS NOT RESPONSIBLE FOR ANY PROBLEMS OF INTELLECTUAL PROPERTY RIGHTS OCCURRING DURING THC63LVD103 USE, EXCEPT FOR DAMAGES RESULTING FROM INFRINGEMENT CAUSED ONLY BY THC63LVD103 WITHOUT ANY ITEM NOT SOLD BY THINE AND/OR ANY USERS’ ACTION. THINE IS NOT RESPONSIBLE FOR PROBLEMS CAUSED BY SPECIFICATIONS SUPPLIED BY USERS. THC63LVD103 is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people’s lives, etc.). In addition, when using THC63LVD103 for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. THINE IS MAKING THE UTMOST EFFORT TO IMPROVE THE QUALITY AND RELIABILITY OF THINE’S PRODUCTS. HOWEVER, THERE IS A VERY SLIGHT POSSIBILITY OF FAILURE IN SEMICONDUCTOR DEVICES. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVD103. 7. Judgment on whether THC63LVD103 comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user’s responsibility. 8. This technical document was provisionally created during development of THC63LVD103, so there is a possibility of differences between it and the product’s final specifications. When designing circuits using THC63LVD103, be sure to refer to the final technical documents. THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0880 Fax: 81-3-3270-1771 Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 12 THine Electronics, Inc.