V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO General Description Features The V103A LVDS display interface transmitter is primarily designed to support pixel data transmission between a video processing engine and a digital video display. The data rate supports up to SXGA+ resolutions and can be used in Plasma, Rear Projector, Front Projector, CRT and LCD display applications. It can also be used in other high-bandwidth parallel data applications and provides a low EMI interconnect over a low cost, low bus width cable up to several meters in length. • Pin compatible with THine THC63LVD103 • Wide pixel clock range: 8 - 135 MHz • Guaranteed operation over -20 to +85° C ambient The V103A converts 35 bits of CMOS/TTL data, clocked on the rising or falling edge of an input clock (selectable), into six LVDS (Low Voltage Differential Signaling) serial data stream pairs. In video applications the 35 bits is normally divided into 10 bits for each R, G and B channel and 5 control bits. When combined with the V104 LVDS display interface receiver, the V103A + V104 combination provides a 35-bit wide, 90 MHz transport. The rate of each LVDS channel is 630 Mbps for a 90MHz data input clock, 945 Mbps for 135MHz. temperature • Supports a wide range of video and graphics modes including VGA, SVGA, XGA, SXGA, SXGA+, NTSC, PAL, SDTV, and HDTV up to 1080I or 720P • Internal PLL requires no external loop filter • Selectable rising or falling clock edge for data alignment • Compatible with Spread Spectrum clock source • Reduced LVDS output voltage swing mode (selectable) to minimize EMI • CMOS/TTL data inputs can be configured for reduced input voltage swing • • • • Single 3.3 V supply Low power consumption CMOS design Power down mode 64-pin TQFP lead free package Block Diagram 7 TA+ TB0-6 7 TA- TC0-6 7 TB+ 7 TB- TA0-6 TD0-6 TE0-6 7 Parallel to Serial RS TC+ TCTD+ R/F TD- /PWDN TE+ TECLKIN (8 to 135 MHz) V103A Datasheet PLL 1 TCLK+ TCLK- 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TD4 TD3 TD2 TD1 R/F TD0 TC6 TC5 GND TC4 TC3 TC2 TC1 VCC TC0 TB6 Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-pin TQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TB5 GND TB4 TB3 TB2 RS TB1 TB0 TA6 GND TA5 TA4 TA3 TA2 TA1 TA0 LVDSGND TE+ TETD+ TDTCLK+ TCLKTC+ TCLVDSGND LVDSVCC TB+ TBTA+ TALVDSGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TD5 GND TD6 TE0 TE1 TE2 VCC TE3 TE4 GND TE5 CLKIN /PWDN PLLGND PLLVCC TE6 V103A Datasheet 2 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO Pin Descriptions Pin Number Pin Name Pin Type 30, 31 TA+, TA- 28, 29 TB+, TB- 24, 25 TC+, TC- 20, 21 TD+, TD- 18, 19 TE+, TE- 22, 23 TCLK+, TCLK- 33, 34, 35, 36, 37, 38, 40 TA0 ~ TA6 41, 42, 44, 45, 46, 48, 49 TB0 ~ TB6 50, 52, 53, 54, 55, 57, 58 TC0 ~ TC6 59, 61, 62, 63, 64, 1, 3 TD0 ~ TD6 4, 5, 6, 8, 9, 11, 16 TE0 ~ TE6 13 Pin Description LVDS OUT LVDS Serial Data Output Pairs LVDS OUT LVDS Reference Clock Output Pair IN CMOS/TTL (or small signal) Data Bit Inputs /PWDN IN High: Normal device operation Low: Power down; all outputs become high impedance 43 RS IN Voltage level on this pin sets LVDS output swing voltage and data input swing voltage; refer to the table at the bottom of this page. 60 R/F IN Input Clock triggering edge select. High: Rising edge; Low: Falling edge. 51, 7 VCC Power 12 CLKIN IN 2, 10, 39, 47, 56 GND Ground Ground pins for TTL inputs and digital circuitry. 27 LVDSVCC Power Power supply pins for LVDS outputs. 17, 26, 32 LVDSGND Ground Ground pins for LVDS outputs. 15 PLLVCC Power Power supply pin for PLL circuitry. 14 PLLGND Ground Ground pin for PLL circuitry. Power supply pins for TTL inputs and digital circuitry. Clock Input. RS Input Voltage Configuration to set LVDS Output Swing and Data Input Swing RS Input Voltage LVDS Output Swing CMOS/TTL Input Configuration (Input Voltage Swing) VCC 350 mV Standard Configuration1 0.6 ~ 1.4 V (VREF1) 350 mV Small Input Swing Configuration1 GND 200 mV Standard Configuration1 Note 1: Refer to DC Electrical Characteristics. V103A Datasheet 3 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO External Components Decoupling capacitors should be used for all power pins. The V103A requires no other external components. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the V103A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VCC -0.3 V to +4.0 V CMOS/TTL Input Voltage -0.3 V to VCC+0.3 V CMOS/TTL Output Voltage -0.3 V to VCC+0.3 V LVDS Driver Output Voltage -0.3 V to VCC+0.3 V Storage Temperature -55 to +150°C Junction Temperature 120°C Soldering Temperature (10 seconds) 260°C Maximum Power Dissipation @ 25°C 1.0 W Recommended Operation Conditions Min. Parameter Ambient Operating Temperature -20 Power Supply Voltage (measured in respect to GND) +3.0 V103A Datasheet 4 Typ. +3.3 Max. Units +85 °C +3.6 V 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO DC Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature -20 to +85°C Parameter Symbol Conditions Min. Typ. Max. Units CMOS/TTL Inputs, Standard Configuration Input High Voltage VIH RS=VCC or GND 2.00 VCC V Input Low Voltage VIL RS=VCC or GND GND 0.80 V Input Current IINC 0V<VIN<VCC ±10 µA 2.8 V CMOS/TTL Inputs, Small Input Swing Configuration Max Input Swing Voltage VDDQ1 VREF = VRS = VDDQ/2 Input Reference Voltage into pin RS VREF High Level Input Voltage (for small input swing condition) VSH2 VREF=VDDQ/2 Low Level Input Voltage (for small input swing condition) VSL2 VREF=VDDQ/2 1.2 VDDQ/2 V VDDQ/2 +0.1V V VDDQ/2 -0.1V V Note 1: VDDQ voltage defines the max voltage of the small swing input and is not an actual input into the device. Note 2: Small input swing voltage is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0], and CLKIN. LVDS Transmitter DC Specifications Differential Output Voltage, RL = 100Ω Change in VOD Between Complimentary Output States Common Mode Voltage Change in VOC Between Complimentary Output States VOD Normal swing RS = VCC 250 350 450 mV Reduced swing RS = GND 100 200 300 mV 35 mV DVOD VOC RL = 100Ω 1.125 1.250 DVOC 1.375 V 35 mV Output Short Circuit Current IOS VOUT = 0V, RL = 100Ω -24 mA Output Tri-State Current IOZ /PWDN = 0V, VOUT = 0V to VCC ±10 µA Supply Current Transmitter Supply Current ITCCG RL = 100Ω, CL=5 pF, VCC = 3.3 V, RS = VCC Gray Scale Pattern RL = 100Ω, CL=5 pF, VCC = 3.3 V, RS = GND Gray Scale Pattern Transmitter Supply Current ITCCW RL = 100Ω, CL = 5 pF, VCC = 3.3 V, RS = VCC Worst Case Pattern RL = 100Ω, CL= 5 pF, VCC = 3.3 V, RS = GND Worst Case Pattern Transmitter Power Down Supply Current V103A Datasheet f = 85 MHz 58 64 mA f =135 MHz 70 76 mA f = 85 MHz 44 50 mA f =135 MHz 56 62 mA f = 85 MHz 69 75 mA f =135 MHz 87 93 mA f = 85 MHz 55 61 mA f =135 MHz 73 79 mA 10 µA /PWDN = L ITCCS 5 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO Gray Scale Pattern CLKIN Tx 0 Tx 1 Tx 2 Tx 3 Tx 4 Tx 5 Tx 6 x = A, B, C, D, E Worst Case Pattern CLKIN Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6 x = A, B, C, D, E V103A Datasheet 6 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO AC Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature -20 to +85°C Parameter Symbol Min. Typ. Max. Units Switching Characteristics CLK IN Transition Time tTCIT CLK IN Period tTCP 7.4 CLK IN High Time tTCH 0.35tTCP CLK IN Low Time tTCL 0.35tTCP CLK IN to TCLK± Delay tTCD 5 ns 125.0 ns 0.5tTCP 0.65tTCP ns 0.5tTCP 0.65tTCP ns 3tTCP ns TTL Data Setup to CLK IN tTS 2.5 ns TTL Data Hold from CLK IN tTH 0 ns LVDS Transition Time tLVT Output Data Position0 tTOP1 Output Data Position1 tTOP0 Output Data Position2 Output Data Position3 Output Data Position4 Output Data Position5 Output Data Position6 Phase Lock Loop Set tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 -0.2 0.6 1.5 0.0 0.2 ns ns ns tTCP -0.2 7 tTCP 7 tTCP +0.2 7 t 2 TCP -0.2 7 t 2 TCP 7 t 2 TCP +0.2 7 t 3 TCP -0.2 7 t 3 TCP 7 t 3 TCP +0.2 7 t 4 TCP -0.2 7 t 4 TCP 7 t 4 TCP +0.2 7 t 5 TCP -0.2 7 t 5 TCP 7 t 5 TCP +0.2 7 t 6 TCP -0.2 7 t 6 TCP 7 t 6 TCP +0.2 7 ns ns ns ns ns tTPLL 10.0 ms Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case V103A Datasheet Symbol Conditions Min. Typ. Max. Units θJA Still air 53 °C/W θJA 1 m/s air flow 40 °C/W θJA 3 m/s air flow 33 °C/W 8 °C/W θJC 7 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO AC Timing Diagrams 90% TTL Input 90% 10% 10% CLK IN tTCIT LVDS Output tTCIT 80% 80% 20% VDIFF = (TA+) – (TA-) 20% tLVT TA+ 5 pF tLVT 100 ohms TA- tTCP TTL Inputs tTCH CLK IN VCC/2 VCC/2 VCC/2 tTCL tTS Tx0-Tx6 tTH VCC/2 VCC/2 tTCD TCLK+ VOC TCLKNote: CLK IN: for R/F = GND, denote as solid line. for R/F = VCC, denote as dashed line V103A Datasheet 8 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO tTCP Small Swing Inputs tTCH CLK IN VDDQ/2 VDDQ/2 VREF VDDQ/2 VDDQ GND tTCL tTS tTH VDDQ Tx0-Tx6 VDDQ/2 VDDQ/2 VREF GND tTCD TCLK+ VOC TCLKNote: CLK IN: for R/F = GND, denote as solid line. for R/F = VCC, denote as dashed line LVDS Output VDIFF = 0V VDIFF = 0V TCLK OUT (Differential) TA+/- TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB+/- TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC+/- TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD+/- TD6 TD5 TD4 TD3 TD2 TD1 TD0 TE+/- TE6 TE5 TE4 TE3 TE2 TE1 TE0 Previous Cycle Next Cycle tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 V103A Datasheet 9 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO Phase Lock Loop Set Time 2.0 V 3.6 V /PWDN 3.0 V tTPLL VCC CLKIN VDIFF = 0V TCLKx+/- V103A Datasheet 10 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO Package Outline and Package Dimensions (64-pin TQFP) Package dimensions are kept current with JEDEC Publication No. 95, variation ACD. ALL DIMENSIONS ARE IN MILLIMETERS. SYMBOL MIN/MAX N 64 A -- / 1.20 A1 0.05 / 0.15 A2 0.95 / 1.05 b 0.17 / 0.27 c 0.09 / 0.20 D 12.00 BASIC D1 10.00 BASIC D2 7.50 Ref. E 12.00 BASIC E1 10.00 BASIC E2 7.50 Ref. e 0.50 BASIC L 0.45 / 0.75 θ 0° / 7° ccc -- / 0.08 D3&E3 - Ordering Information Part / Order Number V103AYLF V103AYLFT Marking V103AYLF V103AYLF Shipping Packaging Package Temperature Tray (160 units per tray) 64-pin TQFP -20 to +85° C Tape and Reel 64-pin TQFP -20 to +85° C The “LF” part number suffix denotes the device as Lead (Pb) Free and that the device is RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. V103A Datasheet 11 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m