WINBOND W78C032C

W78C32C/W78C032C DATA SHEET
8-BIT MICROCONTROLLER
Table of Contents1.
GENERAL DESCRIPTION ......................................................................................................... 2
2.
FEATURES ................................................................................................................................. 2
3.
PIN CONFIGURATIONS ............................................................................................................ 3
4.
PIN DESCRIPTION..................................................................................................................... 4
5.
FUNCTIONAL DESCRIPTION ................................................................................................... 6
5.1
TIMERS 0, 1, AND 2....................................................................................................... 6
5.2
CLOCK............................................................................................................................ 6
5.2.1
5.2.2
5.3
POWER MANAGEMENT ............................................................................................... 6
5.3.1
5.3.2
5.3.3
6.
8.
9.
10.
IDLE MODE......................................................................................................................6
POWER-DOWN MODE....................................................................................................7
RESET .............................................................................................................................7
ELECTRICAL CHARACTERISTICS........................................................................................... 8
6.1
ABSOLUTE MAXIMUM RATINGS ................................................................................. 8
6.2
D.C. CHARACTERISTICS.............................................................................................. 8
6.3
A.C. CHARACTERISTICS.............................................................................................. 9
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
7.
CRYSTAL OSCILLATOR .................................................................................................6
EXTERNAL CLOCK .........................................................................................................6
CLOCK INPUT WAVEFORM ...........................................................................................9
PROGRAM FETCH CYCLE ...........................................................................................10
DATA READ CYCLE ......................................................................................................10
DATA WRITE CYCLE ....................................................................................................11
PORT ACCESS CYCLE.................................................................................................11
TIMING waveformS................................................................................................................... 12
7.1
PROGRAM FETCH CYCLE ......................................................................................... 12
7.2
DATA READ CYCLE .................................................................................................... 12
7.3
DATA WRITE CYCLE................................................................................................... 13
7.4
PORT ACCESS CYCLE ............................................................................................... 13
TYPICAL APPLICATION CIRCUIT........................................................................................... 14
8.1
USING EXTERNAL PROGRAM MEMORY AND CRYSTAL ....................................... 14
8.2
EXPANDED EXTERNAL DATA MEMORY AND OSCILLATOR ................................. 15
PACKAGE DIMENSIONS ......................................................................................................... 16
9.1
40-PIN DIP.................................................................................................................... 16
9.2
44-PIN PLCC ................................................................................................................ 16
9.3
44-PIN QFP .................................................................................................................. 17
REVISION HISTORY ................................................................................................................ 18
-1-
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
1. GENERAL DESCRIPTION
The W78C032C microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is compatible with the industry standard 80C32 microcontroller series.
The W78C032C contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.
The W78C032C microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
1.processor.
2. FEATURES
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8-bit CMOS microcontroller
Fully static design
Low standby current at full supply voltage
DC-40 MHz operation
256 bytes of on-chip scratchpad RAM
ROMless operation
64K bytes program memory address space
64K bytes data memory address space
Four 8-bit bidirectional ports
Three 16-bit timer/counters
One full duplex serial port
Boolean processor
Six-source, two-level interrupt capability
Built-in power management
Packages:
− Lead Free (RoHS) DIP 40:
W78C032C40DL
− Lead Free (RoHS) PLCC 44: W78C032C40PL
− Lead Free (RoHS) PQFP 44: W78C032C40FL
-2-
W78C32C/W78C032C
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44-Pin PLCC
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
A
T
D
2
0
,
,
P
P
1
V 0
. N C .
0 C C 0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
P
3
.
7
,
/
R
D
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
X
T
A
L
2
X V N P
T S C 2
A S
.
L
0
1
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
A
D
3
,
P
0
.
3
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
44-Pin QFP
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
P1.5
P1.6
P1.7
RST
RXD, P3.0
NC
TXD, P3.1
Vcc
P1.5
P1.6
P1.7
RST
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
NC
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
RXD,
P3 0 NC
TXD,
INT0,
P3 2
INT1,
P3T0,
3 P3.4
T1, P3.5
P
2
.
4
,
A
1
2
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
26
8
9
25
10
24
23
11
12 13 14 15 16 17 18 19 20 21 22
1
2
P
3
.
6
,
/
W
R
-3-
T
2
,
P
1
V
. N C
0 C C
P
3
.
7
,
/
R
D
X
T
A
L
2
X V N P
T S C 2
A S
.
L
0
1
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
NC
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P
2
.
4
,
A
1
2
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
4. PIN DESCRIPTION
P0.0−P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0−P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also
serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0−P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0−P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
ALTERNATE FUNCTION
P3.0
RXD Serial Receive Data
P3.1
TXD Serial Transmit Data
P3.2
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
P3.4
T0 Timer 0 Input
P3.5
T1 Timer 1 Input
P3.6
WR Data Write Strobe
P3.7
RD Data Read Strobe
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This
pin should be kept low for all W78C032C operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.
-4-
W78C32C/W78C032C
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a
weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VCC
Power Supplies. These are the chip ground and positive supplies.
-5-
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
5. FUNCTIONAL DESCRIPTION
The W78C032C architecture consists of a core controller surrounded by various registers, four
general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor
supports 111 different instruction and references both a 64K program address space and a 64K data
storage space.
5.1
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature of
the W78C032C: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
5.2
Clock
The W78C032C is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C032C relatively insensitive to duty
cycle variations in the clock.
5.2.1
Crystal Oscillator
The W78C032C incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must
be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from
each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
5.2.2
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
5.3
5.3.1
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
-6-
W78C32C/W78C032C
5.3.2
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
5.3.3
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C032C is
used with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
-7-
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
6. ELECTRICAL CHARACTERISTICS
6.1
Absolute Maximum Ratings
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VCC−VSS
-0.3
+7.0
V
Input Voltage
VIN
VSS -0.3
VCC +0.3
V
Operating Temperature
TA
0
70
°C
Storage Temperature
TST
-55
+150
°C
DC Power Supply
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
6.2
D.C. Characteristics
VCC−VSS = 5V ±10%, TA = 25° C, FOSC = 20 MHz unless otherwise specified.
PARAMETER
SYM.
SPECIFICATION
TEST CONDITIONS
TYP.
MAX.
4.5
5
5.5
V
Operating Voltage
VDD
Operating Current
IDD
No load
VDD = 5.5V
-
-
30
mA
IIDLE
Idle mode
VDD = 5.5V
-
-
6
mA
Power-down mode
VDD = 5.5V
-
-
50
μA
-75
-
+10
μA
-
+184
+350
μA
Idle Current
Power Down Current
IPWDN
-
UNIT
MIN.
Input Current
P1, P3
IIN1
VDD = 5.5V
VIN = 0V or VDD
Input Current
RST (*2)
IIN2
VDD = 5.5V
VIN = VDD
Input Leakage Current
P0 (*1)
ILK
VDD = 5.5V
0V<VIN<VDD
-10
-
+10
μA
Output Low Voltage
P1, P2 (*1), P3
VOL1
VDD = 4.5V
IOL1 = +2 mA
-
-
0.45
V
Output Low Voltage
ALE, PSEN , P0 (*1)
VOL2
VDD = 4.5V
IOL2 = +4 mA
-
-
0.45
V
Output High Voltage
P1, P3
VOH1
VDD = 4.5V
IOH1 = -100 μA
2.4
-
-
V
VOH2
VDD = 4.5V
IOH2 = -400 μA
2.4
-
-
V
VIL1
VDD = 4.5V
0
-
0.8
V
Output High Voltage
ALE, PSEN , P0 (*1), P2
(*1)
Input Low Voltage
P1, P3
-8-
W78C32C/W78C032C
DC Characteristics, continued
PARAMETER
Input Low Voltage
XTAL1, RST (*3)
Input High Voltage
P1, P3
Input High Voltage
XTAL1, RST (*3)
SYM.
SPECIFICATION
TEST CONDITIONS
UNIT
MIN.
TYP.
MAX.
0.8
VIL2
VDD = 4.5V
0
-
VIH1
VDD = 5.5V
2.4
-
VIH2
VDD = 5.5V
3.5
-
VDD
+0.2
VDD
+0.2
V
V
V
Notes:
1. P0 and P2 are in external access mode.
2. RST pin has an internal pull-down resistor of about 30K Ω.
3. XTAL1 is a CMOS input and RST is a Schmitt trigger input.
6.3
A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
6.3.1
Clock Input Waveform
XTAL1
T CH
T CL
F OP,
PARAMETER
TCP
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
FOP
0
-
40
MHz
1
Clock Period
TCP
25
-
-
nS
2
Clock High
TCH
10
-
-
nS
3
Clock Low
TCL
10
-
-
nS
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
-9-
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
6.3.2
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
TAAS
1 TCP-Δ
-
-
nS
4
Address Hold after ALE Low
TAAH
1 TCP-Δ
-
-
nS
1, 4
ALE Low to PSEN Low
TAPL
1 TCP-Δ
-
-
nS
4
PSEN Low to Data Valid
TPDA
-
-
2 TCP
nS
2
Data Hold after PSEN High
TPDH
0
-
1 TCP
nS
3
Data Float after PSEN High
TPDZ
0
-
1 TCP
nS
ALE Pulse Width
TALW
2 TCP-Δ
2 TCP
-
nS
4
PSEN Pulse Width
TPSW
3 TCP-Δ
3 TCP
-
nS
4
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "Δ" ( due to buffer driving delay and wire loading) is 20 nS.
6.3.3
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to RD Low
TDAR
3 TCP-Δ
-
3 TCP+Δ
nS
1, 2
RD Low to Data Valid
TDDA
-
-
4 TCP
nS
1
Data Hold after RD High
TDDH
0
-
2 TCP
nS
Data Float after RD High
TDDZ
0
-
2 TCP
nS
RD Pulse Width
TDRD
6 TCP-Δ
6 TCP
-
nS
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
- 10 -
2
W78C32C/W78C032C
6.3.4
Data Write Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
ALE Low to WR Low
TDAW
3 TCP-Δ
-
3 TCP+Δ
nS
Data Valid to WR Low
TDAD
1 TCP-Δ
-
-
nS
Data Hold from WR High
TDWD
1 TCP-Δ
-
-
nS
WR Pulse Width
TDWR
6 TCP-Δ
6 TCP
-
nS
Note: "Δ" ( due to buffer driving delay and wire loading) is 20 nS.
6.3.5
Port Access Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Port Input Setup to ALE Low
TPDS
1 TCP
-
-
nS
Port Input Hold from ALE Low
TPDH
0
-
-
nS
Port Output to ALE
TPDA
1 TCP
-
-
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 11 -
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
7. TIMING WAVEFORMS
7.1
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
TALW
ALE
TAPL
PSEN
TPSW
TAAS
PORT 2
TPDA
TAAH
TPDH, TPDZ
PORT 0
A0-A7
Code
7.2
Data
A0-A7
Code
A0-A7
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
XTAL1
ALE
PSEN
PORT 2
A8-A15
A0-A7
DATA
PORT 0
T DAR
TDDA
T DDH, T DDZ
RD
TDRD
- 12 -
S6
S1
S2
S3
W78C32C/W78C032C
Timing Waveforms, continued
7.3
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
PORT 0
A8-A15
A0-A7
DATA OUT
WR
TDAW
7.4
TDWD
TDAD
TDWR
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDA
TPDH
PORT
DATA OUT
INPUT
SAMPLE
- 13 -
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
8. TYPICAL APPLICATION CIRCUIT
8.1
Using External Program Memory and Crystal
VCC
31
XTAL1
18
XTAL2
9
RST
12
13
14
15
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
10 u
R
CRYSTAL
8.2 K
C1
EA
19
C2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
RD
WR
PSEN
ALE
TXD
RXD
17
16
29
30
11
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
AD0 3
AD1 4
AD2 7
AD3 8
AD4 13
AD5 14
AD6 17
AD7 18
D0
D1
D2
D3
D4
D5
D6
D7
GND 1
11
OC
G
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
74LS373
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
GND 20
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
CE
OE
27512
W78C32C/W78C032C
Figure A
CRYSTAL
C1
C2
R
16 MHz
30P
30P
-
24 MHz
15P
15P
-
33 MHz
10P
10P
6.8K
40 MHz
5P
5P
6.8K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
- 14 -
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
W78C32C/W78C032C
8.2
Expanded External Data Memory and Oscillator
VCC
31
19
10 u
8.2 K
OSCILLATOR
EA
XTAL1
18
XTAL2
9
RST
INT0
12
13
14
15
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
AD0 3
AD1 4
AD2 7
AD3 8
AD4 13
AD5 14
AD6 17
AD7 18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND 1 OC
11 G
RD
17
16
PSEN 29
ALE 30
11
TXD 10
RXD
WR
74LS373
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
A0 10
A1 9
A2 8
A3 7
A4 6
A5 5
A6 4
A7 3
A8 25
A9 24
A10 21
A11 23
A12 2
A13 26
A14 1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
GND 20
22
27
CE
OE
WR
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
20256
W78C32C/W78C032C
Figure B
- 15 -
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
9. PACKAGE DIMENSIONS
9.1
40-pin DIP
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
E1
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.254
0.150 0.155 0.160
3.81
0.016 0.018 0.022
0.406 0.457 0.559
0.048 0.050 0.054
1.219 1.27
0.008 0.010
0.014
0.203 0.254 0.356
2.055
2.070
52.20 52.58
20
1
3.937 4.064
1.372
0.590 0.600 0.610 14.986 15.24 15.494
0.540
0.545 0.550 13.72 13.84 13.97
0.090 0.100 0.110 2.286
2.54
0.120 0.130 0.140 3.048
3.302 3.556
0
a
eA
S
5.334
0.210
0.010
2.794
0
15
15
0.630 0.650 0.670 16.00 16.51 17.01
0.090
2.286
Notes:
E
S
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the .mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
c
A A2
A1
Base Plane
Seating Plane
L
B
e1
9.2
eA
a
B1
44-pin PLCC
HD
D
6
1
44
40
7
Symbol Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
39
E
17
HE
GE
29
18
28
c
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
0.185
4.699
0.508
0.020
0.145 0.150 0.155 3.683 3.81 3.937
0.026 0.028 0.032
0.66
0.711 0.813
0.016 0.018 0.022 0.406 0.457 0.559
0.008 0.010 0.014 0.203 0.254 0.356
0.648 0.653 0.658 16.46 16.59 16.71
0.648 0.653 0.658 16.46 16.59 16.71
0.050 BSC
1.27
BSC
0.590 0.610 0.630 14.99 15.49 16.00
0.590 0.610 0.630 14.99 15.49 16.00
0.680 0.690 0.700 17.27 17.53 17.78
0.680 0.690 0.700 17.27 17.53 17.78
0.090 0.100 0.110 2.296
2.54 2.794
0.004
L
Notes:
A2 A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
θ
e
b
b1
Seating Plane
A1
y
GD
- 16 -
0.10
W78C32C/W78C032C
Package Dimensions, continued
9.3
44-pin QFP
HD
D
Symbol
34
44
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
33
1
E HE
11
12
e
b
22
Dimension in inch
Dimension in mm
Min. Nom. Max.
Min. Nom.
Max.
---
---
---
---
0.002
0.01
0.02
0.05
0.25
0.5
0.075
0.081
0.087
1.90
2.05
2.20
0.01
0.014
0.018
0.25
0.35
0.45
0.004
0.006
0.010
0.101
0.152
0.254
0.390
0.394
0.398
9.9
10.00
10.1
0.390
0.394
0.398
9.9
10.00
10.1
---
---
0.025
0.031
0.036
0.635
0.80
0.952
0.510
0.520
0.530
12.95
13.2
13.45
0.510
0.520
0.530
12.95
13.2
13.45
0.025
0.031
0.037
0.65
0.8
0.95
0.051
0.063
0.075
1.295
1.6
1.905
0.08
0.003
0
7
0
7
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
c
A2 A
A1
Seating Plane
See Detail F
y
θ
L
L1
Detail F
- 17 -
Publication Release Date: December 4, 2006
Revision A6
W78C32C/W78C032C
10. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A2
July 1999
-
Initial Issued
A3
June, 2004
2
Revise part number in the item of packages
A4
April 19, 2005
17
Add Important Notice
A5
June 7, 2005
2
Add Lead Free (RoHS) parts
A6
December 4, 2006
Remove block diagram
2
Remove all Leaded package parts
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 18 -