WINBOND W78E051B40FL

W78E51B Data Sheet
8-BIT MICROCONTROLLER
Table of Contents1.
GENERAL DESCRIPTION ......................................................................................................... 3
2.
FEATURES ................................................................................................................................. 3
3.
PIN CONFIGURATIONS ............................................................................................................ 4
4.
PIN DESCRIPTION..................................................................................................................... 5
5.
BLOCK DIAGRAM ...................................................................................................................... 6
6.
FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.
8.
6.1
New Defined Peripheral.................................................................................................. 7
6.2
Reduce EMI Emission .................................................................................................... 8
6.3
Watchdog Timer ............................................................................................................. 9
6.4
Clock ............................................................................................................................. 10
6.5
Power Management...................................................................................................... 10
6.6
Reset............................................................................................................................. 11
6.7
On-Chip ROM Characteristics ...................................................................................... 11
6.7.1
Read Operation ..............................................................................................................11
6.7.2
Output Disable Condition................................................................................................11
6.7.3
Program Operation .........................................................................................................11
6.7.4
Program Verify Operation ...............................................................................................11
6.7.5
Erase Operation .............................................................................................................11
6.7.6
Erase Verify Operation ...................................................................................................11
6.7.7
Program/Erase Inhibit Operation ....................................................................................12
SECURITY BITS ....................................................................................................................... 12
7.1
Lock Bit ......................................................................................................................... 13
7.2
MOVC Inhibit................................................................................................................. 13
7.3
Encryption ..................................................................................................................... 13
ELECREICAL CHARACTERISTICS......................................................................................... 14
8.1
Absolute Maximum Ratings .......................................................................................... 14
8.2
D.C. Characteristics...................................................................................................... 14
8.3
A.C. Characteristics ...................................................................................................... 15
8.3.1
Clock Input Waveform ....................................................................................................16
8.3.2
Program Fetch Cycle......................................................................................................16
8.3.3
Data Read Cycle ............................................................................................................16
8.3.4
Data Write Cycle.............................................................................................................17
8.3.5
Port Access Cycle ..........................................................................................................17
8.3.6
Program Operation .........................................................................................................17
-1-
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
9.
10.
11.
12.
TIMING WAVEFORMS ............................................................................................................. 18
9.1
Program Fetch Cycle .................................................................................................... 18
9.2
Data Read Cycle........................................................................................................... 18
9.3
Data Write Cycle........................................................................................................... 19
9.4
Port Access Cycle......................................................................................................... 19
9.5
Program Operation ....................................................................................................... 20
TYPICAL APPLICATION CIRCUITS ........................................................................................ 21
10.1
Expanded External Program Memory and Crystal ....................................................... 21
10.2
Expanded External Data Memory and Oscillator ......................................................... 22
PACKAGE DIMENSIONS ......................................................................................................... 23
11.1
40-pin DIP ..................................................................................................................... 23
11.2
44-pin PLCC ................................................................................................................. 23
11.3
44-pin PQFP ................................................................................................................. 24
REVISION HISTORY ................................................................................................................ 25
-2-
W78E51B
1. GENERAL DESCRIPTION
The W78E51B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E51B is fully compatible with the standard 8051.
The W78E51B contains an 4K bytes Flash EPROM; a 128 bytes RAM; four 8-bit bi-directional and bitaddressable I/O ports; an additional 4-bit I/O port P4; two 16-bit timer/counters; a hardware watchdog
timer and a serial port. These peripherals are supported by seven sources two-level interrupt
capability. To facilitate programming and verification, the Flash EPROM inside the W78E51B allows
the program memory to be programmed and read electronically. Once the code is confirmed, the user
can protect the code for security.
The W78E51B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
y
y
y
y
y
y
y
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 4.5V to 5.5V
128 bytes of on-chip scratchpad RAM
4 KB On-chip Flash EPROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
y
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Two 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
Seven sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
y
y
y
y
y
y
y
y
−
−
−
−
−
−
DIP 40:
W78E51B-40
PLCC 44: W78E51BP-40
PQFP 44: W78E51BF-40
Lead Free (RoHS) DIP 40:
W78E051B40DL
Lead Free (RoHS) PLCC 44: W78E051B40PL
Lead Free (RoHS) PQFP 44: W78E051B40FL
-3-
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
3. PIN CONFIGURATIONS
40-Pin DIP (W78E51B)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44-Pin PLCC (W78E51BP)
/
I
A
N
D
T
0
3
,
,
P P P P P P
P
1 1 1 1 1 4 V 0
. . . . . . D .
4 3 2 1 0 2 D 0
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
P
2
.
1
,
A
9
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin QFP (W78E51BF)
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
/
I
A
N
D
T
0
3
,
,
P P P P P P
P
1 1 1 1 1 4 V 0
. . . . . . D .
4 3 2 1 0 2 D 0
A
D
3
,
P
0
.
3
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
VDD
P1.5
P1.6
P1.7
RST
RXD, P3.0
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
INT2, P4.3
TXD, P3.1
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
INT1, P3.3
T0, P3.4
T1, P3.5
INT0, P3.2
P
2
.
4
,
A
1
2
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
1
2
P
3
.
6
,
/
W
R
-4-
A
D
1
,
P
0
.
1
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
W78E51B
4. PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EA
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is within
on-chip ROM area.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ALE
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RST
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
XTAL1
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS
GROUND: Ground potential
VDD
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
P0.0−P0.7 address/data bus during accesses to external memory. The pins of Port 0 are opendrain and should connect to pull up resistors if necessary while in programming.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
P1.0−P1.7
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
P2.0−P2.7
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
P3.0−P3.7
INT1 (P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) : External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
P4.0−P4.3 function pins. It can be used as general I/O port or external interrupt input sources
( INT2 / INT3 ).
-5-
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
5. BLOCK DIAGRAM
P1.0
~
P1.7
Port
1
Port 1
Latch
B
ACC
INT2
Port 0
Latch
Interrupt
INT3
T2
T1
Port
0
P0.0
~
P0.7
Port
2
P2.0
~
P2.7
DPTR
Timer
0
Stack
Pointer
PSW
ALU
Temp Reg.
Timer
1
PC
Incrementor
UART
Addr. Reg.
P3.0
~
P3.7
Port
3
Port 3
Latch
SFR RAM
Address
Instruction
Decoder
&
Sequencer
128 bytes
RAM & SFR
ROM
Port 2
Latch
Bus & Clock
Controller
P4.0
~
P4.3
Port
4
Port 4
Latch
Watchdog
Timer
Oscillator
Reset Block
XTAL1 XTAL2 ALE PSEN
RST
-6-
Power control
Vcc
Vss
W78E51B
6. FUNCTIONAL DESCRIPTION
The W78E51B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
6.1
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3
PX3:
EX3:
IE3:
IT3:
PX2:
EX2:
IE2:
IT2:
EX3
IE3
IT3
PX2
EX2
IE2
IT2
External interrupt 3 priority high if set
External interrupt 3 enable if set
If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
External interrupt 2 priority high if set
External interrupt 2 enable if set
If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt information
VECTOR
ADDRESS
POLLING SEQUENCE
WITHIN PRIORITY
LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT TYPE
EDGE/LEVEL
External Interrupt 0
03H
0 (highest)
IE.0
TCON.0
Timer/Counter 0
0BH
1
IE.1
-
INTERRUPT SOURCE
External Interrupt 1
13H
2
IE.2
TCON.2
Timer/Counter 1
1BH
3
IE.3
-
Serial Port
23H
4
IE.4
-
External Interrupt 2
33H
5
XICON.2
XICON.0
External Interrupt 3
3BH
6 (lowest)
XICON.6
XICON.3
-7-
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
Port 4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 ,
INT3 ).
Example:
P4
MOV
MOV
ORL
ANL
6.2
REG 0D8H
P4, #0AH
; Output data "A" through P4.0−P4.3.
A, P4
; Read P4 status to Accumulator.
P4,#00000001B ; Set bit P4.0
P4,#11111101B ; Clear bit P4.1
Reduce EMI Emission
Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which
is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78E51B allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may effect to external crystal operating improperly at high frequency above 24 MHz. The
value of R and C1, C2 may need adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
-
-
-
-
-
-
-
AO
POF
GF1
GF0
PD
IDL
AO: Turn off ALE output.
Power-off Flag
***PCON - Power control (87H)
-
-
-
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD:
Power down mode bit. Set it to enter power down mode.
IDL:
Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
-8-
W78E51B
6.3
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
3
2
1
0
ENW
CLRW
WIDL
-
-
PS2
PS1
PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0
PRESCALER SELECT
0
0
0
2
0
1
0
4
0
0
1
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
256
The time-out period is obtained using the following equation:
1
× 2 14 × PRESCALER × 1000 × 12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
-9-
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
ENW
WIDL
IDLE
EXTERNAL
RESET
OSC
PRESCALER
1/12
Watchdog Timer Block Diagram
14-BIT TIMER
INTERNAL
RESET
CLEAR
CLRW
Typical Watch-dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
0
0
0
0
1
1
1
1
6.4
0
1
0
1
0
0
1
1
WATCHDOG TIME-OUT PERIOD
0
0
1
1
0
1
0
1
19.66 mS
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Clock
The W78E51B is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78E51B relatively insensitive to duty
cycle variations in the clock. The W78E51B incorporates a built-in crystal oscillator. To make the
oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load
capacitor must be connected from each pin to ground. An external clock source should be connected
to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as
required by the crystal oscillator.
6.5
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
- 10 -
W78E51B
6.6
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E51B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
6.7
On-Chip ROM Characteristics
The W78E51B has several modes to program the on-chip Flash EPROM. All these operations are
configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15−A0(P2.7−P2.0,
P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these
operations.
6.7.1 Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
6.7.2
Output Disable Condition
When the OE is set to high, no data output appears on the D7..D0.
6.7.3 Program Operation
This operation is used to program the data to ROM and the security bits. Program operation is done
when the VPP is reach to VCP (12.5V) level, CE set to low, and OE set to high.
6.7.4 Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
6.7.5 Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the ROM
cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to VEP level,
CE set to low, and OE set to high.
6.7.6 Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if VPP = VEP (14.5V), CE is high and
OE is low.
- 11 -
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
6.7.7 Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6( CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So,
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
OPERATIONS
P3.0
P3.1
P3.2
P3.3
(A9
(A13
(A14
(OE
CTRL) CTRL) CTRL) CTRL)
P3.6
P3.7
EA
P2, P1
P0
(D7..D0)
( CE )
( OE )
(VPP)
(A15..A0)
Read
0
0
0
0
0
0
1
Address
Data Out
Output Disable
0
0
0
0
0
1
1
X
Hi-Z
Program
0
0
0
0
0
1
VCP
Address
Data In
Program
Verify
0
0
0
0
1
0
VCP
Address
Data Out
Erase
1
0
0
0
0
1
VEP
A0:0,
others: X
Data In
Erase Verify
1
0
0
0
1
0
VEP
Address
Data Out
Program/Erase
Inhibit
X
0
0
0
1
1
VCP/
VEP
X
X
0FFH
NOTE
@3
@4
@5
Notes:
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
7. SECURITY BITS
During the programmer operation mode, the Flash EPROM can be programmed and verified
repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The
protection of Flash EPROM and those operations on it are described below. The W78E51B has a
Special Setting Register, the Security Register, which can be accessed in normal mode. The register
can only be accessed from the Flash EPROM operation mode. Those bits of the Security Registers
can not be changed once they have been programmed from high to low. They can only be reset
through erase-all operation. The Security Register is addressed in the Flash EPROM operation mode
by address #0FFFFh.
- 12 -
W78E51B
D7 D6 D5 D4 D3 D2 D1 D0
B7
Reserved
4KB Flash EPROM
Security Bits
0000h
B2 B1 B0
Program Memory
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
0FFFh
Reserved
B7 : Osillator Control
logic 0 : 1/2 gain
logic 1 : Full gain
Default 1 for all security bits. Reserved bits must be kept in logic 1.
Security Register
0FFFFh
Special Setting Register
7.1
Lock Bit
This bit is used to protect the customer's program code in the W78E51B. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
on-chip ROM data and Special Setting Registers can not be accessed again.
7.2
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
7.3
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
+5V
+5V
VDD
A0 to A7
VIL
P1
VIL
P3.0
P3.1
VIL
VIL
VIL
P3.2
P3.3
P3.6
VIH
P3.7
X'tal1
P0
EA/Vpp
VDD
PGM DATA
A0 to A7
VIL
VCP
VIL
ALE
VIL
RST
VIH
PSEN
VIH
P2
P1
P3.0
P3.1
VCP
ALE
VIL
RST
VIH
VIH
VIL
P3.7
PSEN
VIH
X'tal1
X'tal2
X'tal2
Vss
Vss
Programming Configuration
PGM DATA
P3.2
P3.3
P3.6
VIL
VIL
A8 to A15
P0
EA/Vpp
P2
A8 to A15
Programming Verification
- 13 -
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
8. ELECREICAL CHARACTERISTICS
8.1
Absolute Maximum Ratings
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VDD−VSS
-0.3
+7.0
V
Input Voltage
VIN
VSS -0.3
VDD +0.3
V
Operating Temperature
TA
0
70
°C
Storage Temperature
TST
-55
+150
°C
DC Power Supply
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8.2
D.C. Characteristics
VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.
PARAMETER
SYMBOL
Operating Voltage
VDD
Operating Current
IDD
Idle Current
IIDLE
Power Down Current
Input Current
P1, P2, P3, P4
IIN1
Logical 1-to-0 Transition
Current P1, P2, P3(*1), P4
Input Current
RST
(*2)
Input Leakage Current
P0, EA
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
ALE, PSEN , P0
(*3)
Output High Voltage
P1, P2, P3, P4
Output High Voltage
ALE, PSEN , P0
IPWDN
(*3)
ITL
TEST CONDITIONS
SPECIFICATION
UNIT
MIN.
MAX.
4.5
5.5
V
No load VDD = 5.5V
-
20
mA
Idle mode VDD = 5.5V
-
6
mA
Power-down mode
VDD = 5.5V
-
50
μA
-50
+10
μA
-550
-
μA
VDD = 5.5V
VIN = 0V or VDD
VDD = 5.5V
VIN = 2.0V (*1)
IIN2
VDD = 5.5V
VIN = VDD
-10
+300
μA
ILK
VDD = 5.5V
0V < VIN < VDD
-10
+10
μA
VOL1
VDD = 4.5V
IOL1 = +2 mA
-
0.45
V
VOL2
VDD = 4.5V
IOL2 = +4 mA
-
0.45
V
2.4
-
V
2.4
-
V
VOH1
VOH2
VDD = 4.5V
IOH1 = -100 μA
VDD = 4.5V
IOH2 = -400 μA
- 14 -
W78E51B
DC Characteristics, continued
PARAMETER
Input Low Voltage
(Except RST)
Input Low Voltage
RST (*4)
Input Low Voltage
XTAL1 (*4)
Input High Voltage
(Except RST)
Sink Current
Input High Voltage
(*4)
Input High Voltage
XTAL1
(*4)
P0, ALE, PSEN
Source Current
P0, ALE, PSEN
MAX.
UNIT
0.8
V
VIL2
VDD = 4.5V
0
0.8
V
VIL3
VDD = 4.5V
0
0.8
V
VIH1
VDD = 4.5V
2.4
VDD +0.2
V
4
12
mA
VDD = 4.5V
Vs = 0.45V
VIH2
VDD = 4.5V
0.67
VDD
VDD +0.2
V
VIH3
VDD = 4.5V
0.67
VDD
VDD +0.2
V
8
16
mA
-100
-250
uA
-8
-14
mA
ISK2
Source Current
(*3)
MIN.
0
ISR1
P1, P2, P3, P4
SPECIFICATION
VDD = 4.5V
Sink Current
(*3)
TEST CONDITIONS
VIL1
ISK1
P1, P2, P3, P4
RST
SYMBOL
ISR2
VDD = 4.5V
Vs = 0.45V
VDD = 4.5V
VS = 2.4V
VDD = 4.5V
Vs = 2.4V
Notes:
*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when VIN is approximately 2V.
*2. RST pin has an internal pull-down resistor.
*3. P0, ALE, PSEN are in the external access memory mode.
*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.
8.3
A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
- 15 -
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
8.3.1
Clock Input Waveform
XTAL1
T CH
T CL
F OP,
PARAMETER
Operating Speed
Clock Period
Clock High
Clock Low
TCP
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
FOP
TCP
TCH
TCL
0
25
10
10
-
40
-
MHz
nS
nS
nS
1
2
3
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
8.3.2
Program Fetch Cycle
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
Address Hold from ALE Low
PARAMETER
SYMBOL
TAAS
TAAH
1 TCP -Δ
1 TCP -Δ
-
-
nS
nS
4
1, 4
ALE Low to PSEN Low
TAPL
1 TCP -Δ
-
-
nS
4
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
PSEN Pulse Width
TPDA
-
-
2 TCP
nS
2
TPDH
0
-
1 TCP
nS
3
TPDZ
TALW
TPSW
0
2 TCP
3 TCP
1 TCP
-
nS
nS
nS
4
4
2 TCP -Δ
3 TCP -Δ
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
8.3.3
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
TDAR
-
nS
1, 2
nS
1
RD Low to Data Valid
TDDA
3 TCP -Δ
-
-
3 TCP +Δ
4 TCP
Data Hold from RD High
TDDH
0
-
2 TCP
nS
Data Float from RD High
TDDZ
0
-
2 TCP
nS
RD Pulse Width
TDRD
6 TCP -Δ
6 TCP
-
nS
ALE Low to RD Low
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
- 16 -
2
W78E51B
8.3.4
Data Write Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
ALE Low to WR Low
TDAW
3 TCP -Δ
-
3 TCP +Δ
nS
Data Valid to WR Low
TDAD
1 TCP -Δ
-
-
nS
Data Hold from WR High
TDWD
1 TCP -Δ
-
-
nS
WR Pulse Width
TDWR
6 TCP -Δ
6 TCP
-
nS
Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.
8.3.5
Port Access Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Port Input Setup to ALE Low
TPDS
1 TCP
-
-
nS
Port Input Hold from ALE Low
TPDH
0
-
-
nS
Port Output to ALE
TPDA
1 TCP
-
-
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
8.3.6
Program Operation
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
VPP Setup Time
TVPS
2.0
-
-
μS
Data Setup Time
TDS
2.0
-
-
μS
Data Hold Time
TDH
2.0
-
-
μS
Address Setup Time
TAS
2.0
-
-
μS
Address Hold Time
TAH
0
-
-
μS
CE Program Pulse Width for Program
Operation
TPWP
290
300
310
μS
OECTRL Setup Time
TOCS
2.0
-
-
μS
OECTRL Hold Time
TOCH
2.0
-
-
μS
OE Setup Time
TOES
2.0
-
-
μS
OE High to Output Float
TDFP
0
-
130
nS
Data Valid from OE
TOEV
-
-
150
nS
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,
and the PSEN pin must pull in VIH status.
- 17 -
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
9. TIMING WAVEFORMS
9.1
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
T ALW
ALE
T APL
PSEN
T PSW
T AAS
PORT 2
T PDA
T AAH
T PDH, T PDZ
PORT 0
A0-A7
Code
9.2
Data
A0-A7
Code
A0-A7
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
T DAR
T DDA
RD
T DRD
- 18 -
T DDH, T DDZ
S6
S1
S2
S3
W78E51B
Timing Waveforms, continued
9.3
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
PORT 0
A0-A7
DATA OUT
WR
T DWR
T DAW
9.4
T DWD
TDAD
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
T PDA
T PDH
DATA OUT
PORT
INPUT
SAMPLE
- 19 -
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
Timing Waveforms, continued
9.5
Program Operation
Program
P2, P1 VIH
(A15... A0)
VIL
P3.6
VIH
(CE)
VIL
P3.3
(OECTRL)
VIH
VIH
(OE)
VIL
P0
(A7... A0)
VIH
VIL
Address Valid
Address Stable
TPWP
TAH
TOCS
TOCH
TOES
TDFP
TDH
D OUT
Data In
TDS
Vcp
TOEV
Vpp
VIH
Read Verify
TAS
VIL
P3.7
Program
Verify
TVPS
- 20 -
Data Out
W78E51B
10. TYPICAL APPLICATION CIRCUITS
10.1 Expanded External Program Memory and Crystal
VDD
VDD
31
19
10 u
R
EA
XTAL1
18
XTAL2
9
RST
12
13
14
15
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
CRYSTAL
8.2 K
C1
C2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
RD
WR
PSEN
ALE
TXD
RXD
17
16
29
30
11
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
3
4
7
8
13
14
17
18
1
11
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
OC
G
74373
A0 10
A1
9
A2
8
A3
7
A4
6
A5
5
A6
4
A7
3
A8 25
A9 24
A10 21
A11 23
A12 2
A13 26
A14 27
A15 1
GND
20
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CE
OE
27512
W78E51B
Figure A
CRYSTAL
C1
C2
R
16 MHz
30P
30P
-
24 MHz
15P
15P
-
33 MHz
10P
10P
6.8K
40 MHz
5P
5P
4.7K
Above table shows the reference values for crystal applications (full gain).
Note: C1, C2, R components refer to Figure A.
- 21 -
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
Typical Application Circuits, continued
10.2 Expanded External Data Memory and Oscillator
V DD
V DD
31
10 u
EA
19
XTAL1
18
XTAL2
9
RST
12
13
14
15
INT0
OSCILLATOR
8.2 K
1
2
3
4
5
6
7
8
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
RD
17
16
29
30
11
10
WR
PSEN
ALE
TXD
RXD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
11
OC
G
74373
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
GND
20
22
27
CE
OE
WR
20256
W78E51B
Figure B
- 22 -
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
W78E51B
11. PACKAGE DIMENSIONS
11.1 40-pin DIP
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
E1
eA
S
20
0.254
0.150
0.155
0.160
3.81
3.937
0.016
0.018
0.022
0.406
0.457
0.559
0.048
0.050
0.054
1.219
1.27
1.372
0.008
0.010
0.014
0.203
2.055
2.070
4.064
0.254
0.356
52.20
52.58
15.494
0.590
0.600
0.610 14.986
15.24
0.540
0.545
0.550
13.72
13.84
13.97
0.090
0.100
0.110
2.286
2.54
2.794
0.120
0.130
0.140
3.048
3.302
3.556
15
0
0.670
16.00
16.51
17.01
0
a
1
5.334
0.210
0.010
0.630
0.650
15
0.090
2.286
Notes:
E
S
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
. parting line.
are determined at the mold
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
c
A A2
A1
Base Plane
Seating Plane
L
B
e1
eA
a
B1
11.2 44-pin PLCC
HD
D
6
1
44
40
Symbol
7
39
E
17
HE
GE
29
18
28
c
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.185
4.699
0.508
0.020
3.81
3.937
0.66
0.711
0.813
0.406
0.457
0.559
0.145
0.150
0.155
0.026
0.028
0.032
0.016
0.018
0.022
0.008
0.010
0.014
0.203
0.254
0.356
0.648
0.653
0.658
16.46
16.59
16.71
0.648
0.653
0.658
16.46
16.59
16.71
0.050
BSC
3.683
1.27
BSC
16.00
0.590
0.610
0.630
14.99
15.49
0.590
0.610
0.630
14.99
15.49
16.00
0.680
0.690
0.700
17.27
17.53
17.78
0.680
0.690
0.700
17.27
17.53
17.78
0.090
0.100
0.110
2.296
2.54
2.794
0.004
0.10
L
Notes:
A2 A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
θ
e
b
b1
Seating Plane
A1
y
GD
- 23 -
Publication Release Date: Sep. 6, 2005
Revision A7
W78E51B
Package Dimensions, continued
11.3 44-pin PQFP
HD
D
Symbol
34
44
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
33
1
E HE
11
12
e
b
22
Dimension in inch
Dimension in mm
Min. Nom. Max.
Min. Nom.
---
---
---
0.002
0.01
0.02
0.05
0.25
0.5
0.075
0.081
0.087
1.90
2.05
2.20
0.01
0.014
0.018
0.25
0.35
0.45
0.004
0.006
0.010
0.101
0.152
0.254
0.390
0.394
0.398
9.9
10.00
10.1
0.390
0.394
0.398
9.9
10.00
10.1
0.031
0.036
0.635
0.80
0.952
0.510
0.520
0.530
12.95
13.2
13.45
13.45
0.510
0.520
0.530
12.95
13.2
0.025
0.031
0.037
0.65
0.8
0.95
0.051
0.063
0.075
1.295
1.6
1.905
0.08
0.003
0
7
0
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
A2 A
A1
Seating Plane
See Detail F
y
θ
L
L1
Detail F
- 24 -
---
0.025
Notes:
c
Max.
---
---
7
W78E51B
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A4
July, 2001
-
Formerly issued
A5
June, 2004
3
Revise part number in the item of packages
A6
April 20, 2005
25
Add Important Notice
A7
Sep. 6, 2005
3
Add lead free (RoHS) parts
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 25 -
Publication Release Date: Sep. 6, 2005
Revision A7