W78L33 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The W78L33 microcontroller supplies a wider frequency range and supply voltages than most 8-bit microcontrollers on the market. It is functional compatible with the industry standard 80C32 microcontroller series except the one extra 4-bit bit-addressable I/O port (Port 4). The W78L33 contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters and a serial port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256 bytes of RAM, and the device supports ROMless operation for application programs. The W78L33 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES • Fully static design 8-bit CMOS microcontroller • Supply voltage of 1.8V to 5.5V • DC-24 MHz operation • 256 bytes of on-chip scratchpad RAM • ROMless operation • 64K bytes program memory address space • 64K bytes data memory address space • Four 8-bit bidirectional ports • Three 16-bit timer/counters • One full duplex serial port • Boolean processor • Six-sources, two-level interrupt capability • Built-in power management • One extra 4-bit bit-addressable I/O port • Packages: − PLCC 44: W78L33P-24 − QFP 44: W78L33F-24 -1- Publication Release Date: September 1998 Revision A1 W78L33 PIN CONFIGURATIONS T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 44-Pin PLCC (W78L33P) P1.5 P1.6 P1.7 RST RXD, P3.0 P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 6 7 8 9 10 5 4 3 11 12 13 14 T 2 , P 1 . 0 A D 0 , P P 4 V 0 . D . 2 D 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X V P T S 4 A S . L 0 1 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 A D 2 , P 0 . 2 A D 3 , P 0 . 3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 44-Pin QFP (W78L33F) T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 P1.5 P1.6 P1.7 RST RXD, P3.0 P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 T 2 , P 1 . 0 A D 0 , P P V 0 4 . D . D 0 2 A D 1 , P 0 . 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 1 2 P 3 . 6 , / W R P 3 . 7 , / R D -2- X T A L 2 X V P P T S 4 2 A S . . L 0 0 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 W78L33 PIN DESCRIPTION P0.0−P0.7 Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. P1.0−P1.7 Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively. P2.0−P2.7 Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. P3.0−P3.7 Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions, which are described below: PIN ALTERNATE FUNCTION P3.0 RXD Serial Receive Data P3.1 TXD Serial Transmit Data P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 Input P3.5 T1 Timer 1 Input P3.6 WR Data Write Strobe P3.7 RD Data Read Strobe P4.0−P4.3 Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins. EA External Address Input, active low. This pin forces the processor to execute out of external ROM. This pin should be kept low for all W78L33 operations. RST Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor. -3- Publication Release Date: September 1998 Revision A1 W78L33 ALE Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high state during reset with a weak pull-up. PSEN Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a weak pull-up. XTAL1 Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1. VSS, VDD Power Supplies. These are the chip ground and positive supplies. BLOCK DIAGRAM P1.0 ~ P1.7 Port 1 Port 1 Latch ACC B INT2 Port 0 Interrupt INT3 T1 Latch T2 Timer 2 Port 0 P0.0 ~ P0.7 DPTR Timer 0 Stack Pointer PSW ALU Temp Reg. Timer 1 PC Incrementor UART Addr. Reg. P3.0 ~ P3.7 Port 3 Port 3 Instruction Decoder & Sequencer Latch SFR RAM Address 256 bytes RAM & SFR Port 2 Latch Bus & Clock Controller P4.0 ~ P4.3 Port 4 Port 4 Latch Watchdog Timer Oscillator XTAL1 XTAL2 ALE PSEN Reset Block RST -4- Power control VDD GND Port 2 P2.0 ~ P2.7 W78L33 FUNCTIONAL DESCRIPTION The W78L33 architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different instruction and references both a 64K program address space and a 64K data storage space. Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature of the W78L33: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. Clock The W78L33 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78L33 relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78L33 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts when VDD = 5V. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a reset. -5- Publication Release Date: September 1998 Revision A1 W78L33 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L33 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, Example: P4 MOV MOV SETB CLR REG 0D8H P4, #0AH A, P4 P4.0 P4.1 ; Output data "A" through P4.0−P4.3. ; Read P4 status to Accumulator. ; Set bit P4.0 ; Clear bit P4.1 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT VCC−VSS -0.3 +7.0 V Input Voltage VIN VSS -0.3 VCC +0.3 V Operating Temperature TA 0 70 °C Storage Temperature TST -55 +150 °C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS (VDD−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER SYM. SPECIFICATION MIN. MAX. UNIT TEST CONDITIONS Operating Voltage VDD 1.8 5.5 V Operating Current IDD - 20 mA No load, VDD = 5.5V, 20 MHz - 3 mA No load, VDD = 2.0V, 16 MHz - 6 mA VDD = 5.5V, Fosc = 20 MHz - 1.5 mA VDD = 2.0V, Fosc = 16 MHz - 50 µA VDD = 5.5V, Fosc = 20 MHz - 20 µA VDD = 2.0V, Fosc = 16 MHz Idle Current Power Down Current IIDLE IPWDN -6- W78L33 DC Characteristics, continued PARAMETER Input Current SYM. IIN1 SPECIFICATION MIN. MAX. -50 +10 UNIT µA P1, P2, P3,P4 Input Current IIN2 -10 µA +300 ILK -10 µA +10 ITL [*3] -500 µA - VIL1 VIL2 RST[*1] Input Low Voltage VIL3 XTAL1 [*3] Input High Voltage VIH1 P0, P1, P2, P3, P4, EA Input High Voltage VIH2 RST[*1] Input High Voltage VIH3 XTAL1 [*3] Output Low Voltage VOL1 P1, P2, P3, P4 Output Low Voltage VOL2 P0, ALE, PSEN [*2] Sink Current ISK1 P1, P2, P3, P4 Sink Current ISK2 P0, ALE, PSEN Output High Voltage P1, P2, P3, P4 VDD = 5.5V VIN = 2.0V P0, P1, P2, P3, P4, EA Input Low Voltage VDD = 5.5V 0V < VIN < VDD P1, P2, P3, P4 Input Low Voltage VDD = 5.5V 0 < VIN < VDD P0, EA Logic 1 to 0 Transition Current VDD = 5.5V VIN = 0V or VDD RST Input Leakage Current TEST CONDITIONS VOH1 0 0.8 V VDD = 4.5V 0 0.5 V VDD = 2.0V 0 0.8 V VDD = 4.5V 0 0.3 V VDD = 2.0V 0 0.8 V VDD = 4.5V 0 0.6 V VDD = 2.0V 2.4 VDD +0.2 V VDD = 5.5V 1.4 VDD +0.2 V VDD = 2.0V 3.5 VDD +0.2 V VDD = 5.5V 1.7 VDD +0.2 V VDD = 2.0V 3.5 VDD +0.2 V VDD = 5.5V 1.6 VDD +0.2 V VDD = 2.0V - 0.45 V VDD = 4.5V, IOL = +2 mA - 0.25 V VDD = 2.0V, IOL = +1 mA - 0.45 V VDD = 4.5V, IOL = +4 mA - 0.25 V VDD = 2.0V, IOL = +2 mA 4 9 mA VDD = 4.5V, Vin = 0.45V 1.8 5.4 mA VDD = 2.0V, Vin = 0.45V 8 16 mA VDD = 4.5V, Vin = 0.45V 4.5 9 mA VDD = 2.0V, Vin = 0.45V 2.4 - V VDD = 4.5V, IOH = -100 µA 1.4 - V VDD = 2.0V, IOH = -8 µA -7- Publication Release Date: September 1998 Revision A1 W78L33 DC Characteristics, continued PARAMETER Output High Voltage SYM. VOH2 P0, ALE, PSEN [*2] Source Current ISR1 P1, P2, P3, P4 Source Current ISR2 P0, ALE, PSEN SPECIFICATION UNIT TEST CONDITIONS MIN. MAX. 2.4 - V VDD = 4.5V, IOH = -400 µA 1.4 - V VDD = 2.0V, IOH = -200 µA -100 -250 µA VDD = 4.5V, Vin = 2.4V -12 -30 µA VDD = 2.0V, Vin = 1.4V -8 -16 mA VDD = 4.5V, Vin = 2.4V -1.4 -2.4 mA VDD = 2.0V, Vin = 1.4V Notes: *1. RST pin is a Schmitt trigger input. *2. P0, ALE and /PSEN are tested in the external access mode. *3. XTAL1 is a CMOS input. *4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. AC CHARACTERISTICS The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers. Clock Input Waveform XTAL1 T CH TCL F OP, PARAMETER TCP SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed FOP 0 - 24 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. -8- W78L33 Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP-∆ - - nS 4 Address Hold after ALE Low TAAH 1 TCP-∆ - - nS 1, 4 ALE Low to PSEN Low TAPL 1 TCP-∆ 1Tcp 1Tcp+∆ nS 4 PSEN Low to Data Valid TPDA - - 2 TCP nS 2 Data Hold after PSEN High TPDH 0 - 1 TCP nS 3 Data Float after PSEN High TPDZ 0 - 1 TCP nS ALE Pulse Width TALW 2 TCP-∆ 2 TCP - nS 4 PSEN Pulse Width TPSW 3 TCP-∆ 3 TCP - nS 4 TYP. - MAX. Notes: 1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "∆" ( due to buffer driving delay and wire loading) is 20 nS. Data Read Cycle PARAMETER SYMBOL TDAR MIN. UNIT nS NOTES 1, 2 nS 1 - 3 TCP+∆ 4 TCP 0 - 2 TCP nS TDDZ 0 - 2 TCP nS TDRD 6 TCP-∆ 6 TCP - nS SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP-∆ - 3 TCP+∆ nS Data Valid to WR Low TDAD 1 TCP-∆ - - nS Data Hold from WR High TDWD 1 TCP-∆ - - nS WR Pulse Width TDWR 6 TCP-∆ 6 TCP - nS RD Low to Data Valid TDDA 3 TCP-∆ - Data Hold after RD High TDDH Data Float after RD High RD Pulse Width ALE Low to RD Low 2 Notes: 1. Data memory access time is 8 TCP. 2. "∆" (due to buffer driving delay and wire loading) is 20 nS. Data Write Cycle PARAMETER Note: "∆" ( due to buffer driving delay and wire loading) is 20 nS. -9- Publication Release Date: September 1998 Revision A1 W78L33 Port Access Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. TIMING WAVEFORMS Program Fetch Cycle S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 T ALW ALE T APL PSEN T PSW T AAS PORT 2 T PDA T AAH T PDH, T PDZ PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 Data Read Cycle S4 S5 S6 S1 S2 S3 S4 S5 XTAL1 ALE PSEN PORT 2 A8-A15 A0-A7 DATA PORT 0 T DAR TDDA T DDH, T DDZ RD T DRD - 10 - S6 S1 S2 S3 W78L33 Timing Waveforms, continued Data Write Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 PORT 0 A8-A15 A0-A7 DATA OUT TDWD TDAD WR TDAW T DWR Port Access Cycle S5 S6 S1 XTAL1 ALE TPDS TPDH TPDA PORT DATA OUT INPUT SAMPLE - 11 - Publication Release Date: September 1998 Revision A1 W78L33 TYPICAL APPLICATION CIRCUIT Using External Program Memory and Crystal VDD 35 21 10 u R 20 XTAL2 10 RST 14 15 16 17 INT0 INT1 T0 T1 2 3 4 5 6 7 8 9 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 23 34 1 12 P4.0 P4.1 P4.2/INT3 P4.3/INT2 CRYSTAL 8.2 K C1 EA XTAL1 C2 W78L33P P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 43 42 41 40 39 38 37 36 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 24 25 26 27 28 29 30 31 RD WR PSEN ALE TXD RXD 19 18 32 33 13 11 A8 A9 A10 A11 A12 A13 A14 A15 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 7 8 13 14 17 18 GND 1 11 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 GND 20 22 CE OE A0 A1 A2 A3 A4 A5 A6 A7 OC G 74LS373 27512 44-pin PLCC Figure A CRYSTAL C1 C2 R 16 MHz 30P 30P - 24 MHz 15P 15P - 33 MHz 10P 10P 6.8K 40 MHz 5P 5P 4.7K Above table shows the reference values for crystal applications. Note: C1, C2, R components refer to Figure A. - 12 - O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 W78L33 PACKAGE DIMENSIONS 44-pin PLCC HD D 6 1 44 40 Symbol 7 39 E 17 HE GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.185 4.699 0.020 0.508 0.145 0.150 0.155 3.683 3.81 3.937 0.026 0.028 0.032 0.66 0.711 0.813 0.016 0.018 0.022 0.406 0.457 0.559 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 2.54 2.794 0.004 0.10 L Notes: A2 A 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. θ e b b1 Seating Plane A1 y GD 44-pin QFP HD Symbol 34 A A1 A2 b c D E e HD HE L L1 y θ 33 1 E HE 11 12 e Dimension in mm Dimension in inch D 44 b 22 Min. Nom. Max. Min. Nom. Max. --- --- --- --- 0.002 0.01 0.02 0.05 0.25 0.5 0.075 0.081 0.087 1.90 2.05 2.20 0.01 0.014 0.018 0.25 0.35 0.45 0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 0.025 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 0.510 0.520 0.530 12.95 13.2 13.45 0.025 0.031 0.037 0.65 0.8 0.95 0.051 0.063 0.075 1.295 1.6 1.905 --- 0.08 0.003 0 7 --- 0 7 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. c A2 A A1 Seating Plane See Detail F y θ L L1 Detail F - 13 - Publication Release Date: September 1998 Revision A1 W78L33 Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 14 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798