Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger 1 Introduction The last issue of this data sheet was May, 2002 (This document was previously labeled Advance Information.) A change history is included in 9 Change History on page 25. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically mentioned. If the reader displays this document in Acrobat Reader®, clicking on any blue entry in the text will bring the reader to that reference point. This document describes the hardware interfaces to the Agere Systems Inc. TSI-8 device. Information relevant to the use of the device in a board design is covered. Ball descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included. 1.1 Related Documents More information on the TSI-8 is contained in the following documents: TSI-8 Product Description TSI-8 Register Description TSI-8 Systems Design Guide 2 Description 2.1 Block Diagram and High-Level Interface Definition TEST PATTERN GENERATOR TEST PATTERN MONITOR TRANSLATION TABLE LOOKUP TEST ACCESS PORT 8K X 8K SWITCH FABRIC 32 RECEIVE CHI TRANSMIT CHI DATA STORE WRITE ADDRESS COUNTER CONNECTION STORE READ ADDRESS COUNTER MICROPROCESSOR INTERFACE CLOCK GENERATOR Figure 2-1. Block Diagram and High-Level Interface Definition 32 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 Table of Contents Contents Page 1 Introduction .............................................................. 1 1.1 Related Documents .......................................... 1 2 Description ............................................................... 1 2.1 Block Diagram and High-Level Interface Definition .......................................................... 1 3 Ball Information ........................................................ 3 3.1 Ball Diagram ..................................................... 3 3.2 Package Ball Assignments ............................... 4 3.3 Ball Types ......................................................... 8 3.4 Ball Definitions .................................................. 8 4 Absolute Maximum Ratings ................................... 11 4.1 Handling Precautions ..................................... 11 4.2 ESD Tolerance ............................................... 11 4.3 Package Thermal Characteristics ................... 11 4.4 Recommended Operating Conditions ............ 12 5 dc Electrical Characteristics .................................. 13 6 Timing Diagrams and ac Characteristics ............... 14 7 Outline Diagrams ................................................... 24 8 Ordering Information .............................................. 25 9 Change History ...................................................... 25 Figures Page Figure 2-1. Block Diagram and High-Level Interface Definition ................................................... 1 Figure 3-1. Package Diagram (Top View) ................... 3 Figure 6-1. CHICLK Timing Specifications ................ 14 Figure 6-2. MPUCLK Timing Specifications .............. 14 Figure 6-3. ac Timing Specification ........................... 15 Figure 6-4. CHI Interface Timing ............................... 15 Figure 6-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK... 16 Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK ............... 16 Figure 6-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK... 17 Figure 6-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK ............... 17 Figure 6-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK... 18 Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK ............... 18 Figure 6-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK... 19 Figure 6-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK ............... 19 2 Contents Page Figure 6-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK ..... 20 Figure 6-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK ................. 20 Figure 6-15. CHI 3-State Output Control ................... 21 Figure 6-16. Microprocessor Port Timing— Read Cycle............................................. 22 Figure 6-17. Microprocessor Port Timing— Write Cycle............................................. 23 Tables Page Table 3-1. Package Ball Assignments in Signal Name Order ........................................................... 4 Table 3-2. Package Ball Assignments in Ball Number Order (Top View) ......................................... 6 Table 3-3. Package Ball Assignments in Ball Number Order (Bottom View) (continued)................. 7 Table 3-4. Ball Types ................................................... 8 Table 3-5. Timing Port.................................................. 8 Table 3-6. Transmit and Receive Concentration Highways..................................................... 8 Table 3-7. Control Port................................................. 9 Table 3-8. Initialization and Test Access...................... 9 Table 3-9. Power Balls............................................... 10 Table 4-1. Absolute Maximum Ratings ...................... 11 Table 4-2. ESD Tolerance.......................................... 11 Table 4-3. Power Consumption ................................. 11 Table 4-4. Operating Conditions ................................ 12 Table 5-1. CMOS Inputs ............................................ 13 Table 5-2. CMOS Outputs ......................................... 13 Table 5-3. CMOS Bidirectionals (Excluding TXD[31:00]) ............................................... 13 Table 5-4. CMOS Bidirectionals (TXD[31:00]) ........... 13 Table 6-1. CHICLK Timing Specifications .................. 14 Table 6-2. MPUCLK Timing Specifications ................ 14 Table 6-3. CMOS Output ac Timing Specification * ... 15 Table 6-4. CHI Interface Timing ................................. 15 Table 6-5. CHI 3-State Output Control .......................21 Table 6-6. Microprocessor Port Timing— Read Cycle................................................ 22 Table 6-7. Microprocessor Port Timing— Write Cycle23 Table 8-1. Ordering Information................................. 25 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger 3 Ball Information 3.1 Ball Diagram The TSI-8 is housed in a 240-ball plastic ball grid array. Figure 3-1 shows the ball arrangement viewed from the top of the package. The balls are spaced on a 1.0 mm pitch. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A B C D E F G H J K L M N P R T U V Figure 3-1. Package Diagram (Top View) Agere Systems Inc. 3 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 3.2 Package Ball Assignments Table 3-1. Package Ball Assignments in Signal Name Order 4 Symbol Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball ADDR00 A17 DATA13 P18 RXD11 V7 TXD08 F1 VDD15 D13 ADDR01 A16 DATA14 P17 RXD12 T8 TXD09 G3 VDD15 D14 ADDR02 A15 DATA15 P16 RXD13 U8 TXD10 G2 VDD15 G4 ADDR03 A14 DT H17 RXD14 V8 TXD11 G1 VDD15 H4 ADDR04 A13 FSYNC T11 RXD15 U9 TXD12 H2 VDD15 L4 ADDR05 A12 HIZ R17 RXD16 V9 TXD13 H1 VDD15 M4 ADDR06 A11 INT H16 RXD17 V10 TXD14 J2 VDD15 R7 ADDR07 A10 MPUCLK K15 RXD18 U10 TXD15 J1 VDD15 R8 ADDR08 A9 PAR0 R18 RXD19 V11 TXD16 K1 VDD15 R11 ADDR09 A8 PAR1 P15 RXD20 U11 TXD17 K2 VDD15 R12 ADDR10 A7 R/W J17 RXD21 V12 TXD18 L1 VDD33 C9 ADDR11 A6 RESET H15 RXD22 U12 TXD19 L2 VDD33 C10 ADDR12 A5 RSV1 F17 RXD23 V13 TXD20 M1 VDD33 C17 ADDR13 A4 RSV2 F18 RXD24 U13 TXD21 M2 VDD33 D9 ADDR14 A3 RSV3 E15 RXD25 V14 TXD22 N1 VDD33 D10 ADDR15 A2 RSV4 E16 RXD26 U14 TXD23 N2 VDD33 E3 AS J16 RSV5 E17 RXD27 V15 TXD24 N3 VDD33 F3 CHICLK R16 RSV6 D17 RXD28 U15 TXD25 P1 VDD33 F15 CKSPD0 E18 RSV7 B18 RXD29 T15 TXD26 P2 VDD33 H3 CKSPD1 D16 RSV8 C18 RXD30 V16 TXD27 R1 VDD33 J3 CS J18 RSV9 D18 RXD31 U16 TXD28 R2 VDD33 K16 DATA00 K18 RSV10 T18 TCK G17 TXD29 T1 VDD33 P3 DATA01 K17 RSV11 V17 TDI G16 TXD30 T2 VDD33 R3 DATA02 L18 RXD00 V2 TDO G18 TXD31 U1 VDD33 T5 DATA03 L17 RXD01 U3 TMS G15 VDD15 C5 VDD33 T6 DATA04 L16 RXD02 V3 TRSTN H18 VDD15 C6 VDD33 T9 DATA05 M18 RXD03 U4 TXD00 B1 VDD15 C7 VDD33 T10 DATA06 M17 RXD04 V4 TXD01 C2 VDD15 C12 VDD33 T14 DATA07 M16 RXD05 U5 TXD02 C1 VDD15 C13 VDD33 T17 DATA08 M15 RXD06 V5 TXD03 D2 VDD15 C14 VDDPLL R14 DATA09 N18 RXD07 U6 TXD04 D1 VDD15 D5 VIO K3 DATA10 N17 RXD08 V6 TXD05 E2 VDD15 D6 VPRE T4 DATA11 N16 RXD09 T7 TXD06 E1 VDD15 D7 VSS A1 DATA12 N15 RXD10 U7 TXD07 F2 VDD15 D12 VSS A18 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger Table 3-1. Package Ball Assignments in Signal Name Order (continued) Symbol VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Agere Systems Inc. Ball B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C3 C4 Symbol VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball C8 C11 C15 C16 D3 D4 D8 D11 D15 E4 F4 F16 H8 H9 H10 H11 J4 J8 Symbol VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball J9 J10 J11 J15 K4 K8 K9 K10 K11 L3 L8 L9 L10 L11 L15 M3 N4 P4 Symbol VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSPLL Ball R4 R5 R6 R9 R10 R15 T3 T12 T13 T16 U2 U17 U18 V1 V18 R13 5 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 Table 3-2. Package Ball Assignments in Ball Number Order (Top View) (continued) 1 A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VSS ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR09 ADDR08 ADDR07 ADDR06 ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 ADDR00 B TXD00 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSV7 C TXD02 TXD01 VSS VSS VDD15 VDD15 VDD15 VSS VDD33 VDD33 VSS VDD15 VDD15 VDD15 VSS VSS VDD33 RSV8 D TXD04 TXD03 VSS VSS VDD15 VDD15 VDD15 VSS VDD33 VDD33 VSS VDD15 VDD15 VDD15 VSS CKSPD1 RSV6 RSV9 E TXD06 TXD05 VDD33 VSS — — — — — — — — — — RSV3 RSV4 RSV5 CKSPD0 F TXD08 TXD07 VDD33 VSS — — — — — — — — — — VDD33 VSS RSV1 RSV2 G TXD11 TXD10 TXD09 VDD15 — — — — — — — — — — TMS TDI TCK TDO H TXD13 TXD12 VDD33 VDD15 — — — VSS VSS VSS VSS — — — RESET INT DT TRSTN J TXD15 TXD14 VDD33 VSS — — — VSS VSS VSS VSS — — — VSS AS R/W CS K TXD16 TXD17 VIO VSS — — — VSS VSS VSS VSS — — — MPUCLK VDD33 DATA01 DATA00 L TXD18 TXD19 VSS VDD15 — — — VSS VSS VSS VSS — — — VSS DATA04 DATA03 DATA02 M TXD20 TXD21 VSS VDD15 — — — — — — — — — — DATA08 DATA07 DATA06 DATA05 N TXD22 TXD23 TXD24 VSS — — — — — — — — — — DATA12 DATA11 DATA10 DATA09 P TXD25 TXD26 VDD33 VSS — — — — — — — — — — PAR1 DATA15 DATA14 DATA13 R TXD27 TXD28 VDD33 VSS VSS VSS VDD15 VDD15 VSS VSS VDD15 VSS CHICLK HIZ PAR0 T TXD29 TXD30 VSS VPRE VDD33 VDD33 RXD09 RXD12 VDD33 VDD33 FSYNC VSS VSS VDD33 RXD29 VSS VDD33 RSV10 VSS RXD01 RXD03 RXD05 RXD07 RXD10 RXD13 RXD15 RXD18 RXD20 RXD22 RXD24 RXD26 RXD28 RXD31 VSS VSS RXD00 RXD02 RXD04 RXD06 RXD08 RXD11 RXD14 RXD16 RXD17 RXD19 RXD21 RXD23 RXD25 RXD27 RXD30 RSV11 VSS U TXD31 V 6 VSS VSS 18 VDD15 VSSPLL VDDPLL Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger Table 3-3. Package Ball Assignments in Ball Number Order (Bottom View) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 A VSS B RSV7 VSS VSS VSS VSS VSS VSS VSS C RSV8 VDD33 VSS VSS VDD15 VDD15 VDD15 VSS VDD33 VDD33 VSS D RSV9 RSV6 CKSPD1 VSS VDD15 VDD15 VDD15 VSS VDD33 VDD33 VSS E CKSPD0 RSV5 RSV4 RSV3 — — — — — — — — — F RSV2 RSV1 VSS VDD33 — — — — — — — — G TDO TCK TDI TMS — — — — — — — H TRSTN DT INT RESET — — — VSS VSS VSS J CS R/W AS VSS — — — VSS VSS K DATA00 DATA01 VDD33 MPUCLK — — — VSS L DATA02 DATA03 DATA04 VSS — — — M DATA05 DATA06 DATA07 DATA08 — — N DATA09 DATA10 DATA11 DATA12 — P DATA13 DATA14 DATA15 PAR1 — R PAR0 HIZ CHICLK VSS T RSV10 VDD33 VSS RXD29 VDD33 VSS U VSS VSS RXD31 RXD28 RXD26 RXD24 RXD22 RXD20 RXD18 RXD15 RXD13 RXD10 RXD07 RXD05 RXD03 RXD01 V VSS RSV11 RXD30 RXD27 RXD25 RXD23 RXD21 RXD19 RXD17 RXD16 RXD14 2 ADDR00 ADDR01 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 Agere Systems Inc. VSS VDD15 VDD15 VDD15 VSS VSS TXD01 TXD02 VDD15 VDD15 VDD15 VSS VSS TXD03 TXD04 — VSS VDD33 TXD05 TXD06 — — VSS VDD33 TXD07 TXD08 — — — VDD15 TXD09 TXD10 TXD11 VSS — — — VDD15 VDD33 TXD12 TXD13 VSS VSS — — — VSS VDD33 TXD14 TXD15 VSS VSS VSS — — — VSS VIO TXD17 TXD16 VSS VSS VSS VSS — — — VDD15 VSS TXD19 TXD18 — — — — — — — — VDD15 VSS TXD21 TXD20 — — — — — — — — — VSS TXD24 TXD23 TXD22 — — — — — — — — — VSS VDD33 TXD26 TXD25 VSS VSS VSS VSS VSS VDD33 TXD28 TXD27 VPRE VSS TXD30 TXD29 VSS VSS VSS VSS VDD15 VDD15 VSS VSS FSYNC VDD33 VDD33 RXD12 RXD09 VDD33 VDD33 RXD11 VSS VSS VSS VDDPLL VSSPLL VDD15 VDD15 VSS 1 VSS RXD08 RXD06 RXD04 RXD02 RXD00 TXD00 TXD31 VSS 7 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 3.3 Ball Types This table describes each type of input, output, and I/O ball used on the TSI-8. Table 3-4. Ball Types Type Label I Description CMOS input, TTL switching thresholds. I pd CMOS input, TTL switching thresholds with internal pull-down resistor. I pu CMOS input, TTL switching thresholds with internal pull-up resistor. O O od I/O None P CMOS output. Open drain output. Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output. Analog inputs for external resistors, capacitors, voltage references, etc. Power and ground. The dc switching and other electrical characteristics are specified later in this document. 3.4 Ball Definitions This section describes the function of each of the device balls. The balls are listed by ball name. Package ball numbers are listed in Table 3-1 of this document. The static parameters (drive currents, switching thresholds, etc.) for each ball type (input, output, etc.) are described in Table 5-1 through Table 5-4. Table 3-5. Timing Port Ball Name Type Name/Description FSYNC I Frame Synchronization. This signal indicates the beginning of a 125 µs frame event (8 kHz). The FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all concentration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative edge of CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection of FSYNC. CHICLK I Clock. This is the master synchronous clock for the transmit and receive concentration highways. The frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate. CKSPD0 I Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If CHICLK is connected to an 8.192 MHz source, CKSPD0 should be tied to VSS. If CHICLK is connected to a 16.384 MHz source, CKSPD0 should be tied to VDD33. CKSPD1 I pd Clock Speed. Reserved, leave disconnected. 20 kΩ pull-down resistor. Table 3-6. Transmit and Receive Concentration Highways Ball Name Type Name/Description RXD[31:00] I pd Receive Data [31:00]. Receive concentration highways. These are serial, synchronous data streams which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight contiguous bits. 20 kΩ pull-down resistor. TXD[31:00] I/O Transmit Data [31:00]. Normally these are output concentration highway data streams with data rate options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex ports such as H.110. Further information can be found in the system design guide. 20 kΩ resistor connected to VPRE. 8 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger Table 3-7. Control Port Ball Name Type Name/Description MPUCLK I Processor Clock. This clock is used to sample address, data, and control signals from the microprocessor. This clock must be within the range of 0 MHz—66 MHz. Required for operation. CS I Chip Select. Active-low chip select. This input is held low for the duration of any read or write access to the TSI-8. Required for operation. AS I Address Strobe. Active-low address strobe that is one MPUCLK cycle wide at the start of a microprocessor access cycle to the TSI-8. This is used to initiate a microprocessor access. Required for operation. R/W I Read/Write. Cycle selection. R/W is set high during a read cycle, or set low for a write cycle. Required for operation. ADDR[15:00] I pu Address [15:00]. ADDR[15] is the most significant bit and ADDR[00] is the least significant bit for addressing all the internal registers during microprocessor access cycles. All addresses are 16-bit word addresses; hence, in a typical application ADDR[00] of the TSI-8 device would be connected to address bit 1 of a byte addressable system address bus. Required for operation. 200 kΩ pull-up resistor. DATA[15:00] PAR[1:0] DT INT Note: The TSI-8 is little-endian; the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised in connection to microprocessors that use big-endian byte ordering. I/O Data [15:00]. Data bus for all transfers between the microprocessor and the internal registers. The balls are inputs during write cycles and outputs during read cycles. DATA[15] is the most significant bit, and DATA[00] is the least significant bit. Required for operation. I/O Control Port Parity [1:0]. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and PAR[0] is the parity for DATA[7:0]. The parity sense (even or odd) is application programmable via a register bit in the TSI-8. Not required for operation. O Data Transfer Acknowledge. Active-low for one MPUCLK cycle. Indicates that data has been written during write cycles or that data is valid during read cycles. High impedance when CS is a 1 and driven when CS is 0. Required for operation. O od Interrupt. This output is asserted low to indicate that an interrupt condition has occurred. This signal remains active-low until the interrupt status register has been cleared or masked. Table 3-8. Initialization and Test Access Ball Name Type Name/Description I pu Reset. Global reset, active-low. Initializes all internal registers to their default state. The reset occurs RESET asynchronously, but RESET should be held low for at least two CHICLK periods. 20 kΩ pull-up resistor. TCK I pu Test Clock. This signal provides timing for the boundary scan and test access port (TAP) controller. Should be static except during boundary-scan testing. 20 kΩ pull-up resistor. TDI I pu Test Data In. Data input for the boundary scan. Sampled on the rising edge of TCK. 20 kΩ pull-up resistor. TMS I pu Test Mode Select (Active-Low). Controls boundary-scan test operations. TMS is sampled on the rising edge of TCK. 20 kΩ pull-up resistor. TRSTN I pd Test Reset (Active-Low). This signal is an asynchronous reset for the TAP controller. 20 kΩ pull-down resistor. TDO O Test Data Out. Updated on the falling edge of TCK. The TDO output is high impedance except when scanning out test data. I pu Output Enable. All output and bidrectional buffers will be high impedance when this input is low unless HIZ boundary scan is enabled (TRSTN = 1). 20 kΩ pull-up resistor. RSV[11:1] — Reserved [11:1]. These balls are used by Agere Systems during the manufacturing process. They must be left unconnected. Agere Systems Inc. 9 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 Table 3-9. Power Balls Symbol Type Name/Description VDD33 P I/O Power. Power supply balls for the I/O pads (3.3 V ± 5%). VDD15 P Core Power. Power supply balls for the core (1.5 V ± 5%). VSS P Ground. Common ground balls for 3.3 V and 1.5 V supplies. VPRE P Precharge. Precharge voltage to support H.110 hot insertion on TXD[31:00]. If the device is used in an H.110 hot insertion applications, the signal should be connected to backplane early voltage; otherwise connect this signal to ground. VIO P PCI Buffer Voltage Select. For an H.110 application using TXD[31:00] in a 5 V signaling environment, connect this signal to 5 V. For an H.110 application using TXD[31:00] in a 3 V signaling environment, connect this signal to VDD33. For all other applications, connect this signal to VDD33. VDDPLL P PLL Power. 1.5 V power supply for the internal phase-locked loop. Must include local 0.01 µF capacitor to VSSPLL. VSSPLL P PLL Ground. Isolated ground for the internal phase-locked loop. 10 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger 4 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 4-1. Absolute Maximum Ratings Parameter Supply Voltage (VDD33) Supply Voltage (VDD15) Input Voltage: TXD[31:00] All Other Inputs Storage Temperature Junction Temperature Min –0.5 –0.5 Max 4.2 1.8 Unit V V –0.5 –0.3 –40 — 5.5 VDD33 + 0.3 125 125 V °C °C 4.1 Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC’s JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. 4.2 ESD Tolerance Table 4-2. ESD Tolerance Device TSI-8 Voltage 2,000 V 500 V Type HBM (human-body model) CDM (charged-device model) 4.3 Package Thermal Characteristics ΘJA = 24.0 °C/W. Table 4-3. Power Consumption Supply Voltage VDD33 VDD15 Typ* 100 mW at 3.3 V 275 mW at 1.5 V Max 150 mW at 3.47 V 325 mW at 1.6 V *MPUCLK = 66 MHz, CHICLK = 16.384 MHz, TA = 25 °C, all CHIs active, all outputs loaded with 50 pF. Agere Systems Inc. 11 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 4.4 Recommended Operating Conditions Recommended conditions apply unless otherwise specified. Table 4-4. Operating Conditions Parameter Supply Voltage (VDD33) Supply Voltage (VDD15) Ambient Temperature 12 Min 3.14 1.4 –40 Typ 3.3 1.5 — Max 3.47 1.6 85 Unit V V °C Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger 5 dc Electrical Characteristics This section describes the static parameters associated with all the ball types used in the TSI-8 device. Table 5-1. CMOS Inputs Parameter Input Leakage Current High-Input Voltage Low-Input Voltage Input Capacitance Symbol Conditions Min Typ Max Unit IIL VIH VIL CI VSS < VIN < VDD33 — — — — 2.0 –0.3 — — — — 2.5 1* VDD33 + 0.3 0.8 — µA V V pF * Excludes current due to pull-up or pull-down resistors. Table 5-2. CMOS Outputs Parameter Output Voltage Low Output Voltage High Output Current Low Output Current High Output Capacitance HIZ Output Leakage Current Symbol Conditions Min Typ Max Unit VOL VOH IOL IOH CO IOZ IOL = –10 mA IOL = 10 mA — — — — — 2.4 — — — — — — — — 3 — 0.4 — 10 10 — 10 V V mA mA pF µA Table 5-3. CMOS Bidirectionals (Excluding TXD[31:00]) Parameter Leakage Current High-Input Voltage Low-Input Voltage Biput Capacitance Output Voltage Low Output Voltage High Symbol Conditions Min Typ Max Unit IL VIH VIL CIB VOL VOH VSS < VIN < VDD33 — — — IOL = –10 mA IOL = 10 mA — 2.0 –0.3 — — 2.4 — — — 5.0 — — 11 VDD33 + 0.3 0.8 — 0.4 — µA V V pF V V Table 5-4. CMOS Bidirectionals (TXD[31:00]) Parameter Symbol Conditions Min Max Unit Leakage Current High-Input Voltage IL VIH VIL Biput Capacitance Output Voltage Low CIB VOL Output Voltage High VOH Positive-Going Threshold Negative-Going Threshold Hysteresis (Vt+ – Vt–) Vt+ Vt– VHYS — 2.0 0.5 VDD33 –0.5 –0.5 — — — 0.9 VDD33 2.4 1.2 0.6 0.4 10 5.5 VDD33 + 0.5 0.8 0.3 VDD33 10 0.1 VDD33 0.55 — — 2.0 1.6 — µA V Low-Input Voltage VSS < VIN < VDD33 VIO = 5.0 V VIO = 3.3 V VIO = 5.0 V VIO = 3.3 V — IOL = 1.5 mA, VIO = 3.3 V IOL = 6.0 mA, VIO = 5.0 V IOL = –0.5 mA, VIO = 3.3 V IOL = –2.0 mA, VIO = 5.0 V — — — Agere Systems Inc. V pF V V V V V 13 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 6 Timing Diagrams and ac Characteristics Figure 6-1 and Figure 6-2 describe the timing specifications for the input clocks on the TSI-8. t2 t1 t3 VDD33 VIH VIH 50% VIL VIL t4 Figure 6-1. CHICLK Timing Specifications Table 6-1. CHICLK Timing Specifications Parameter Description Min Typ Max Unit t1 CHICLK Rise Time — 2 7 ns t2 CHICLK Width (8.192 MHz)* 48.84 — 73.24 ns t2 CHICLK Width (16.384 MHz)* 24.42 — 36.62 ns t3 CHICLK Fall Time — 2 7 ns t4 CHICLK Period (8.192 MHz) — 122.07 — ns t4 CHICLK Period (16.384 MHz) — 61.03 — ns * VIH to VIH or VIL to VIL. t6 t7 t5 VDD33 VIH VIH 50% VIL VIL t8 Figure 6-2. MPUCLK Timing Specifications Table 6-2. MPUCLK Timing Specifications Parameter Description t5 MPUCLK Rise Time t6 MPUCLK Width* t7 MPUCLK Fall Time t8 MPUCLK Period Min Typ Max Unit — 2 7 ns 6.06 — — ns — 2 7 ns 15.2 — — ns * VIH to VIH or VIL to VIL. 14 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger Figure 6-3 shows the ac timing specifications for the CMOS outputs on the device. 80 % 80 % 20% 20 % t9 t10 Figure 6-3. ac Timing Specification Table 6-3. CMOS Output ac Timing Specification * Parameter Description Min Typ Max Unit t9 Rise Time (20%—80%) — 1.5 7 ns t10 Fall Time (80%—20%) — 1.5 7 ns * Test load = 50 pF (total). FSYNC t13 t14 t15 t16 CHICLK RXD t17 t19 t18 TXD Note: This figure assumes TSI-8 is programmed to sample FSYNC on rising edge of CHICLK. Figure 6-4. CHI Interface Timing Table 6-4. CHI Interface Timing Parameter Description Min Max Unit 10 — ns t13 FSYNC Setup Time to Active CHICLK Edge t14 FSYNC Hold Time from Active CHICLK Edge 5 — ns t15 RXD Setup to Active CHICLK Edge 10 — ns t16 RXD Hold Time from Active CHICLK Edge 5 — ns t17 TXD High Z to Data Valid — 15 ns t18 TXD Propagation Delay from Active CHICLK Edge 2 12 ns t19 Transmit Data High Impedance* — 15 ns * Applies if Driver_Enable_Control = 01. For Driver_Enable_Control = 11 refer to Figure 6-15 CHI 3-State Output Control on page 21. Agere Systems Inc. 15 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 All timing specifications also apply under the following conditions: If FS is active-low. If the falling edge of CHICLK is specified as the active edge. At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of 16.384 MHz or 8.192 MHz. FSYNC CHICLK w/ 0 offset TS255 B6 w/ ¼ bit offset TS255 B6 TS255 B5 w/ bit offset = 1 w/ 2¾ bit offset TS255 B3 TS255 B7 TS255 B6 TS255 B4 TS0 B2 TS0 B0 TS0 B1 data sampled TS255 B7 TS255 B6 TS255 B5 TS0 B0 TS0 B1 data sampled TS255 B7 TS255 B6 w/ ½ bit offset w/ ¾ bit offset TS255 B7 TS0 B2 TS0 B0 TS0 B1 data sampled TS0 B1 TS0 B5 TS0 B4 TS0 B3 TS0 B2 TS255 B6 TS255 B7 data sampled TS0 B4 TS0 B3 TS0 B2 TS0 B0 TS0 B1 data sampled TS255 B7 TS0 B0 data sampled TS255 B5 TS0 B3 TS0 B4 TS0 B3 TS0 B2 TS0 B0 TS0 B5 TS0 B5 TS0 B4 TS0 B5 TS0 B4 TS0 B3 TS0 B1 TS0 B2 TS0 B3 w/ bit offset = 7 TS254 B7 TS255 B0 TS255 B1 TS255 B2 data sampled TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7 TS0 B 0 TS0 B1 w/ TS offset = 1, bit offset = 0 TS254 B6 TS254 B7 TS255 B0 TS255 B1 data sampled TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7 TS0 B0 w/ TS offset = 13, bit offset = 3¼ w/ TS offset = 255, bit offset = 7¾ TS242 B3 TS255 B6 TS242 B4 TS255 B7 TS242 B5 TS242 B6 data sampled TS0 B0 TS242 B7 TS0 B1 TS0 B2 data sampled TS243 B0 TS0 B3 TS243 B1 TS0 B4 TS243 B2 TS0 B5 TS243 B3 TS0 B6 TS243 B4 TS0 B7 TS243 B5 TS1 B0 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK w/ 0 offset w/ ½ bit offset TS255 B5 TS255 B6 TS255 B5 TS255 B7 TS255 B6 TS0 B0 TS255 B7 TS0 B1 TS0 B0 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B4 TS0 B3 TS0 B5 TS0 B4 w/ bit offset = 1 TS255 B4 TS255 B5 TS255 B6 TS255 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 w/ TS offset = 1, bit offset = 0 TS254 B5 TS254 B6 TS254 B7 TS255 B0 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 w/ TS offset = 255, bit offset = 7½ TS255 B6 TS255 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5 Notes: 1/4 bit offset not valid with 16 Mbits/s data. For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and sampled by the rising edge of the CHICLK. Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK 16 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger FSYNC CHICLK w/ 0 offset TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled w/ ¼ bit offset TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled TS127 B7 w/ ½ bit offset TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ ¾ bit offset TS 127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ bit offset = 1 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 2¾ bit offset TS 127 B4 TS127 B5 TS127 B6 TS127 B7 TS0 B0 TS0 B1 data sampled w/ bit offset = 7 TS127 B0 TS127 B1 TS127 B2 TS127 B3 TS127 B4 TS127 B5 TS127 B1 TS127 B2 TS127 B3 TS127 B4 data sampled w/ TS offset = 1, bit offset = 0 TS126 B7 data sampled w/ TS offset = 13, bit offset = 3¼ w/ TS offset = 127, bit offset = 7¾ TS127 B0 TS114 B4 TS114 B5 TS114 B6 TS114 B7 TS115 B0 TS115 B1 data sampled TS 127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK w/ 0 offset w/ ¼ bit offset w/ ½ bit offset TS 127 B6 TS127 B7 TS127 B6 TS0 B0 TS127 B7 TS127 B6 TS0 B1 TS0 B0 TS127 B7 TS0 B2 TS0 B1 TS0 B0 TS0 B3 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B3 w/ bit offset = 1 TS 127 B5 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 w/ TS offset = 1, bit offset = 0 TS 126 B6 TS126 B7 TS127 B0 TS127 B1 TS127 B2 TS127 B3 w/ TS offset = 127, bit offset = 7¾ TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK Agere Systems Inc. 17 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 FSYNC CHICLK w/ 0 offset TS0 B0 TS0 B1 TS0 B2 data sampled w/ ¼ bit offset TS63 B7 TS0 B0 TS0 B1 TS0 B2 data sampled w/ ½ bit offset TS63 B7 TS0 B0 TS0 B1 TS0 B2 data sampled w/ ¾ bit offset TS63 B7 TS0 B0 TS0 B1 data sampled w/ bit offset = 1 TS63 B7 TS0 B0 TS0 B1 data sampled w/ 2¾ bit offset TS63 B5 TS63 B6 TS63 B7 data sampled w/ bit offset = 7 TS63 B1 TS63 B2 TS63 B3 TS63 B1 TS63 B2 data sampled w/ TS offset = 1, bit offset = 0 w/ TS offset = 13, bit offset = 3¼ TS63 B0 data sampled TS50 B4 TS50 B5 TS50 B6 TS50 B7 data sampled w/ TS offset = 63, bit offset = 7¾ TS0 B0 TS0 B1 TS0 B2 data sampled Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK w/ 0 offset TS63 B7 w/ ¼ bit offset w/ ½ bit offset TS0 B0 TS63 B7 TS63 B6 TS0 B1 TS0 B0 TS63 B7 TS0 B1 TS0 B0 TS0 B1 w/ bit offset = 1 TS63 B6 TS63 B7 TS0 B0 w/ TS offset = 1, bit offset = 0 TS62 B7 TS63 B0 TS63 B1 w/ TS offset = 63, bit offset = 7¾ TS63 B7 TS0 B0 TS0 B1 TS0 B2 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK 18 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger FSYNC CHICLK TS0 B0 w/ 0 offset TS0 B1 data sampled TS0 B0 w/ ¼ bit offset TS0 B1 data sampled w/ ½ bit offset TS31 B7 TS0 B0 TS0 B1 data sampled TS31 B7 w/ ¾ bit offset TS0 B0 TS0 data sampled w/ bit offset = 1 TS31 B7 TS0 B0 data sampled w/ 2¾ bit offset TS31 B5 TS31 B6 TS31 data sampled TS31 B1 w/ bit offset = 7 TS31 B2 data sampled w/ TS offset = 1, bit offset = 0 TS31 B0 TS31 B1 data sampled w/ TS offset = 13, bit offset = 3¼ TS18 B5 TS18 B6 data sampled w/ TS offset = 31, bit offset = 7¾ TS0 B0 TS0 B1 TS0 data sampled Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK TS31 B7 w/ 0 offset TS0 B0 TS31 B7 w/ ¼ bit offset TS0 B0 TS31 B7 w/ ½ bit offset TS0 B1 TS0 B0 w/ bit offset = 1 TS31 B6 TS31 B7 TS0 B0 w/ TS offset = 1, bit offset = 0 TS30 B7 TS31 B0 TS31 B01 w/ TS offset = 31, bit offset = 7¾ TS31 B7 TS0 B0 TS0 B1 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK Agere Systems Inc. 19 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 FSYNC CHICLK w/ 0 offset w/ ¼ bit offset TS127 B6 TS127 B6 w/ ½ bit offset w/ ¾ bit offset w/ bit offset = 1 w/ 2¾ bit offset TS127 B7 TS127 B7 TS127 B6 TS127 B5 TS127 B3 TS127 B4 TS127 B6 TS127 B7 data sampled TS0 B0 TS0 B5 TS0 B4 TS0 B3 TS0 B2 TS0 B5 TS0 B4 TS0 B3 TS0 B2 TS0 B1 TS0 B4 TS0 B3 TS0 B2 TS0 B0 TS0 B1 data sampled TS127 B7 TS0 B0 data sampled TS127 B5 TS0 B3 TS0 B2 TS0 B0 TS0 B1 data sampled TS127 B7 TS127 B6 TS0 B2 TS0 B0 TS0 B1 data sampled TS127 B7 TS127 B6 TS127 B5 TS0 B0 TS0 B1 data sampled TS0 B5 TS0 B4 TS0 B3 TS0 B1 TS0 B5 TS0 B4 TS0 B2 TS0 B3 w/ bit offset = 7 TS126 B7 TS127 B0 TS127 B1 TS127 B2 data sampled TS127 B3 TS127 B4 TS127 B5 TS127 B6 TS127 B7 TS0 B 0 TS0 B1 w/ TS offset = 1, bit offset = 0 TS126 B6 TS126 B7 TS127 B0 TS127 B1 data sampled TS127 B2 TS127 B3 TS127 B4 TS127 B5 TS127 B6 TS127 B7 TS0 B0 w/ TS offset = 13, bit offset = 3¼ w/ TS offset = 127, bit offset = 7¾ TS114 B3 TS127 B6 TS114 B4 TS127 B7 TS114 B5 TS114 B6 data sampled TS0 B0 TS114 B7 TS0 B1 TS0 B2 data sampled TS115 B0 TS0 B3 TS115 B1 TS0 B4 TS115 B2 TS0 B5 TS115 B3 TS0 B6 TS115 B4 TS0 B7 TS115 B5 TS1 B0 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK FSYNC CHICLK w/ 0 offset w/ ½ bit offset TS127 B5 TS127 B6 TS127 B5 TS127 B7 TS127 B6 TS0 B0 TS127 B7 TS0 B1 TS0 B0 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B4 TS0 B3 TS0 B5 TS0 B4 w/ bit offset = 1 TS127 B4 TS127 B5 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 w/ TS offset = 1, bit offset = 0 TS126 B5 TS126 B6 TS126 B7 TS127 B0 TS127 B1 TS127 B2 TS127 B3 TS127 B4 TS127 B5 w/ TS offset = 127, bit offset = 7½ TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5 Notes: 1/4 bit offset not valid with 8 MHz data and 8 MHz clock. For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 6-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK 20 Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger CHICLK 16.384 MHz t20 TXD 16.384 Mbits/s CHICLK 8.192 MHz t21 TXD 8.192 Mbits/s CHICLK 8.192 MHz t22 TXD 8.192 Mbits/s Figure 6-15. CHI 3-State Output Control Table 6-5. CHI 3-State Output Control Control in the table below refers to bits [6:4] in the Transmit_CHI_Global_Configuration register (0x0C84). This only applies if bits 13 and 12 of the corresponding Transmit_CHI_Control register (0x0C00—0x0C3E) are set to 11. See the TSI-8 Register Description document. Parameter Control t20 t21 t22 Reference Point* Min Max* Unit 000 After Previous Like Edge in 16 MHz 50 59 ns 001 After Previous Like Edge in 16 MHz 44 53 ns 010 After Previous Like Edge in 16 MHz 38 47 ns 011 After Previous Like Edge in 16 MHz 32 41 ns 000 After Previous Opposite Edge in 8 MHz 50 59 ns 001 After Previous Opposite Edge in 8 MHz 44 53 ns 010 After Previous Opposite Edge in 8 MHz 38 47 ns 011 After Previous Opposite Edge in 8 MHz 32 41 ns 100 After Previous Like Edge (8 MHz mode only) 111 120 ns 101 After Previous Like Edge (8 MHz mode only) 105 114 ns 110 After Previous Like Edge (8 MHz mode only) 99 108 ns 111 After Previous Like Edge (8 MHz mode only) 93 102 ns * Like edge is the reference edge (rising or falling) as defined by the Transmit_Clock_Edge bit in the Transmit_CHI_Global_Configuration (0x0C84) register. See the TSI-8 Register Description document for further details. Agere Systems Inc. 21 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 MPUCLK t23 t24 ADDR[15:00] t26 t25 CS t27 t28 AS t30 t29 R/W t31 t32 t33 DATA[15:00] PAR[1:0] t35 t35 t36 t34 DT Figure 6-16. Microprocessor Port Timing—Read Cycle Table 6-6. Microprocessor Port Timing—Read Cycle Parameter 22 Description Min Max Unit t23 Address Setup 5 — ns t24 Address Hold 1 — ns t25 Chip Select Setup 5 — ns t26 Chip Select Hold 1 — ns t27 Address Strobe Setup 5 — ns t28 Address Strobe Hold 1 — ns t29 R/W Setup 5 — ns t30 R/W Hold 1 — ns t31 Data Output Enable — 15 ns t32 Data Clock to Valid 1 7 ns t33 Data High-Impedance — 8 ns t34 DT High-Impedance to Valid 1 15 ns t35 DT Clock to Out 1 7 ns t36 DT Valid to High-Impedance 1 8 ns Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger MPUCLK t37 t38 ADDR[15:00] t40 t39 CS t41 AS t42 t44 t43 R/W t46 t45 DATA[15:00] PAR[1:0] DT t48 t48 t47 t49 Figure 6-17. Microprocessor Port Timing—Write Cycle Table 6-7. Microprocessor Port Timing—Write Cycle Parameter Description Min Max Unit t37 Address Setup 5 — ns t38 Address Hold 1 — ns t39 Chip Select Setup 5 — ns t40 Chip Select Hold 1 — ns t41 Address Strobe Setup 5 — ns t42 Address Strobe Hold 1 — ns t43 R/W Setup 5 — ns t44 R/W Hold 1 — ns t45 Data Setup 5 — ns t46 Data Hold 1 — ns t47 DT High-Impedance to Valid 1 15 ns t48 DT Clock to Out 1 7 ns t49 DT Valid to High-Impedance 1 8 ns Note: Posted writes follow the same timing shown in Figure 6-17 and Table 6-7. A posted write may return a DT prior to the device completing the write cycle. This allows the microprocessor to continue operation while the TSI-8 completes the write. Agere Systems Inc. 23 TSI-8 8K x 8K Time-Slot Interchanger Hardware Design Guide, Revision 1 November 2, 2005 7 Outline Diagrams Dimensions are in millimeters. TOP VIEW 19.00 SQUARE +0.70 17.70–0.05 SQUARE A1 INDICATOR (PLATED) 1.75 TYP. USE OF EJECTOR PINS IS OPTIONAL 4.00 x 45° APPROX TYP 4 CORNERS 1.20 x 45° APPROX TYP 3 PLACES 0.80 ± 0.050 0.50 R MAX ALL EDGES 30° APPROX ALL SIDES 0.35 Z 0.20 Z 0.10 0.56 ± 0.06 Z SEATING PLANE 1.86 ± 0.21 0.50 ± 0.10 18 17 16 15 14 13 12 11 A B C D E 1.00 TYP F G H J K L M N P R T U V 0.50 +0.07 0.63 –0.13 DIA BOTTOM VIEW 24 A1 INDICATOR (UNDER SOLDER MASK) 10 9 8 7 6 5 4 3 2 1 CENTER ARRAY FOR THERMAL ENHANCEMENT Agere Systems Inc. Hardware Design Guide, Revision 1 November 2, 2005 TSI-8 8K x 8K Time-Slot Interchanger 8 Ordering Information Table 8-1. Ordering Information Device Part Number Ball Count Package Comcode TSI-8 TTSI008321BL-2-DB L-TTSI008321BL-2-DB 240 PBGAM1 700046829 700078759* * Pb-free/RoHS. 9 Change History On page 1, updated Figure 2-1. On page 15, deleted 2 sentences at the beginning of the page. (All timing parameters are referenced to VIHmin and VILmax. The reference signal polarity may be inverted for some timing parameters.) On page 15, updated Figure 6-3, ac Timing Specification. On page 15, updated Table 6-3. CMOS Output ac Timing Specification * . On page 15, under Table 6-4 eliminated the following sentence: All timing specifications are with respect to VIHmin and VILmax as shown in Figure 5. On page 21, deleted footnote † under Table 6-5 and clarified the remaining footnote. On page 22, deleted the footnote under Table 6-6. On page 23, deleted the footnote under Table 6-7. On page 26, changed the part numbers. Adobe Acrobat and Acrobat Reader are registered trademarks of Adobe Systems Incorporated. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: Home: http://www.agere.com Sales: http://www.agere.com/sales E-MAIL: [email protected] N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen), (86) 10-65391096 (Beijing) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc. Copyright © 2005 Agere Systems Inc. All Rights Reserved November 2, 2005 DS02-122SWCH-1 (Replaces DS02-122SWCH)