MITSUBISHI <DIGITAL ASSP> ARY N I IM REL M66272FP tion. ange. ifica h spec t to c final bjec u a s t e r no a is his mits tric li ce: T Noti parame e m o S LCD CONTROLLER with VRAM • Displayable LCD • Binary display Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2 VGA) • 4 gray scale display Monochrome STN-LCD of up to 76800 dots(equivalent to 1/4 VGA) Reflective color STN-LCD of up to 76800 dots (equivalent to 1/4 VGA) • Interface with MPU • Capability of switching the interface with two-way 8/16-bit MPU • Provides WAIT output pin(WAIT output when access from MPU to VRAM is gained) • Capability of controlling BHE or LWR/HWR at the interface with a 16-bit MPU • Interface with LCD • LCD display data bus is a 4-bit or 8-bit parallel output. • 4 kinds of control signals: CP, LP, FLM and M • Display functions • Graphic display only • Binary or 4 gray scale display(gray scale palette is used to set pseudo medium 2 gray scale.) • Reflective color(ECB) uses a gray scale function. • Vertical scrolling is allowed within memory range. • Additional function for LCD module built-in system • Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU byte access is not allowed.) • Access from MPU to VRAM is gained via the I/O register. • 5V or 3V single power supply DESCRIPTION The M66272FP is a graphic display-only controller for dot matrix type STN-LCD which is used widely for OA equipment, PDA, amusement equipment, etc. It is capable of displaying six types of LCD by combining the panel configuration(single or dual scan), LCD display function(binary or gray scale), LCD display data bus width(4 or 8 bit). Equivalent to 640 x 240 Equivalent to 320 x 240 Equivalent to 320 x 240 x 2 screens Equivalent to 320 x 120 x 2 screens The M66272FP can support the reflective color type LCD (ECB : Electrically Controlled Birefringence). The IC has a built-in 19200-byte VRAM as a display data memory. All of the VRAM addresses are externally opened. Direct addressing of display data can be performed from MPU, thus display data processing such as drawing can be efficiently carried out. The built-in arbiter circuit(cycle steal system) which gives priority to display access allows timing-free access from MPU to VRAM, preventing display screen distortion. The IC provides has a function for LCD module built-in system by lessening connect pins between the MPU and the IC. FEATURES • Display memory • Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 320 x 240 dots x 2 screens) • All addresses of built-in VRAM are externally opened. 41 42 43 44 45 46 47 48 49 51 50 52 54 55 56 57 58 59 61 60 62 65 40 66 39 67 38 68 37 69 36 70 35 71 34 72 33 M66272FP 73 32 24 VSS N.C N.C N.C CSE CYCLE STEAL ENABLE VSS VDD SWAP BUS SWAP A<14> A<13> A<12> MPU ADDRESS A<11> BUS A<10> A<9> A<8> VSS VSS 23 22 21 20 19 18 17 16 15 11 10 9 MPU CLOCK MPUCLK VSS RESET RESET 8/16MPU SELECT MPUSEL VSS BUS HIGH ENABLE BHE A<0> A<1> A<2> A<3> MPU ADDRESS BUS A<4> A<5> A<6> A<7> VDD VSS IOCS HWR LWR RD MCS WAIT VDD 8 25 7 26 80 6 27 79 5 28 78 4 29 77 3 30 76 2 31 75 1 74 CONTROL REGISTER CHIP SELECT HIGH WRITE STROBE LOW WRITE STROBE READ STROBE VRAM CHIP SELECT WAIT Outline 80P6N-A • PPC/FAX operation panel, display/operation panel of other OA equipment, multifunction/public telephone • PDA/electronic notebook/information terminal, portable terminal • Game, Amusements, kid's computer etc. VSS VDD LCD ALTERNATING M SIGNAL LCDENB LCD CONTROL D<15> SIGNAL D<14> D<13> D<12> MPU DATA BUS D<11> D<10> D<9> D<8> VDD VSS D<7> D<6> D<5> D<4> MPU DATA BUS D<3> D<2> D<1> D<0> VDD VSS 63 64 PIN CONFIGURATION (TOP VIEW) VSS DISPLAY DATA TRANSFER CLOCK CP DISPLAY DATA LATCH PULSE LP FIRST LINE MARKER SIGNAL FLM VD<0> VD<1> VD<2> VD<3> LCD DISPLAY DATA BUS VD<4> VD<5> VD<6> VD<7> VDD N.C N.C VSS APPLICATION 14 Dual scan Displayable LCD size 53 Single scan Binary/ gray scale LCD display data 4bit Binary 8bit 4bit Gray scale 8bit Binary 4bit Gray scale 4bit 13 Panel configuration 12 P N.C : No Connection 1 MITSUBISHI <DIGITAL ASSP> ARY N I IM REL M66272FP tion. ange. ifica h spec t to c final bjec u a s t e r no a is his mits tric li ce: T Noti parame e m o S P LCD CONTROLLER with VRAM BLOCK DIAGRAM 1 VDD 8 23 34 42 52 63 77 – 15 ADDRESS BUFFER 61 CONTROL REGISTER 32 – 43 DATA BUFFER 50 53 – MPU DATA BUS D<15:0> 60 VRAM CONTROL REGISTER IOCS CHIP SELECT VRAM CHIP SELECT MCS HIGH WRITE STROBE HWR LOW W RITE STROBE LWR READ STROBE RD 8/16MPU SELECT MPUSEL RESET RESET BUS HIGH ENABLE BHE BUS SWAP SWAP MPU CLOCK MPUCLK WAIT WAIT CYCLE STEAL ENABLE CSE LCD DISPLAY TIMING CONTROL CIRCUIT 2 LCD DISPLAY DATA CONTROL CIRCUIT 19200byte 6 3 4 66 67 68 62 LCD CONTROL LCDENB SIGNAL DISPLAY DATA CP TRANSFER CLOCK DISPLAY DATA LATCH PULSE LINE MARKER FLM FIRST SIGNAL LCD ALTERNATING M SIGNAL LP 69 – 22 26 GRAY SCALE PATTERN TABLE A<14:0> – MPU ADDRESS BUS 76 VD<7:0> LCD DISPLAY DATA BUS MPU I/F CONTROL CIRCUIT 5 12 11 14 33 BUS ARBITER TIMIG CONTROL 9 7 36 (CYCLE STEAL CONTROL) CLOCK CONTROL (BASIC TIMING CONTROL) 1 10 13 24 25 35 40 41 51 64 65 80 37 38 39 78 79 VSS N.C BLOCK DIAGRAM 2 (When interfacing with the LCD module built-in system and having the maximum number of pins connected with MPU) INPUT FIXED PIN 3 6 11 12 14 15 26 32 33 VDD OPEN PIN 7 8 23 34 42 52 63 77 – ADDRESS BUFFER – 43 D<15:0> 50 53 – MPU DATA BUS 60 CONTROL REGISTER IOCS CHIP SELECT LOW WRITE STROBE READ STROBE 61 CONTROL REGISTER DATA BUFFER VRAM ADDRESS INDEX REGISTER DATA PORT REGISTER 2 VRAM LCD DISPLAY TIMING CONTROL CIRCUIT 4 RD 5 LCD DISPLAY DATA CONTROL CIRCUIT MPU I/F CONTROL CIRCUIT BUS ARBITER TIMIG CONTROL MPU CLOCK MPUCLK 9 CLOCK CONTROL (BASIC TIMING CONTROL) 1 10 13 24 25 35 40 41 51 64 65 80 VSS 2 67 68 62 19200byte LWR 66 36 37 38 39 78 79 N.C LCD CONTROL LCDENB SIGNAL DISPLAY DATA CP TRANSFER CLOCK DATA LATCH LP DISPLAY PULSE FIRST LINE FLM SIGNAL MARKER LCD ALTERNATING M SIGNAL 69 – 22 GRAY SCALE PATTERN TABLE 16 A<7:1> – MPU ADDRESS BUS VD<7:0> LCD DISPLAY DATA BUS 76 MITSUBISHI <DIGITAL ASSP> ARY N I IM REL M66272FP . ation hange. c ecific al sp bject to n fi u not a s are s is it is h m tric li ce: T Noti parame e Som P LCD CONTROLLER with VRAM PIN DESCRIPTIONS Item Input/ Pin name Output D<15:0> Input/ Output Number of pins MPU data bus When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to VDD or VSS. 16 15 A<14:0> Input MPU address bus When selecting 8-bit MPU, use A<14:0>. When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to internal VRAM can be gained. When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address is restricted. Use A<7:0> for selecting address of control register. IOCS Input Chip select input of control register When this pin is "L", select the internal control register. Assign to I/O space of MPU. 1 MCS Input Chip select input of VRAM When this pin is "L", select the internal VRAM. Assign to memory space of MPU. 1 HWR Input LWR Input RD MPU interface MPUSEL Input Input High-Write strobe input When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU controlled byte access by LWR and HWR. Low-Write strobe input When this pin is "L", write data to the internal control register or VRAM. Read strobe input When this pin is "L", read data from the internal control register or VRAM. 8/16-bit MPU select input According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU. 1 1 1 1 RESET Input Reset input Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and counters. 1 MPUCLK Input MPU clock Input system clock output from MPU. 1 BHE Input Bus-High-Enable input This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE. Connect to "VDD" to select 8-bit MPU. 1 Input Bus swap input When selecting 16-bit MPU, connect SWAP to “VSS” to transfer VD<n:0> in order of Upper/Lower byte of MPU data bus, reversally connect to “VDD” in order of Lower/Upper byte. When selecting 8-bit MPU, connect to “VSS”. Even if connecting to “VDD”, use D<7:0> to access to register of 8-bit width. 1 1 SWAP WAIT Output WAIT output for MPU This signal makes WAIT for MPU. Change WAIT to "L" at timing of falling edge of overlapping with MCS and RD or LWR and HWR. And return to "H" at synchronization with the rising edge of MPUCLK after internal processing. (Output WAIT only when requested access from MPU to VRAM is gained during cycle steal access.) CSE Output Cycle Steal Enable output State output of internal cycle steal access. 1 VD<7:0> Output Display data bus for LCD Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in parallel. The VD<n:0> output pin in use differs depending on the number of driven screens and the display mode. 8 CP Output Display data transfer clock Shift clock for the transfer of display data to LCD. Take the display data of VD<n:0> to LCD at falling edge of CP. 1 LP Output Display data latch pulse This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal. LP is output when it finishes transferring display data of a line. Latch of display data and the transfer of scanning signal at falling edge of LP. 1 FLM Output First Line Marker signal output Output the start pulse of scanning line. This signal is "H" active, the IC for driving scanning line catches FLM at falling edge of LP. 1 M Output LCD alternating signal output Signal for driving LCD by alternating current. 1 LCDENB Output LCD (ON/OFF) control signal output Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be used for controlling the LCD power supply, because LCDENB is set to "L" by RESET. 1 VDD Power supply pin 7 VSS Ground 12 N.C No connection LCD interface Others Function 5 3 MITSUBISHI <DIGITAL ASSP> ARY N I IM REL M66272FP . on. icati change pecif to nal s ubject fi a not are s his is ic limits tr ce: T Noti parame e Som P LCD CONTROLLER with VRAM OUTLINE M66272FP is a graphic display only controller for displaying a dot matrix type STN-LCD. • LCD display mode It is capable of displaying six types of LCD by combining the panel configuration, binary/gray scale, LCD display data bus width. Display mode Panel Binary/ LCD display configuration gray scale data 4bit 1 Binary 2 Single scan 3 Gray scale 8bit 4bit 8bit 4 5 Dual scan 6 Displayable LCD size Equivalent to 640 x 240 Equivalent to 320 x 240 Binary 4bit Equivalent to 320 x 240 x 2 screens Gray scale 4bit Equivalent to 320 x 240 x 2 screens • Control register When accessing the control register from MPU, use pins IOCS, LWR, RD, A<7:0> and D<7:0>. (However, use D<15:0> only when 16-bit MPU controls the LCD module built-in support function.) The IC contains the following registers as control registers. Operation control In accessing VRAM from MPU, output WAIT. Change WAIT to "L" at the timing of the falling edge of overlapping with MCS and RD or LWR / HWR, and return to "H" at synchronizing with rising edge of MPUCLK after internal processing. For the cycle steal system, this IC provides a cycle steal control function to improve data transfer efficiency in a line. This function gains access with the cycle steal system by taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On the other side, it does not output WAIT for keeping throughput of MPU during horizontal synchronous term (idle running term) with no necessity for the display data transfer from VRAM to LCD side. • Output to LCD side LCD display data VD<7:0> is output in parallel per 4 bits or 8 bits in synchronization with the rising edge of CP. Pin VD<n:0> differs depending on the display mode. Single scan R1 to R11 Supporting LCD module built-in type R12 to 14 or R15 to 16 4-bit transfer Dual scan 8-bit transfer R17 to R80 Gray scale pattern table • VRAM This IC has a built-in 19200-byte VRAM which is equivalent to two screens of 320 x 240 dots LCD. When accessing VRAM from MPU, use pins MCS, HWR, LWR, RD, BHE, A<14:0> and D<15:0>. Use of MPUSEL input can support both 8-bit MPU and 16-bit MPU. The VRAM address settable range is restricted depending on the panel configuration, as follows. VRAM address settable range ♦When single scan mode • A<14:0>=0000 to 4AFFH --- 19200 byte 0000H VRAM 4AFFH ♦When dual scan mode • For the 1st screen --- A<14:0>=0000 to 257F H --- 9600 byte • For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte 0000H VRAM for the 1st screen 257FH 2580H VRAM for the 2nd screen 4AFFH 4 • Cycle steal system Cycle steal system is interact method of transforming display data for LCD from VRAM and accessing VRAM from MPU on the basic cycle (MAINCLK) of internal operation. Basic timing is two clocks of MAINCLK, and assign first clock to the access from MPU to VRAM and second clock to the transfer of display data from VRAM to LCD. 4-bit transfer VD<7:4> VD<3:0> Display mode 1 3 VD<7:0> 2 4 VD<3:0> 5 6 When display data for a line has been sent, LP outputs data in synchronization with the falling edge of MAINCLK. The IC enables adjustment to an optimum value of the frame frequency as requested from the LCD PANEL side by adjusting pulse width of LP with the LPW register value. FLM is output when the display data for the first line has been sent. M output is an LCD alternating signal for driving LCD with alternating current. M output cycles can be set in lines with the M output cycle variable register and is available to prevent LCD from deterioration. • Gray scale display function Gray scale display can assign 2-bit VRAM data to a picture element of LCD display to show the display density at four levels. Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16 patterns x 2 medium gray scale), consisting of SRAM of 64 bytes in total, can set any gray scale display pattern. • Application to reflective color type LCD The above gradation display function is available to control about four display colors on the reflective color type LCD with ECB (Electrically Controlled Birefringence).