MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
DESCRIPTION
The M66273 is a graphic display-only controller for dot matrix type STNLCD which is used widely for OA equipment, PDA, amusement
equipment, etc.
The M66273 is an advanced product from the M66272 at the point of MPU
interface and timing specifications. This LCD display functions are the
same with the M66272.
It is capable of displaying six types of LCD by combining the panel
configuration(single or dual scan), LCD display function(binary or gray
scale), LCD display data bus width(4 or 8 bit).
Binary/
Panel
Displayable LCD size
configuration gray scale LCD display data
4bit
Binary
Equivalent to 640 x 240
8bit
Single scan
4bit
Gray scale
Equivalent to 320 x 240
8bit
4bit
Binary
Equivalent to 320 x 240 x 2 screens
Dual scan
Equivalent to 320 x 120 x 2 screens
Gray scale
4bit
The M66273 can support the reflective color type LCD (ECB : Electrically
Controlled Birefringence).
The IC has a built-in 19200-byte VRAM as a display data memory. All of
the VRAM addresses are externally opened. Direct addressing of display
data can be performed from MPU, thus display data processing such as
drawing can be efficiently carried out.
The built-in arbiter circuit(cycle steal system) which gives priority to
display access allows timing-free access from MPU to VRAM, preventing
display screen distortion.
The IC provides has a function for LCD module built-in system by
lessening connect pins between the MPU and the IC.
FEATURES
· Display memory
·Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 640 x 240 dots x 1
screen, 320 x 240 dots x 2 screens)
· All addresses of built-in VRAM are externally opened.
· Displayable LCD
· Binary display
Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2
VGA)
· 4 gray scale display
Monochrome STN-LCD of up to 76800 dots(equivalent to 1/4 VGA)
Reflective color STN-LCD of up to 76800 dots (equivalent to 1/4
VGA)
· Interface with MPU
· Capability of switching the interface with two-way 8/16-bit MPU
· Provides WAIT output pin(WAIT output when access from MPU to
VRAM is gained)
· Capability of controlling BHE or LWR/HWR at the interface with a
16-bit MPU
· Interface with LCD
· LCD display data bus is a 4-bit or 8-bit parallel output.
· 4 kinds of control signals: CP, LP, FLM and M
· Display functions
· Graphic display only
· Binary or 4 gray scale display(gray scale palette is used to set
pseudo medium 2 gray scale.)
· Reflective color(ECB) uses a gray scale function.
· Vertical scrolling is allowed within memory range.
· Additional function for LCD module built-in system
· Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU
byte access is not allowed.)
· Access from MPU to VRAM is gained via the I/O register.
· 5V or 3V single power supply
APPLICATION
PPC/FAX operation panel, display/operation panel of other OA
equipment, multifunction/public telephone
· PDA/electronic notebook/information terminal, portable terminal
· Game, Amusements, Kids computer, etc.
PIN CONFIGURATION
(TOP VIEW)
VSS
CP
DISPLAY DATA LATCH PULSE LP
65
40
66
39
67
38
FIRST LINE MARKER SIGNAL FLM
68
37
VD<0>
69
36
VD<1>
70
35
VD<2>
71
34
VD<3>
72
VD<4>
73
VD<5>
74
31
VD<6>
75
30
VD<7>
VDD
N.C
76
29
77
28
78
27
N.C
VSS
79
26
80
25
DISPLAY DATA TRANSFER CLOCK
LCD DISPLAY DATA BUS
Outline 80P6N-A
M66273FP
33
32
VS S
N.C
N.C
N.C
CYCLE STEAL
CSE
ENABLE
VS S
V DD
WAITCNT WAIT CONTROL
A<14>
A<13>
A<12>
A<11>
A<10>
A<9>
A<8>
VS S
MPU ADDRESS
BUS
N.C : No Connection
1
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
V DD
BLOCK DIAGRAM 1
8 23 34 42 52 63 77
15
MPU ADDRESS
BUS
A<14:0>
22
26
ADDRESS
BUFFER
CONTROL
REGISTER
32
LCD
DISPLAY
TIMING
CONTROL
CIRCUIT
43
MPU DATA BUS
D<15:0>
50
53
LCD CONTROL
SIGNAL
DISPLAY
DATA
66 CP
TRANSFER CLOCK
DISPLAY DATA
67 LP
LATCH PULSE
FIRST LINE MARKER
FLM
68
SIGNAL
LCD ALTERNATING
62 M
SIGNAL
61 LCDENB
DATA
BUFFER
60
VRAM
CONTROLREGISTER
IOCS
CHIP SELECT
2
VRAM CHIP SELECT MCS
6
HIGH WRITE STROBE HWR
LOW WRITE STROBE LWR
3
4
RD
READ STROBE
8/16MPU SELECT MPUSEL
12
RESET
11
BHE
BUS HIGH ENABLE
WAIT CONTROL WAITCNT
MPU CLOCK MPUCLK
WAIT
WAIT
CYCLE STEAL ENABLE CSE
14
RESET
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
19200byte
5
69
VD<7:0> LCD DISPLAY
DATA BUS
76
MPU I/F
CONTROL
CIRCUIT
33
BUS
ARBITER
TIMING
CONTROL
9
7
36
(CYCLE
STEAL
CONTROL)
CLOCK
CONTROL
(BASIC
TIMING
CONTROL)
1 10 13 24 25 35 40 41 51 64 65 80
37 38 39 78 79
VS S
N.C
BLOCK DIAGRAM 2 (When interfacing with the LCD module built-in system and having the maximum number of pins connected with MPU)
INPUT FIXED PIN
3 6 11 12 14 15
26
32 33
16
MPU ADDRESS
BUS
A<7:1>
22
D<15:0>
50
53
7 36
V DD
8 23 34 42 52 63 77
ADDRESS
BUFFER
DATA
BUFFER
LCD CONTROL
SIGNAL
DISPLAY DATA
66 CP
TRANSFER CLOCK
DISPLAY DATA
67 LP
LATCH PULSE
FIRST LINE MARKER
68 FLM
SIGNAL
LCD ALTERNATING
62 M
SIGNAL
61 LCDENB
CONTROL
REGISTER
43
MPU DATA BUS
OPEN PIN
LCD
DISPLAY
TIMING
CONTROL
CIRCUIT
VRAM
ADDRESS
INDEX
REGISTER
60
CONTROL REGISTER
CHIP SELECT
DATA
PORT
REGISTER
IOCS
VRAM
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
2
19200byte
LOW WRITE STROBE
READ STROBE
LWR
4
RD
5
MPU I/F
CONTROL
CIRCUIT
BUS
ARBITER
TIMING
CONTROL
MPU CLOCK
2
MPUCLK
9
CLOCK
CONTROL
(BASIC
TIMING
CONTROL)
1 10 13 24 25 35 40 41 51 64 65 80
37 38 39 78 79
VS S
N.C
69
76
VD<7:0> LCD DISPLAY
DATA BUS
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
PIN DESCRIPTIONS
Item
Input/
Pin name Output
D<15:0>
Function
MPU data bus
Input/
Output When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to "VDD" or "VSS ".
A<14:0>
Input
MPU address bus
When selecting 8-bit MPU, use A<14:0>.
When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to
internal VRAM can be gained.
When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address
is restricted. When IOCS control use A <7:0>, and MCS control use A <14:0> for selecting address of
control register.
IOCS
Input
Chip select input of control register
When this pin is "L", select the internal control register. Assign to I/O space of MPU.
Input
Chip select input of VRAM / control register
When this pin is "L", select the internal VRAM. Assign to memory space of MPU.
And this pin can for chip select of control register.
In detail, refer to "COMBINATIONS OF CONTROL INPUT PINS ON THE MPU INTERFACE" and "CONTROL
REGISTER".
MCS
HWR
Input
LWR
Input
RD
MPU
interface MPUSEL
Input
Input
RESET
Input
MPUCLK
Input
BHE
Input
WAITCNT Input
WAIT
Output
CSE
Output
High-Write strobe input
When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU
controlled byte access by LWR and HWR.
Low-Write strobe input
When this pin is "L", write data to the internal control register or VRAM.
Read strobe input
When this pin is "L", read data from the internal control register or VRAM.
8/16-bit MPU select input
According to MPU, set "VSS " for 8-bit MPU and set "VDD" for 16-bit MPU.
Reset input
Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and
counters.
MPU clock
Input system clock output from MPU.
Bus-High-Enable input
This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE.
Connect to "VDD" to select 8-bit MPU.
Wait control input
This pin is used for controlling WAIT output timing when requested access from MPU to VRAM.
Use this pin, when it is necessary to output WAIT earlier than the timing of falling edge of overlapping with
MCS and RD or LWR and HWR.
And then connect AS, ALE or etc of MPU.
Connect WAITCNT to "VDD" or "VSS", when it is necessary to output WAIT at the timing of falling edge of
overlapping with MCS and RD or LWR and HWR.
WAIT output for MPU
This signal makes WAIT for MPU. In case of fixed WAITCNT input("VSS " or "VDD" )change WAIT to
"L" at the timing of falling edge of overlapping with MCS and RD or LWR and HWR. And in case of
using WAITCNT input, change WAIT to "L" at timing of falling edge of WAITCNT on MCS = "L".
And WAIT output return to "H" at synchronization with the rising edge of MPUCLK after internal
processing. (Output WAIT only when requested access from MPU to VRAM is gained during cycle
steal access.)
Cycle Steal Enable output
State output of internal cycle steal access.
Number
of pins
16
15
1
1
1
1
1
1
1
1
1
1
1
1
3
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
PIN DESCRIPTIONS
Item
Pin name
Input/
Output
VD<7:0>
Output
Display data bus for LCD
Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in
parallel.
The VD<n:0> output pin in use differs depending on the number of driven screens and the display
mode.
CP
Output
Display data transfer clock
Shift clock for the transfer of display data to LCD.
Take the display data of VD<n:0> to LCD at falling edge of CP.
LP
Output
Display data latch pulse
This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal.
LP is output when it finishes transferring display data of a line.
Latch of display data and the transfer of scanning signal at falling edge of LP.
1
FLM
Output
First Line Marker signal output
Output the start pulse of scanning line.
This signal is "H" active, the IC for driving scanning line catches FLM at falling edge of LP.
1
M
Output
LCD
interface
LCDENB Output
Others
Number
of pins
Function
LCD alternating signal output
Signal for driving LCD by alternating current.
LCD (ON/OFF) control signal output
Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be used
for controlling the LCD power supply, because LCDENB is set to "L" by RESET.
8
1
1
1
VDD
Power supply pin
7
VSS
Ground
7
N.C
No connection
10
DIFFERENCE BETWEEN M66273FP AND M66272FP
The M66273FP is an adv anced product f rom the M66272FP at the point of MPU interf ace and timing
specif ications.
LCD display f unctions are the same with the M66272FP.
The f ollowing shows dif f erence between the M66273FP and the M66272FP without timing specif ications.
Ref er to the later item about timing specif ications and detail specif ications.
Specif ication
M66273FP
M66272FP
Pin f unction
WAITCNT input ( WAIT control input)
SWAP input ( Bus swap input)
WAIT output
control
It is capable of selecting WAIT output trigger input.
WAIT output change to "L" at the timing of the falling
In case of fixed WAITCNT input, change WAIT to "L" at the
edge of overlapping with MCS and RD or LWR/HWR.
timing of the falling edge of overlapping with MCS and RD or
LWR/HWR, and in case of using WAITCNT input, change
WAIT to "L" at the timing of the falling edge of WAITCNT on
MCS="L".
Access to
control register
Use IOCS or MCS pins for chip select of
control register.
(capable of controlling VRAM and control register by MCS
pin.)
Bus swap f unction Set by SWAP register.
4
Use IOCS pin for chip select of control register.
Set by SWAP pin.
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
OUTLINE
The M66273 is a graphic display only controller for displaying a dot
matrix type STN-LCD.
· LCD display mode
It is capable of displaying six types of LCD by combining the panel
configuration, binary/gray scale, LCD display data bus width.
LCD display
Display Panel
Binary/
configuration gray scale data
mode
1
Displayable LCD
size
4bit
Equivalent to 640
x 240
Binary
2
8bit
Single
scan
3
Gray scale
4
4bit
Equivalent to 320
x 240
8bit
5
Dual
scan
6
Binary
4bit
Gray scale
4bit
Equivalent to 320 x
240 x 2 screens
Equivalent to 320 x
120 x 2 screens
· Control register
When accessing the control register from MPU, use pins IOCS,
LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD,A<14:0> and
D<7:0> (However, use D<15:0> only when 16-bit MPU controls the
LCD module built-in support function.)
Refer to Table-1, setting of control input.
The IC contains the following registers as control registers.
Operation control
R1 to R11
· Cycle steal system
Cycle steal system is interact method of transforming display data for
LCD from VRAM and accessing VRAM from MPU on the basic
cycle (MAINCLK) of internal operation.
Basic timing is two clocks of MAINCLK, and assign first clock to the
access from MPU to VRAM and second clock to the transfer of
display data from VRAM to LCD.
In accessing VRAM from MPU, output WAIT. In case of fixed
WAITCNT input, change WAIT to "L" at the timing of the falling edge
of overlapping with MCS and RD or LWR / HWR,and in case of
using WAITCNT input, change WAIT to "L" at the timing of the falling
edge of WAITCNT on MCS="L", And return to "H" at synchronizing
with rising edge of M PUCLK after internal processing.
For the cycle steal system, this IC provides a cycle steal control
function to improve data transfer efficiency in a line. This func-tion
gains access with the cycle steal system by taking WAIT for MPU
during the display term with necessity for the display data transfer
from built-in VRAM to LCD. On the other side, it does not output
WAIT for keeping throughput of MPU during horizontal synchronous
term (idle running term) with no necessity for the display data
transfer from VRAM to LCD side.
In detail,refer to "Description of cycle steal".
· Output to LCD side
LCD display data VD<7:0> is output in parallel per 4 bits or 8 bits in
synchronization with the rising edge of CP.
Pin VD<n:0> differs depending on the display mode.
Supporting LCD module built-in type R12 to 14 or R15 to 16
Gray scale pattern table
4-bit transfer
· VRAM
This IC has a built-in 19200-byte VRAM which is equivalent to two
screens of 320 x 240 dots LCD.
When accessing VRAM from MPU, use pins MCS, HWR, LWR,
RD, BHE, A<14:0> and D<15:0>.
Use of MPUSEL input can support both 8/16 bit MPU.
Refer to table-2 to 6, VRAM specifications for 8/16 bit MPU and input
setting in access.
The VRAM address settable range is restricted depending on the
panel configuration, as follows.
VRAM address settable range
· When single scan mode
·A<14:0>=0000 to 4AFFH --- 19200 byte
0000H
VRAM
4AFFH
· When dual scan mode
·For the 1st screen --- A<14:0>=0000 to 257F H --- 9600 byte
·For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte
0000H
VRAM for the 1st screen
257FH
Dual scan
Single scan
R17 to R80
8-bit transfer
4-bit transfer
VD<7:4>
VD<3:0>
VD<7:0>
1
2
Display mode
3
4
VD<3:0>
5
6
When display data for a line has been sent, LP outputs data in
synchronization with the falling edge of MAINCLK.
The IC enables adjustment to an optimum value of the frame
frequency as requested from the LCD PANEL side by adjusting pulse
width of LP with the LPW register value.
FLM is output when the display data for the first line has been sent.
M output is an LCD alternating signal for driving LCD with alternating
current.
M output cycles can be set in lines with the M output cycle variable
register and is available to prevent LCD from deterioration.
· Gray scale display function
Gray scale display can assign 2-bit VRAM data to a picture element
of LCD display to show the display density at four levels.
Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16 patterns x
2 medium gray scale), consisting of SRAM of 64 bytes in total, can
set any gray scale display pattern.
In detail,refer to "Description of gray scale function".
· Application to reflective color type LCD
The above gradation display function is available to control about four
display colors on the reflective color type LCD with ECB (Electrically
Controlled Birefringence).
2580H
VRAM for the 2nd screen
4AFFH
5
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
COMBINATIONS OF CONTROL INPUT PINS ON THE MPU INTERFACE
Tables 1 to 6 show input setting conditions for access to the control register and VRAM from the MPU side.
(1) Access to the control register
For data, D<7:0> is used.
(Only when 16bit MPU is used to control the LCD module built-in system, D<15:0> is used for data.)
Table-1
IOCS MCS LWR RD
L
L
H
H
H
H
H
L
L
H
L
H
L
H
X
H
L
H
L
X
A<14:0>
Operation
0000H to 009EH
0000H to 009EH
5000H to 509EH
5000H to 509EH
IOCS
control
MCS
control
Writes to control register
Reads from control register
Writes to control register
Reads from control register
Invalid
(2) Write to VRAM
(2-1) For use of 8bit MPU (Set as follow: MPUSEL="L", BHE=HWR="H")
Table-2
MPU
SEL MCS BHE A<0> HWR LWR Odd address Even address
L
L
H
H
L
H
X
X
H
L
H
X
Invalid
Write
Write
Invalid
Invalid
Invalid
Valid data bus width
for MPU
8bit
(2-2) For use of 16bit MPU - 1 (For MPU controlling byte access with A<0> and BHE, set as follow: MPUSEL=HWR="H")
Table-3
MPU
SEL MCS BHE A<0> HWR LWR
H
L
L
L
H
L
H
L
H
L
H
L
H
X
H
L
H
H
H
X
X
Upper byte
Lower byte
Write
Invalid
Write
Invalid
Invalid
Write
Invalid
Invalid
Invalid
Write
Invalid
Invalid
Valid data bus width
for MPU
16bit
Upper 8bit
Lower 8bit
(2-3) For use of 16bit MPU - 2 (For MPU controlling byte access with LWR and HWR, set as follow: MPUSEL=BHE="H", A<0>="L")
Table-4
MPU
SEL MCS BHE A<0> HWR LWR
H
L
H
L
L
H
H
X
Upper byte
Lower byte
Valid data bus width
for MPU
L
H
Write
Write
Write
Invalid
16bit
Upper 8bit
L
Invalid
Write
Lower 8bit
H
X
Invalid
Invalid
(3) Read from VRAM
(3-1) For use of 8bit MPU (Set as follows: MPUSEL="L", BHE="H")
Table-5
MPU
SEL MCS BHE A<0>
L
L
H
L
H
X
H
RD
Odd address Even address
L
Invalid
Read
Read
Invalid
Invalid
Invalid
RD
Upper byte
Lower byte
L
H
X
Read
Read
Invalid
Invalid
H
X
Valid data bus width
for MPU
8bit
(3-2) For use of 16bit MPU (Set as follow: MPUSEL="H")
Table-6
MPU
SEL MCS BHE A<0>
H
L
H
X
X
Valid data bus width
for MPU
16bit
Notes : Combinations except for the above cause malfunction. Be sure to make settings according to the above combinations.
: X=either " L " or " H"
6
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
CONTROL REGISTER
M66273 is equipped with 80 types of built-in control registers.
For operation control
Only for LCD module built-in system
For gradation pattern table
IOCS, LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD, A<14:0>
and D<7:0> are used for setting from the MPU to control register.
And for address in IOCS control,use A<7:0>=00H to 9EH,and in MCS
control, use A<14:0>=5000H to 509EH.
(However, D<15:0> is to be used only when registers R15 and R16
only for LCD module built-in system are used.)
R1 to R11
R12 to R14, or R15 to R17
R17 to R80
(1) Types of control registers
· List of registers for operation control
Types of register
No.
R1
R2
R3
R4
R5
R6
R7
Name
Basic operation mode
LCD output mode
Number of horizontal display characters
Horizontal synchronous pulse width
Cycle steal enable width
Number of vertical lines
1st screen display start address
R8
R9
2nd screen display start address
R10
R11 M output frequency variable
Address Address
Data
(ICOS control)(MCS control)
A<7:0>
00H
02H
04H
06H
08H
0AH
D6
D5
D4
D3
A<14:0> D7
DIV
5000H RESET IDXON
WAITCSWAP
5002H
CR
5004H
LPW
5006H
CSW
5008H
SLT
500AH
0C H
500C H
SA1L
0EH
500EH
SA1H
10H
5010H
SA2L
12H
14H
5012H
5014H
SA2H
MT
D2
D1
D0
DISP
REV
LCDE
DUAL GRAY
4/8
R/W
Reset
R/W
R/W
W
00H
00H
28H
04H
02H
78H
W
W
W
D0
0
R/W
00H
00H
D0
0
R/W
W
80H
25H
00H
· List of registers only for LCD module built-in type support function
(For 8bit MPU only)
R12
VRAM address index
R13
R14 Data port
16H
18H
1AH
IDX8L
IDX8H
DP8
5016H
5018H
501AH
R/W
00H
00H
R/W
Undetermined
R/W
Reset
(For 16bit MPU only)
Types of register
No.
Name
Address Address
Data
(ICOS control)(ICOS control)
A<7:0>
D0
A<14:0> D15
D14
R15 VRAM address index
1C H
501C H
R16 Data port
1EH
501EH
D1
IDX16
D15
D0
0
D0
DP16
R/W
0000H
R/W
Undetermined
R/W
Reset
R/W
Undetermined
R/W
Undetermined
· List of registers for gray scale pattern table
Types of register
No.
R17
R18
to
R47
R48
R49
R50
to
Name
Gray scale pattern 0-1
Gray scale pattern 0-2
to
Gray scale pattern 0-31
Gray scale pattern 0-32
Gray scale pattern 1-1
Gray scale pattern 1-2
to
R79 Gray scale pattern 1-31
R80 Gray scale pattern 1-32
Address Address
Data
(ICOS control)( I C O S c o n t r o l 9
A<7:0>
20H
22H
to
5C H
5EH
60H
62H
to
9C H
9EH
A<14:0>
5020H
5022H
to
505C H
505EH
5060H
5062H
to
509C H
509EH
D7
D6
D5
D4
D3
D2
D1
FRC0-1-2
FRC0-1-1
FRC0-1-4
FRC0-1-3
to
to
FRC0-16-2
FRC0-16-1
FRC0-16-4
FRC0-16-3
FRC1-1-2
FRC1-1-1
FRC1-1-4
FRC1-1-3
to
to
FRC1-16-2
FRC1-16-1
FRC1-16-4
FRC1-16-3
D0
7
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(2) Description of registers
Address is listed for ICOS control. Incase of MCS control,set to address adding 50H to upper 7 bit (50**H).
[R1] Basic operation mode
Set the Basic operation mode
Function
Address R/W
·Software reset.
D7
Reset OFF
1
Reset ON
D6
Index mode OFF
1
Index mode ON
DIV
D4 D3
0
0
0
1
1
0
1
1
0
0
Reset
0
·Set to decide whether or not the function only for LCD
module built-in system is used.
·Set Index mode OFF for reset.
Division of
MPUCLK input
1
1/2 division
1/4 division
1/8 division
1/16 division
·Set the division of MPUCLK input to set the
reference clock cycle (MAINCLK) for internal
operation.
·Resetting does not divide MPUCLK.
0
·Don't set except for the
settings in the table at
left.
000
R/W
D2
DISP
0
Display OFF
1
Display ON
D1
REV
0
Normal display
1
Reverse display
D0
8
IDXON
0
D5
0
0
0
0
1
00H
RESET
0
Restriction
·Surely return to reset
off after reset on.
And then, can't set
another bits (D6 to
D0) at the same time.
LCDE
0
LCDENB="0"output
1
LCDENB="1"output
·Control display ON/OFF of LCD.
·In the reverse mode with REV (D1) set to "1", "1" is output to
display data VD<n:0> with DISP="0".
·Reset sets display OFF.
·Controls normal/reverse of LCD display.
·Resetting sets normal display.
0
0
·Sets the data output from the LCDENB output pin.
·Resetting outputs "0" (Vss potential) to the LCDENB output pin.
·This function is prepared for controlling the apply voltage to LCD.
When the power supply is turned ON after registers have been
completely set, set this LCDE to "1" to apply the LCD voltage.
Conversely for turning OFF the power supply to the system, set
the LCDE to "0" to turn OFF the LCD voltage.
This prevents abnormal DC voltage from being applied to the
LCD.
This function depends on the LCD functions.
Use the function, if necessary.
0
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R2] MPUI/LCD mode
Set the display data output mode on the LCD side.
Address R/W
Function
D7 , D6 are not used.
D5
WAITC
MCS and RD or H/LWR
0 control
1 WAITCNT control
D4
02H
R/W
SWAP
0 Order of upper/lower byte
1 Order of lower/upper byte
DUAL
0 1 screen driving panel
Reset
0
·Set to select trigger signal of WAIT output.
·When setting WAITC to "0", change WAIT to "L" at timing of
falling edge of overlapping with MCS and RD or LWR and
HWR. And return to "H" at synchronization with the rising
edge of MPUCLK offer internal processing.
·When setting WAITC to "T", change WAIT to "L" at timing of
falling edge of WAITCNT on MCS="L".And return to "H" at
synchronization with rising edge of MPUCLK after internal
processing.
·Output WAIT only when requested access from MPU to
VRAM is gained during cycle steal access.
·Resetting set WAITC ="0".
·set when register is
initialized.
·When setting to
"0",connect
WAITCNT input to
VSS or VDD.
·When selecting 16 bit MPU, set SWAP to "0" to transfer
VD<n:0> in order of Upper/Lower byte of MPU data
bus,reversally set to "1" in order of Lower/Upper byte.
·When selecting 8 bit MPU, set to "0"
·Even if setting to "1", use D<7:0> to access to register of
8 bit width.
·Resetting set SWAP="0".
·set when register is
initialized.
0
0
·To read R2, "0" is output to D3.
D3 is not used.
D2
Restriction
·To read R2, "0" is output to D7 , D6.
0
·Set the LCD panel configuration.
·Resetting sets the 1 screen driving panel.
·set when register is
initialized.
0
·Set the LCD display mode (binary or gray scale).
·Resetting sets the binary display mode.
·set when register is
initialized.
0
·Set the transfer path width of the LCD display data path
VD<n:0>.
·Resetting sets 4bit transfer.
·set when register is
initialized.
1 2 screen driving panel
D1
GRAY
0 Binary display mode
1 Gray scale display mode
D0
4/8
0
4bit transfer
1
8bit transfer
0
9
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R3] Number of horizontal display characters
Address R/W
Function
Restriction
·Sets the number of hori-zontal
Number of LCD display dots
Number of
display characters per line.
D7 to D0 characters Binary display Gray scale display ·Resetting sets "28 H" (=40
characters).
00H
CR
04H
W
01H
1
8
4
02H
2
16
8
FF H
255
2040
1020
·For CR, maximum of 255
characters can be set.
·In display modes 2,
3 , 4 and 6 , the number
of even cha-racters can be
set.
Reset
28H
(Note) Definition of the number of characters
The number of display characters means data corresponding to 1byte of VRAM.
One character : In the case of binary, one character means 8dots of LCD display.
In the case of gray scale display, one character means 4dots of LCD display (because 2bits of VRAM corresponds to 1dot of LCD display).
[R4] Horizontal synchronous pulse width
Address R/W
Function
LPW
Number of
D7 to D0 characters
00H
06H
W
01H
02H
2
FF H
255
Restriction
Reset
·In the unit of characters, set the width of horizontal synchronous
pulse generated per line.
Horizontal synchronous pulse is output from the LP pin and is
used for serial/parallel conversion of displayed data.
Adjustment of LPW can set the frame frequency to an optimum
value.
The LP output pulse actually generated takes the value(LPW
setup value - 2CP), taking into account the CP output timing.
Only in the case of display mode 4, however, the LP output
pulse takes the value (LPW set value - 1CP).
·Resetting sets "04 H" (= 4 characters).
·In display modes 2
, 3 , 4 and 6 , only the
number of even characters
can be set.
·In display modes 1 and 5
, set LPW to 02H or more.
·In display modes 2
, 3 , 4 and 6 , set LPW
to 04H or more.
Function
·In unit of characters, set the period of access by the cycle steal
system near the end of the horizontal synchronous portion set
with LPW.
·With CSW=LPW, gain access by the permanent cycle steal
system.
·Resetting sets "02 H" (=2 characters).
Restriction
Reset
·Set CSW to the LPW set
value or less.
·In display modes 2,
3 , 4 and 6 , only the
number of even
02H
characters can be set.
·In display modes 1 and 5
,set CSW to 01H or more.
·In display modes 2 ,
3 , 4 and 6 , set CSW
to 02H or more.
04H
[R5] Cycle steal enable width
Address R/W
CSW
Number of
D7 to D0 characters
00H
08H
W
01H
1
02H
2
FF H
255
[R6] Number of vertical lines
Address R/W
Function
SLT
Number of
D7 to D0 vertical lines
00H
0AH
10
W
01H
2
02H
4
FF H
510
·Sets the number of lines displayed in the direction of LCD vertical
line.
·SLT also sets the LCD display driving duty.
·In dual scan mode, the actual number of displayed lines is given
by SLT x 2 screens.
·Resetting sets "78 H" (=240 lines).
Restriction
·Be sure to set SLT according to the number of
LCD display lines.
·For SLT, a maximum of
510 even lines can be
set.
Reset
78H
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R7, R8] 1st screen display start address
Function
Address R/W
SA1H
SA1L
D7 D6 to D0 D7 to D0
0C H
(SA1L)
R/W
0EH
(SA1H)
1st screen display start
address
00H
00H
0000H
00H
02H
0002H
00H
04H
0004H
4AH
FEH
4AFEH
Restriction
·Sets the 1st screen display
start address.
·The display start address is
determined by writing data
into SA1H.
·Reading SA1H outputs "0" to
D7.
·Resetting sets "0000H".
·At the display start add-ress,
even addresses can only
be set.
· For single scan;
0000H to 4AFEH
· For dual scan;
Sets 0000H to 257EH.
Settings except for the
above must not be made.
·To modify the display start
address, be sure to
respecify in order of SA1LSA1H even when only
SA1L is modified.
Reset
00H
00H
[R9, R10] 2nd screen display start address
Function
Address R/W
SA2H
SA2L
D7 D6 to D0 D7 to D0
10H
(SA2L)
R/W
12H
(SA2H)
2nd screen display start
address
25H
80H
2580H
25H
82H
2582H
25H
84H
2584H
4AH
FEH
4AFEH
Restriction
·Used for dual scan mode
only to set the 2nd
screen display start
address.
·The display start address is
determined by writing data
into SA2H.
·Reading SA2H outputs "0" to
D7.
·Resetting sets "2580H".
·At the display start address, only even addresses can be set, and;
·Can set 2580H to 4AFEH.
Settings except for the
above must not be
made.
·To modify the display start
address, be sure to
respecify in order of
SA2L - SA2H even when
only SA2L is modified.
Reset
80H
25H
[R11] M output cycle variable
Function
Address R/W
MT
D7 to D0
14H
W
Output cycle of M signal
00H
Makes toggle change every frame.
01H
Makes toggle change every line (=1LP).
02H
Makes toggle change every 2 lines.
FF H
Makes toggle change every 255 lines.
Restriction
·Sets the output cycle of M signal
output from the M terminal.
With MT=01H, for example, M signal repeatedly reverses (toggles)
every line.
·Resetting sets "00H".
·It is recommended to set this
register to an optimum value according to the LCD specification.
Reset
00H
11
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R12, R13] VRAM address index (8bit MPU only)
Address R/W
Function
IDX8H
16H
IDX8L
VRAM address
to access
D7 D6 to D0 D7 to D0
(IDX8L)
R/W
00H
00H
0000H
00H
01H
0001H
00H
02H
0002H
18H
(IDX8H)
FF H
4AH
4AFFH
Reset
Restriction
·VRAM addresses to
·VRAM address index register only for LCD
access can be set to
module built-in system. Sets the VRAM
0000H to 4AFFH.
address to access.
·Since IDX8H and IDX8L are independent from Settings except for the
above must not be made.
each other, either one of the register values
can also be set and modified.
In addition, automatic increments are made
for consecutive addresses.
·Reading IDX8H outputs "0" to D7.
·Resetting sets "0000H".
00H
00H
[R14] Data port (8bit MPU only)
Address R/W
Function
DP8
Data port (8bit)
D7 to D0
1AH
R/W
Restriction
·Data port register only for LCD module builtin type support additional functions. Via this
register, 8bit data is read/written between
MPU and VRAM.
·Completion of access to DP8 increments the
IDX8H and IDX8L values by +1.
· Resetting outputs undetermined data.
Reset
XXH
(Undetermined)
[R15] VRAM address index (16bit MPU only)
Address R/W
Function
IDX16
D15
1C H
D14 to D0
VRAM address
to access
0000H
0000H
0002H
0002H
0004H
0004H
4AFEH
4AFEH
R/W
Reset
Restriction
·VRAM address index register only for LCD
module built-in type support addi-tional
functions. Sets the VRAM address to
access.
·Automatically incremented for consecu-tive
addresses.
·Reading IDX16 outputs "0" to D15.
·Resetting sets "0000H".
·VRAM address to ac-cess
can be set to 0000H to
4AFEH.
Settings except for the
above must not be made.
·Set the VRAM address
with D<14:1> and fix it to
D<0>=0.
0000H
Note : With SWAP="1" set, set the byte-swapped data for the VRAM address to access.
(Set low order bytes of VRAM address to D<15:8> and set high order bytes of VRAM address to D<7:0>.)
[R16] Data port (16bit MPU only)
Address R/W
DP16
D15 to D0
1EH
R/W
Restriction
Function
Data port (16bit)
·Data port register only for LCD module builtin type support additional functions. Via this
register, 16bit data is read/ written between
MPU and VRAM.
·Completion of access to DP16 incre-ments
the IDX16 value by +1.
·Resetting outputs undetermined data.
Note : Registers R12 to R16 are used only for LCD module built-in system.
Register setting is not needed if these functions are not used.
12
Reset
XXXXH
(Undetermined)
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R17 to R80] Gradation patterns 0-1 to 32 and 1-1 to 32
Address R/W Function
Restriction
Register
No.
Name
R17 Gray scale pattern 0-1
20H
to
5EH
R/W
R18 Gray scale pattern 0-2
to
to
to
to
5C H
FRC0-16-2 FRC0-16-1
R48 Gray scale pattern 0-32
5EH
FRC0-16-4 FRC0-16-3
No.
Name
R49 Gray scale pattern 1-1
R/W
to
Data
R47 Gray scale pattern 0-31
Register
60H
to
9EH
·Sets data of gradation
pattern 0.
D3 to D0
A<7:0> D7 to D4
Gradation pattern 0
FRC0-1-2 FRC0-1-1
provides 16 patterns of
20H
4 x 4 matrix.
FRC0-1-4 FRC0-1-3
22H
Address
R50 Gray scale pattern 1-2
to
to
·Set gradation patterns
when the register is
initialized.
·When access to R17 to
R80, must be set
XXH
(UndeterDISP=OFF.
mined)
Can't access to R17
to R80 on DISP=ON.
·All registers R17 to R80
must be set.
·Sets data of gradation
pattern 1.
D3 to D0
A<7:0> D7 to D4
Gradation pattern 1
FRC1-1-2 FRC1-1-1
60H
provides 16 patterns of
4 x 4 matrix.
FRC1-1-4 FRC1-1-3
62H
Address
to
Reset
Data
to
(Undetermined)
to
R79 Gray scale pattern 1-31
9C H
FRC1-16-2 FRC1-16-1
R80 Gray scale pattern 1-32
9EH
FRC1-16-4 FRC1-16-3
XXH
FRC0-1-1
Gray scale pattern 0-1
Gray scale pattern table 0 or 1
Register running Nos. 1 to 32
Gray scale pattern table 0 or 1
Number of patterns : 1 to 16
Number of lines : 1 to 4
Gray scale pattern setting example
Gray scale pattern 0-1 = 48H
Gray scale pattern 0-2 = 12H
1st frame
1st line
FRC0-1-1
2nd line
FRC0-1-2
3rd line
FRC0-1-3
4th line
FRC0-1-4
Note : Registers R17 to R80 are used to set gray scale patterns for gray scale display.
Register setting is not needed for binary display.
13
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Description of LCD display
Relationships between control register setting and LCD display
1 horizontal line
CR
LPW
CSW
SA2H,L
SA1H,L
2nd screen
1st
screen
LCD screen to
be display ed
SLT
Control register setting conditions
·1st screen drive
Binary --- (CR x 8) x SLT
Gray scale --·2nd screen drive
Binary --- (CR x 8) x (SLT x 2)
Gray scale ---
1 horizontal line
Number of horizontal display
characters CR
Horizontal synchronous
pulse width LPW
<=153600 dots
<= 76800 dots
<=153600 dots
<= 76800 dots
x Number of vertical lines SLT
MAINCLK
1
2
3
m-2
m-1
m
1
2
CP
Data not determined
VD<n:0>
LP
(1) Time required for processing 1 horizontal line (TH)
2
x (CR+LPW)
TH =
·Display modes 1 and 5
fMAINCLK
·Display mode
2 , 3 , 4 and
6
TH =
1
x (CR+LPW)
fMAINCLK
(2) Time required for processing 1 frame (TFR)
TFR = TH x SLT
Relationships between control register setting and LCD display
14
CR,LPW,CSW : Unit of characters
SLT : Unit of even lines
fMAINCLK : Frequency of MAINCLK for
internal operation
Adjustment of LPW can set the number of
frame frequencies requested on the LCD panel
side to an optimum value.
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Relationships between display start address and LCD display
Example) When 8bit MPU is used :
With display start address = 1000 H
0000H
0001
1000H
1001H
LCD screen
VRAM
~
~
1000H
~
~
1001H
~
~
4AFE H 4AFFH 0000H
~
~
0001H
4AFE H 4AFFH
·The data of display start address (SA1H, L, SA2H,
L) is displayed upper left in the LCD.
·The display start address is loaded from register
in frames.
Relationships between display start address and LCD display
Relationships between VRAM address, data and LCD display
VRAM address, data
For 16bit MPU A<14:0>
D<15:0>
For 8bit MPU
A<14:0>
D<7:0>
A<14:0>
D<15:0>
A<14:0>
D<7:0>
0000H
E41BH
0000H
E4H
D15 D14 D13 D12 D11
D7 D6 D5 D4 D3
1
1
1
0
0
a
b
c
d
e
D10
D2
1
f
D9
D1
0
g
D8
D0
0
h
D7
D7
0
i
D6
D6
0
j
D5
D5
0
k
0001H
1BH
D4 D3
D4 D3
1
1
l
m
D2
D2
0
n
D1
D1
1
o
D0
D0
1
p
D5
D5
0
K
2581H
50H
D4 D3
D4 D3
1
0
L
M
D2
D2
0
N
D1
D1
0
O
D0
D0
0
P
16bit MPU (when
setting SWAP = "0")
8bit MPU
2580H
FA50H
2580H
FAH
D15 D14 D13 D12 D11
D7 D6 D5 D4 D3
1
1
1
1
1
A
B
C
D
E
D10
D2
0
F
D9
D1
1
G
D8
D0
0
H
D7
D7
0
I
D6
D6
1
J
LCD display
Display mode
1
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
Display mode
3
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
Display mode
2
VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
Display mode
4
VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
1
a
1
b
1
c
0
d
0
e
1
f
0
g
0
h
a
b
c
d
e
f
LCD screen
Display mode
5
VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4
1
a
1
b
1
c
0
d
0
e
1
f
0
g
0
h
Display mode
6
1
A
1
B
1
C
1
D
1
E
0
F
2nd screen of LCD
1
G
0
H
m
n
o
p
VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4
a
b
c
d
e
f
1st screen of LCD
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
g
i
k
h
j
l
LCD screen
g
i
k
m
h
j
l
n
1st screen of LCD
o
p
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
A
B
C
D
E
F
G
I
K
M
H
J
L
N
2nd screen of LCD
O
P
: Gray scale display image
15
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Relationships between SWAP setting and LCD display
When 16bit MPU is in use, setting the SWAP register can modify the sending order of LCD display data in bytes.
SWAP setting
0
1
For D<15:0>, sends VD<n:0> in order of upper / lower bytes.
For D<15:0>, sends VD<n:0> in order of lower / upper order bytes.
D15 D14 D13 D12 D11 D10 D9
1
1
1
0
0
1
0
VRAM data
D8
0
D7
0
High order byte = E4H
to
D5
0
D4
1
D3
1
D2
0
D0
1
D1
1
Low order byte = 1BH
·Setting SWAP = "1"
·Setting SWAP = "0"
D15
D6
0
D8D7
to
D0
D7
1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1
E4H
to
D0D15
to
D8
0 0 0 1 1 0 1 1 1 1 1 0 0 1 0 0
1BH
1BH
LCD screen
E4H
LCD screen
Relationships between LCD display mode and VD<n:0> pin
Single scan mode 4bit parallel Display mode
1
,
3
VD3 VD2 VD1 VD0
Dual scan mode 4bit parallel Display mode
VD7 VD6 VD5 VD4
LCD screen
1st screen of LCD
VD3 VD2 VD1 VD0
Single scan mode 8bit parallel Display mode
VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
LCD screen
16
2
,
4
2nd screen of LCD
5
,
6
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Output signal on the LCD side
Example) Assuming 320 x 240 dots LCD is used in display mode 1
(CR = 40 characters, LPW = 2 characters, SLT = 240 lines, DIV = division value 1, MT = 1)
(1) Output per line
MAINCLK
80
1
2
79
80
1
2
CP
Output each time one
piece of display data
is transferred.
4bit transfer
VD<3:0>
Output when display
data for a line is
comp-letely sent.
LP
(2) Output signal per screen
239
240
239
1
240
1
LP
FLM
Output when display
data in the 1st line is
completely sent.
M
Output reverse period
of M signal can be set
with the MT register.
(3) LCDENB output signal
MAINCLK
LCDENB
(4) Reset to 1st screen/1st line
RESET
MAINCLK
LCDENB
LP
FLM
"L"
M
1
2
3
4
5
6
CP
1st screen/1st line
(5) 1st line to 2nd line
MAINCLK
LP
FLM
M
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
1st line
2nd line
(6) 1st screen/240th line to 2nd screen/1st line
MAINCLK
LP
FLM
"L"
M
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
1st screen/240th line
2nd screen/1st line
17
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Description of cycle Steal
Basic timing
The basic timing for internal operation of the M66273 adopts 2 clocks of
MAINCLK as a basic cycle to assign the 1st clock and 2nd clock to access
from MPU to VRAM and transfer of display data from VRAM to the LCD
side, respectively.
MAINCLK is reference clock for internal operation inputting division of
MPUCLK and reference with rising edge of MPUCLK.
MPU access execution cycle (WAIT output period)
Writing/reading to/from VRAM in the display section takes,
Best case = 0.5tc(MAINCLK) + 1tc(CLK),
Worst case = 2.5tc(MAINCLK) + 1tc(CLK),
depending on the internal cycle steal status when access request from
MPU starts.
LCD access cycle
MPU access cycle
Display data
Access
to VRAM transfer from
from MPU VRAM to LCD
MPU
LCD
MAINCLK
Basic
cycle
Basic timing
In this case, tc(CLK) = MPUCLK cycle time,
tc(MAINCLK) = MAINCLK cycle time.
LCD access cycle
MPU access cycle
LCD access cycle
MAINCLK
Ex.1 ) Assuming set to WAITCNT = "0" and MCS input is faster than RD or LWR/HWR input.(1/4 division)
Best case (When access start in LCD access cycle.)
MCS
MPU access
execution cycle
LWR
0.5tc (MAINCLK)
1tc (CLK)
WAIT
Release of WAIT in synchronization with rising edge of
MPUCLK.
Start of WAIT in synchronization with falling edge of
LWR.
MPUCLK
Worst case (When access start in MPU access cycle.)
MCS
MPU access
execution cycle
LWR
1tc (CLK)
1.5tc (MAINCLK)
WAIT
Start of WAIT in synchronization with falling edge of
LWR.
Release of WAIT in synchronization with rising edge of
MPUCLK.
MPUCLK
Ex.2 ) Assuming set to WAITC = "1".(1/4 division)
Best case (When access start in LCD access cycle.)
MCS
WAITCNT
MPU access
execution cycle
LWR
0.5tc (MAINCLK) 1tc (CLK)
WAIT
Start of WAIT in synchronization with falling edge of
WAITCNT.
Release of WAIT in synchronization with rising edge of
MPUCLK.
MPUCLK
Worst case (When access start in MPU access cycle.)
MCS
WAITCNT
MPU access
execution cycle
LWR
1.5tc (MAINCLK)
WAIT
MPUCLK
18
MPU access execution cycle
1tc (CLK)
Release of WAIT in synchronization with rising edge of
MPUCLK.
Start of WAIT in synchronization with falling edge of
WAITCNT.
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Description of cycle steal control function
The M66273 provides the cycle steal control function to efficiently carry
out one-line data processing.
In the display section where display data requires to be transferred from
built-in VRAM to the LCD side, this function adopts a cycle steal system
to gain access to the MPU while putting the MPU in WAIT.
In a horizontal synchronous section where display data does not
require to be transferred from VRAM to the LCD side, this function does
not output WAIT in the section to avoid reducing the MPU throughput.
However, since malfunction is restrained near the termination of
horizontal synchronous section, the CSW register should be surely set
to provide a period of access by the cycle steal system.
(It need to set at least 1 cycle of MPU bus timing.)
Example) Assuming 320 x 240 dot LCD in display mode 1.
1 horizontal line
Output when 1-line
display data is
comp-letely sent.
LP
1
2
3
78
79
80
1
CP
Output each time
one piece of display
data is transferred.
4bit transfer
VD<3:0>
Set with the CR register
Section where data requires to be
transferred from display section = VRAM to
the LCD side (cycle steal system)
Set with the LPW register
Section where data does not require to be
transferred from horizontal section =
VRAM to the LCD side
CSE
Set with the CSW register
Putting MPU in WAIT according
to cycle steal access.
WAIT
Gains access at the
MPU bus timing without
putting MPU in WAIT.
Provides a timing for
setting CSE to ÒHÓ
to put MPU in WAIT.
Without putting
MPU in WAIT
19
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Description of gray scale function
Set the same pattern for each 4 or 8 frames period in 16 frames.
So enable to decrease frame numbers of gray scale period.
Set gray scale mode by register (GRAY= "1").
Gray scale assign 2bits of VRAM to 1dot of LCD and displaying
4density.
ex.) for 8bit-MPU
1 Address
VRAM data D7 D6 D5 D4 D3 D2 D1 D0
Pack
C1 C0 C1 C0 C1 C0 C1 C0
C1
0
0
1
1
Still more, set the same gray scale pattern table in frame unit, so enable
to display thinned-out frame method.
When thinned-out 1frame from continuous 4frames, the following are
example of setting pattern table.
1st frame
2nd frame
Contents of display
Display OFF
Followed gray scale pattern table 0
Followed gray scale pattern table 1
Display ON
C0
0
1
0
1
D7
VRAM data
Gray scale
n Address
D0
1 1 1 0 0 1 0 0
3
2
1
0
D7
4th frame
4 Frames
n+1 Address
Thinned-out
frame
D0
t
1 1 0 0 0 1 1 0
3
0
1
Turn on frame
2
When use thinned-out frame, distribute thinned-out equally, and avoid
thinned-out continuous frame together.
Image of LCD
Upper figure are image of gray scale display of LCD and VRAM data,
actually controlling pseudo medium gray scale.
Setting of gray scale pattern table
Gray scale pattern table 0, 1 a used for controlling display density. It set
to control register R17-R80 (SRAM configuration).
Gray scale pattern set 16 patterns for 1 medium gray scale (1 pattern =
4dots x 4lines matrix).
It need to set 32 patterns (64 byte) because 2 medium gray scale.
Medium gray scale period is a maximum of 16 frames.
Example of gray scale pattern
The following are example of gray scale pattern. (Select 4dots from
1matrix, and each dot set equally in 1 period.)
1st frame
3rd frame
2nd frame
3rd frame
4th frame
1st line
2nd line
3rd line
4th line
Gray scale function use the features of liquid crystal changed
brightness by practical voltage.
The following are gray scale patterns for each frame, and the relation
between brightness and practical voltage.
White
(0,0)
~
V0
Light gray
(0,1)
~
V1
5th frame
6th frame
7th frame
Gray
(1,0)
8th frame
~
V2
9th frame
10th frame
11th frame
12th frame
Black
(1,1)
~
V3
Practical voltage
13th frame
14th frame
15th frame
16th frame
Brightness
White
Light gray
When VRAM data are following, VD output 1 for only
Pack
C1
VRAM data 0
C0
1
C1
0
C0
1
C1
0
C0
1
C1
0
dot.
Gray
C0
1
Gray scale pattern of
1st line in 1st frame
Displaying data VD
Black
1
0
0
0
Gray scale pattern of
1st line in 2nd frame
Displaying data VD
20
V0
0
0
1
0
V1
V2
V3 Practical voltage
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Additional function for LCD module built-in system
(When use this function,recommend using ICOS to control I/O registers.)
As all of the VRAM address in the M66273 are externally opened
for addressing VRAM from MPU directly.
· Interface pins with MPU and I/O register for access to VRAM.
When consider the LCD module built-in system, connect pins are
increased.
But the M66273 has an additional function for the LCD module built-in
system by lessening connect pins.
8bit MPU
A<7:1>
D<7:0>
IOCS
LWR
Interface pins
RD
MPUCLK
(19 pins)
Access the internal VRAM through the VRAM address index register in
this function.
When use this function, need to set to IDXON = "0".
When use this function and access to VRAM, it need to set to DISP = "0".
IDX8H, IDX8L
DP8
I/O register
· Method of accessing the internal VRAM
The following show the process of accessing VRAM.
16bit MPU
A<7:1>
D<15:0>
IOCS
LWR
RD
MPUCLK
(27 pins)
IDX16
DP16
· No use pins set the following.
·HWR, MCS = "H",
·BHE, A<0>, A<14:8> = "L" , D<15:8> = "L" (only for 8bit MPU),
·MPUSEL, WAITCNT = "L" or "H",
·WAIT, CSE = open,
RESET = Power on reset or software reset.
· (In case of software reset RESET = "H" : set)
Set fixed pins
Set control register
set to DISP = "0"
· Access the DP after writing the mode register DISP = "0".
Always enable to access, because the display signal fixed "H" or "L"
in DISP = "0" and a term is no wait access.
Discontinuous address
Access to
VRAM address
index register
· Select IDX8L, IDX8H (or IDX16), and write address (15bit) of VRAM as data.
Enable to change IDXL and IDXH, even if either.
Continuous address
Access to Data Port
register
· Select DP8 (or DP16), and read or write data to address of VRAM.
Access DP and IDX without WAIT function.
VRAM address is automatically increased of +1, when finished access to DP.
After setting data of VRAM It doesn't need to set IDX, when access to continuous address.
VRAM address is
increased of +1.
Set to DISP = "1"
· Set to DISP = "1", and displaying LCD.
· Example of access to VRAM (In case of 8bit MPU)
Increase to
Addr=0001
Increase to
Addr=1001
Increase to
Addr=1002
IOCS
LWR
R1
R1
R12
R13
R14
R12
R13
R14
R14
R14
R14
R1
A<7:0>
00 H
00 H
16 H
18 H
1A H
16 H
18 H
1A H
1A H
1A H
1A H
00 H
D<7:0>
80 H
40 H
00 H
00 H
AA H
00 H
10 H
BB H
CC H
DD H
EE H
44 H
Write
Data=CC
to
Addr=1001
Write
Data=DD
to
Addr=1002
Software IDXON=1
reset
DISP=0
(initialize)
Write Data=AA
to Addr=0000
Write Data=BB
to Addr=1000
Discontinuous address
Write
Data=EE
to
Addr=1003
IDXON=1
DISP=1
Continuous address
21
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
ABSOLUTE MAXIMUM RATINGS (Ta=-20 to +75 C unless otherwise noted)
Symbol
Parameter
Condition
Ratings
Unit
VDD
Supply voltage
-0.3 to +6.5
V
VI
Input voltage
-0.3 to VDD+0.3
V
VO
Output voltage
-0.3 to VDD+0.3
V
IO
Output current
±20
mA
Pd
Power dissipation
600
mW
Tstg
Storage temperature
-55 to +150
C
RECOMMENDED OPERATING CONDITIONS (Ta=-20 to +75 C unless otherwise noted)
Symbol
Parameter
VDD
Supply voltage
VSS
Supply voltage
Condition
5.0V support
3.0V support
Limits
Min. Typ.
4.5
5.0
2.7
3.0
Max. Unit
5.5
V
3.3
V
0
VI
Input voltage
0
VDD
V
VO
Output voltage
0
VDD
V
Topr
tr, tf
Operating temperature
-20
Normal input
Schmidt trigger input
Input rise, down time
+25
+75
C
500
ns
5
ms
ELECTRICAL CHARACTERISTICS (5V version support specifications, Ta=-20 to +75 C unless otherwise noted )
Symbol
Parameter
VIH
"H" input voltage
VIL
"L" input voltage
VT+
VT-
Threshold voltage in positive direction
Threshold voltage in negative direction
VOH
"H" output voltage
VOL
"L" output voltage
IIH
"H" input current
IIL
"L" input current
Note 1
VDD = 5.5V
VDD = 4.5V
Note 2
VDD = 5.0V
IOH = -4mA
IOL = 4mA
VDD = 5.5V
VI = V DD
VI = V SS
-10
VDD = 5.5V
VO = V DD
VO = V SS
-10
Display mode 1,2,3,4
60
Display mode 5,6
80
"H" output current in off status
IOZL
"L" output current in off status
IDD(A)
Average supply current in operation
mode
VDD = 5.5V, VI = V DD or VSS
fMAINCLK = 15MHz(MAX),
Output =open
Supply current in static mode
VDD = 5.5V, IOCS, MCS = VDD
Other VI = V DD or VSS fixed
D<15:0>
Notes 1: Normal input terminal
--- A<14:0>, D<15:0>
2: Schmidt trigger input terminal --- All input pins except for A<14:0>, D<15:0>
22
4.1
VDD = 4.5V
IOZH
IDD(S)
Limits
Min. Typ. Max. Unit
3.85
5.5
V
0
1.35
2.3
3.7
V
1.25
2.3
Condition
0.4
10
10
V
uA
uA
mA
200
uA
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
ELECTRICAL CHARACTERISTICS (3V version support specification, Ta=-20~+75 C unless otherwise noted )
VIH
"H" input voltage
VIL
"L" input voltage
VT+
Threshold voltage in positive direction
VT-
Threshold voltage in negative direction
VOH
"H" output voltage
VOL
"L" output voltage
IIH
"H" input current
IIL
"L" input current
IOZH
"H" output current in off status
IOZL
"L" output current in off status
IDD(A)
IDD(S)
Limits
Unit
Min. Typ. Max.
2.31
3.3
V
0
0.81
Condition
Parameter
Symbol
Note 1
VDD = 3.3V
VDD = 2.7V
Note 2
VDD = 3.0V
D<15:0>
1.27
2.18
0.45
1.5
2.3
VDD = 2.7V
IOH = -4mA
IOL = 4mA
VDD = 3.3V
VI = V DD
VI = V SS
-10
VDD = 3.3V
VO = V DD
VO = V SS
-10
Average supply current in operation
mode
VDD = 3.3V, VI = V DD or VSS
fMAINCLK = 10MHz(MAX),
Output = open
Supply current in static mode
VDD = 3.3V, IOCS, MCS = VDD
Other VI = V DD or VSS fixed
V
V
0.4
10
10
Display mode 1 to 4
25
Display mode 5 and 6
35
uA
uA
mA
200
uA
Notes 1: Normal input terminal
--- A<14:0>, D<15:0>
2: Schmidt trigger input terminal --- All input pins except for A<14:0>, D<15:0>
STANDARD CHARACTERISTICS (Ta=25 C )
SUPPLY CURRENT VS OPERATING FREQUENCY
(DISPLAY MODE 3)
SUPPLY CURRENT VS OPERATING FREQUENCY
(DISPLAY MODE 1)
50
50
VDD=5.5V
40
VDD=5.5V
40
VDD=3.3V
30
30
20
20
10
10
0
VDD=3.3V
0
2
4
6
8
10
OPERATING FREQUENCY
12
14
16
f (MHz)
2
4
6
8
10
OPERATING FREQUENCY
12
14
16
f (MHz)
SUPPLY CURRENT VS OPERATING FREQUENCY
(DISPLAY MODE 6)
50
VDD=5.5V
40
VDD=3.3V
30
20
10
0
2
4
6
8
10
OPERATING FREQUENCY
f
12
14
(MHz)
16
23
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
5V version support spcification
SWITCHING CHARACTERISTICS (V DD =5V±10%, Ta=-20~+75 C )
Symbol
Parameter
tdis(IOCS-D)
tdis(MCS-D)
tdis(RD-D)
IOCS data access time
MCS data access time
RD data access time
Output disable time after IOCS
Output disable time after MCS
Output disable time after RD
tpHL(MCS-WAIT)
tpHL(WR-WAIT)
tpHL(RD-WAIT)
tpHL(WC-WAIT)
WAIT output propagation time after MCS
WAIT output propagation time after WR
WAIT output propagation time after RD
WAIT output propagation time after WAITCNT
ta(IOCS-D)
ta(MCS-D)
ta(RD-D)
Test
condition
Min.
Limits
Ty p.
tpLH(CLK-WAIT) WAIT output propagation time after MPUCLK
Max.
Unit
70
ns
20
ns
15
ns
15
ns
30
ns
tpd(CLK-CP)
CP output propagation time after MPUCLK
tpLH(CLK-LP)
tpHL(CLK-LP)
LP output propagation time after MPUCLK
30
ns
ta(VD)
VD access time
30
ns
tpLH(CLK-FLM)
tpHL(CLK-FLM)
FLM output propagation time after MPUCLK
30
ns
tpd(CLK-M)
M output propagation time after MPUCLK
30
ns
tpLH(CLK-LE)
tpHL(CLK-LE)
LCDENB output propagation time after MPUCLK
30
ns
tpLH(CLK-CSE)
tpHL(CLK-CSE)
CSE output propagation time after MPUCLK
30
ns
tpd(D-WAIT)
Data definite time before cancelling WAIT
CL=50pF
0
ns
TIMING REQUIREMENTS (V DD =5V±10%, Ta=-20~+75 C )
(1) Accessing to control register
Symbol
Parameter
Test
condition
Min.
Limits
Ty p.
Max.
Unit
t W(CS)
t W(LWR)
IOCS/MCSpulse width
LWR pulse width
35
ns
t su(D-CS)
t su(D-LWR)
Data set up time before rising edge of IOCS/MCS
Data set up time before rising edge of LWR
20
ns
t h(CS-D)
t h(LWR-D)
Data hold time after rising edge of IOCS/MCS
Data hold time after rising edge of LWR
2
ns
t su(A-CS)
t su(A-LWR)
t su(A-RD)
t h(CS-A)
t h(LWR-A)
t h(RD-A)
Address set up time before falling edge of IOCS/MCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
10
ns
0
ns
Address hold time after rising edge of IOCS/MCS
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
(2) Accessing to VRAM
Symbol
Parameter
Min.
Limits
Ty p.
Max.
Unit
t W(MCS)
t W(WR)
MCS pulse width
WR pulse width
35
ns
t su(D-MCS)
t su(D-WR)
t h(MCS-D)
t h(WR-D)
Data set up time before rising edge of MCS
Data set up time before rising edge of WR
20
ns
2
ns
t su(A-MCS)
t su(A-WR)
t su(A-RD)
t h(MCS-A)
t h(WR-A)
t h(RD-A)
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
10
ns
0
ns
t su(D-CLKD)
Data set up time before rising edge of WAIT
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
t su(MCS-WC) MCS set up time before falling edge of WAITCNT
24
Test
condition
t su(CLK)+10
ns
5
ns
* tc(CLK)=MPUCLK cycle time
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(3) Clock and accessing to LCD display
Symbol
Parameter
t c(CLK)
MPUCLK cycle time
t WH(CLK)
MPUCLK "H" pulse width
t WL(CLK)
MPUCLK "L" pulse width
Test
condition
t WH(CP)
CP "H" pulse width
t WL(CP)
CP "L" pulse width
t W(FLM)
FLM pluse width
ns
tC(CLK)
(1/n)
ns
2 · tC(CLK)
(1/n)
ns
Display mode 1,2,3,5,6
tC(CLK)
2 · (1/n)
ns
Display mode 4
tC(CLK)
(1/n)
ns
tC(CLK) · LPW
(1/n)
ns
2 · tC(CLK) · LPW
(1/n)
ns
CP "H" pulse width
CP "L" pulse width
Unit
ns
CP syscle time
t WL(CP)
Max.
tC(CLK)
2
Display mode 4
t WH(CP)
Limits
Ty p.
50
Display mode 1,2,3,5,6
t C(CP)
Min.
Display mode 1,2,3,5,6
Display mode 4
Note : Clock frequency of MPUCLK input is less than fmax = 20MHz.
Limit of clock for the internal operation is fmax = 15MHz.
When MPUCLK is more than 15MHz from extemal input,set clock for the internal operation
up to 15MHz by using division of DIV register.
Division is set with rising dege of MPUCLK input.
1/n =Division of MPUCLK
LPW =Setting value of LPW register
25
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
3V version support spcification
SWITCHING CHARACTERISTICS (V DD =3V±10%, Ta=-20~+75 C )
Symbol
Test
condition
Parameter
Min.
Limits
Ty p.
IOCS data access time
MCS data access time
RD data access time
Output disable time after IOCS
tdis(IOCS-D)
Output disable time after MCS
tdis(MCS-D)
tdis(RD-D)
Output disable time after RD
tpHL(MCS-WAIT) WAIT output propagation time after MCS
tpHL(WR-WAIT) WAIT output propagation time after WR
tpHL(RD-WAIT) WAIT output propagation time after RD
tpHL(WC-WAIT) WAIT output propagation time after WAITCNT
ta(IOCS-D)
ta(MCS-D)
ta(RD-D)
tpLH(CLK-WAIT) WAIT output propagation time after MPUCLK
Max.
Unit
100
ns
30
ns
25
ns
25
ns
40
ns
tpd(CLK-CP)
CP output propagation time after MPUCLK
tpLH(CLK-LP)
tpHL(CLK-LP)
LP output propagation time after MPUCLK
40
ns
ta(VD)
VD access time
40
ns
tpLH(CLK-FLM)
tpHL(CLK-FLM)
FLM output propagation time after MPUCLK
40
ns
tpd(CLK-M)
M output propagation time after MPUCLK
40
ns
tpLH(CLK-LE)
tpHL(CLK-LE)
LCDENB output propagation time after MPUCLK
40
ns
tpLH(CLK-CSE)
tpHL(CLK-CSE)
CSE output propagation time after MPUCLK
40
ns
tpd(D-WAIT)
Data definite time before cancelling WAIT
CL=50pF
ns
0
TIMING REQUIREMENTS (V DD =3V±10%, Ta=-20~+75 C )
(1) Accessing to control register
Symbol
Parameter
Test
condition
Min.
Limits
Ty p.
Max.
Unit
t W(CS)
t W(LWR)
IOCS/MCS pulse width
LWR pulse width
50
ns
t su(D-CS)
t su(D-LWR)
Data set up time before rising edge of IOCS/MCS
Data set up time before rising edge of LWR
30
ns
t h(CS-D)
t h(LWR-D)
Data hold time after rising edge of IOCS/MCS
Data hold time after rising edge of LWR
2
ns
t su(A-CS)
t su(A-LWR)
t su(A-RD)
t h(CS-A)
t h(LWR-A)
t h(RD-A)
Address set up time before falling edge of IOCS/MCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
15
ns
0
ns
Address hold time after rising edge of IOCS/MCS
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
(2) Accessing to VRAM
Symbol
Parameter
t W(MCS)
t W(WR)
t su(D-MCS)
t su(D-WR)
t h(MCS-D)
t h(WR-D)
t su(A-MCS)
t su(A-WR)
t su(A-RD)
t h(MCS-A)
t h(WR-A)
t h(RD-A)
MCS pulse width
WR pulse width
t su(D-CLK)
Data set up time before rising edge of WAIT
Data set up time before rising edge of MCS
Data set up time before rising edge of WR
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
t su(MCS-WC) MCS set up time before falling edge of WAITCNT
Test
condition
Min.
Limits
Ty p.
Max.
Unit
50
ns
30
ns
2
ns
15
ns
0
ns
t c(CLK)+15
ns
7
ns
* tc(CLK)=MPUCLK cycle time
26
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(3) Clock and accessing to LCD display
Symbol
Test
condition
Parameter
t c(CLK)
MPUCLK cycle time
t WH(CLK)
MPUCLK "H" pulse width
t WL(CLK)
MPUCLK "L" pulse width
Min.
t WH(CP)
t WH(CP)
CP "H" pulse width
t WL(CP)
tC(CLK)
(1/n)
ns
Display mode 4
2 · tC(CLK)
(1/n)
ns
Display mode 1,2,3,5,6
tC(CLK)
2 · (1/n)
ns
Display mode 4
tC(CLK)
(1/n)
ns
tC(CLK) · LPW
(1/n)
ns
2 · tC(CLK) · LPW
(1/n)
ns
CP "L" pulse width
Display mode 1,2,3,5,6
t W(FLM)
ns
ns
CP "H" pulse width
CP "L" pulse width
Unit
tC(CLK)
2
CP syscle time
t WL(CP)
Max.
50
Display mode 1,2,3,5,6
t C(CP)
Limits
Ty p.
FLM pluse width
Display mode 4
Note : Clock frequency of MPUCLK input is less than fmax = 20MHz.
Limit of clock for the internal operation is fmax = 10MHz.
When MPUCLK is more than 10MHz from extemal input,set clock for the internal operation
up to 10MHz by using division of DIV register.
Division is set with rising dege of MPUCLK input.
Test circuit
1/n =Division of MPUCLK
LPW =Setting value of LPW register
VDD
Input
VDD
RL=1K Ohm
SW1
D<15:0>
SW2
DUT
P.G
CL
RL=1K Ohm
50 Ohm
VSS
CL
Outputs
except for
D<15:0>
Parameter
t dis (LZ)
t dis (HZ)
t a(ZL)
t a(ZH)
SW1
Closed
Open
Closed
SW2
Open
Closed
Open
Open
Closed
(1) Input pulse level: 0 to 3V
Input pulse rise/fall time: tr,tf=3ns
Input decision voltage: 1.5V
Output decision voltage: VDD/2
(However,tdis(LZ) is 10% of output amplitude and
tdis(HZ) is 90% of that for dezision.)
(2) Load capacity C L include float capacity of
connection and input capacity of probe.
27
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
TIMING DIAGRAM
(1) Write to control register ( RD = "H")
No WAIT
tw(CS)
IOCS
(or MCS)
tw(LWR)
LWR
"H"
WAIT
th(CS-D)
tsu(D-CS)
tsu(D-LWR)
th(LWR-D)
Note 1
D<7:0>
Data input is established
tsu(A-CS)
th(CS-A)
th(LWR-A)
tsu(A-LWR)
A<7:0>
(or A<14:0>)
Address is established
(2) Read from control register (LWR= "H")
No WAIT
IOCS
(or MCS)
RD
"H"
WAIT
tdis(CS-D)
ta(CS-D)
ta(RD-D)
tdis(RD-D)
Note 1
D<7:0>
Data output is established
tsu(A-CS)
th(CS-A)
tsu(A-RD)
A<7:0>
(orA<14:0>)
th(RD-A)
Address is established
Note 1 : D<15:0> is used only when 16bit MPU controls the LCD module built-in type support function.
2 : Writing/reading operation for the control register is performed during "L" overlapping of IOCS or MCS and LWR or RD input signal.
Limits of IOCS,MCS, LWR and RD are prescribed by the input signal of last change to "L" in starting access, and by the input
signal of first change to "H" in ending access.
28
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(3) Write to VRAM
( RD = "H" )
Term of non cycle steal access
tw(MCS)
MCS
tw(WR)
LWR
(+HWR)
WAIT
tsu(D-WR)
D<7:0>
(D<15:0>)
"H"
th(WR-D)
Data input is established
tsu(A-MCS)
th(MCS-A)
th(WR-A)
tsu(A-WR)
A<14:0>
(+BHE)
(4) Read from VRAM
th(MCS-D)
tsu(D-MCS)
Address is established
(LWR, HWR = "H")
Term of non cycle steal access
MCS
RD
"H"
WAIT
tdis(MCS-D)
ta(MCS-D)
ta(RD-D)
D<7:0>
(D<15:0>)
tdis(RD-D)
Data output is established
tsu(A-MCS)
th(MCS-A)
tsu(A-RD)
A<14:0>
th(RD-A)
Address is established
Note 3 : Writing/reading operation for VRAM during non cycle steal access is performed during "L" overlapping of MCS and LWR
(+HWR) or RD input signal.
Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the
input signal of first change to "H" in ending access.
29
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(5) Write to VRAM ( RD = "H",WAITCNT= "L" or "H" fixed )
Term of cycle steal access (and When setting register WAITC to "0")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
tw(MCS)
MCS
tw(WR)
LWR
(+HWR)
WAIT
tpLH(CLK-WAIT)
tpHL(MCS-WAIT)
tpHL(WR-WAIT)
th(MCS-D)
tsu(D-CLK)
th(WR-D)
D<7:0>
(D<15:0>)
Data input is established
tsu(A-MCS)
th(MCS-A)
tsu(A-WR)
th(WR-A)
A<14:0>
(+BHE)
Address is established
(6) Read from VRAM( LWR, HWR = "H",WAITCNT = "L" or "H" fiexed)
Term of cycle steal access (and when setting segester WAITC to "0")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
MCS
RD
WAIT
tpLH(CLK-WAIT)
tpHL(MCS-WAIT)
tpHL(RD-WAIT)
ta(MCS-D)
ta(RD-D)
D<7:0>
(D<15:0>)
tdis(RD-D)
Data output is established
tsu(A-MCS)
th(MCS-A)
tsu(A-RD)
A<14:0>
tdis(MCS-D)
tpd(D-WAIT)
th(RD-A)
Address is established
Note 4 :Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
Data output D is established before changing WAIT output.
tc(M A I N C L K ) = Reference clock cycle time for internal operation after setting division of MPUCLK.
5 : Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of
first change to "H" in ending access.
6 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this
causes malfunction to occur.
30
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(7) Write to VRAM ( RD = "H" )
Term of cycle steal access (and When setting register WAITC to "1")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
tw(MCS)
MCS
WAITCNT
tsu(MCS-WC)
LWR
(+HWR)
tpLH(CLK-WAIT)
WAIT
th(MCS-D)
tsu(D-CLK)
tpHL(WC-WAIT)
th(WR-D)
D<7:0>
(D<15:0>)
Data input is established
th(MCS-A)
tsu(A-WR)
th(WR-A)
A<14:0>
(+BHE)
Address is established
(8) Read from VRAM ( LWR, HWR = "H")
Term of cycle steal access (and when setting register WAITC to "1")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
MCS
WAITCNT
tsu(MCS-WC)
RD
WAIT
tpHL(WC-WAIT)
tpLH(CLK-WAIT)
tdis(MCS-D)
ta(RD-D)
D<7:0>
(D<15:0>)
tdis(RD-D)
Data output is established
th(MCS-A)
tsu(A-RD)
A<14:0>
tpd(D-WAIT)
th(RD-A)
Address is established
Note 7 : Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
Data output D is established before changing WAIT output.
tc(M A I N C L K ) = Reference clock cycle time for internal operation after setting division of MPUCLK.
8 : When setting WAITC to "1" , MCS is necessary to change "L" earier than LWR (+HWR) ,RD.
Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first
change to "H" in ending access.
9 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this
causes malfunction to occur.
31
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(9) Interface timing with LCD (DIV = 1 division : set )
(9-1) LCD display data transfer
* When DIV = 1 division, MAINCLK for internal operation = MPUCLK input.
tC(CLK)
tWH(CLK)
tWL(CLK)
MPUCLK
tpd(CLK-CP)
tC(CP)
tWL(CP)
tWH(CP)
CP
tpLH(CLK-LP)
tpHL(CLK-LP)
LP
ta(VD)
Data is indefinite
VD<n:0>
(9-2) Control signal
MPUCLK
CP
LP
tpLH(CLK-FLM)
FLM
tpHL(CLK-FLM)
tW(FLM)
tpd(CLK-M)
M
tpLH(CLK-LE)
tpHL(CLK-LE)
LCDENB
Note 10 :
Output signal to LCD side is synchronized with MAINCLK (reference clock for internal operation).
When division is set to 1/2 to 1/16 by DIV register, switching characteristics is defined by rising edge of MPUCLK.
(10) CSE output timing (DIV=1 divison : set)
MPUCLK
tpHL(CLK-CSE)
CSE
32
tpLH(CLK-CSE)
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
FLOWCHART
EXAMPLE OF INITIALIZE ON DISPLAY MODE 3 (STANDARD ACCESS)
Example
of setting
Start
Note ) When use software reset, surely return to reset off
after reset on.
And then, can't set another bits (D6 to D0) at the
same time.
System reset
RESET input ="L" or use R1-D7(RESET)bit
#
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
(00 H )
R2:MPU/LCD mode register
(WAITC,SWAP,DUAL,GRAY,4/8)
(02 H )
R3:Number of horizontal display characters
register(CR)
(50 H )
R4:Horizontal synchronous pulse width
register(LPW)
(04 H )
R5:Cycle steal enable width register(CSW)
(04 H )
Set IDXON=OFF,DISP=OFF.
(Set RESET,IDXON,DIV when register is initialized.)
Set display mode, only when register is initialized.
Note ) Set R1-D6(IDXON) and R2 register at the beginning
of initializing register after system reset.
Set suitable value for LCD.
(Set these value only when register is
initialized.)
R6:Number of vertical lines register(SLT)
(78 H )
#
R7:1st screen display start address
register(SA1L)
(00 H )
Set lower address of 1st screen display start address.
#
R8:2nd screen display start address
register(SA1H)
(00 H )
Set upper address of 1st screen display start address.
R11:M output frequency variable register(MT)
(07 H )
Set suitable value for LCD.
(Set MT only when register is initialized.)
Set gray scale pattern.
Note ) When access to R17 to R80, must be set DISP=OFF.
Can't access to R17 to R80 on DISP=ON.
R17 to R80:Gray scale pattern register
Write display data to VRAM
N
Set display data to VRAM.
Complete?
Y
#
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
(05 H )
Set DISP=ON.
Display start
Setting example suppose LCD size = 320x240dots and display mode 3 (Single scan,Gray scale, 4bit transfer).
# Can change R1(DISP,REV,LCDE),R7(SA1L),R6(SA1h) registers value during display on.
33
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
EXAMPLE OF INITIALIZE ON DISPLAY MODE 3 (LCD MODULE BUILT-IN ACCESS)
Example
of setting
Start
Note ) When use software reset, surely return to reset off
after reset on.
And then, can't set another bits (D6 to D0) at the
same time.
System reset
RESET input ="L" or use R1-D7(RESET)bit
#
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
R2:MPU/LCD MODE REGISTER
(WAITC,SWAP,DUAL,GRAY,4/8)
(40 H )
Set IDXON=ON,DISP=OFF.
(Set RESET,IDXON,DIV when register is initialized.)
Set display mode, only when register is initialized.
(02 H ) Note ) Set R1-D6(IDXON) and R2 register at the beginning
of initializing register after system reset.
R3:Number of horizontal display characters
register(CR)
R4:Horizontal synchronous pulse width register(LPW)
(50 H )
(04 H )
R5:Cycle steal enable width register(CSW)
(04 H )
R6:Number of vertical lines register(SLT)
(78 H )
Set suitable value for LCD.
(Set these value only when register is initialized.)
#
R7:1st screen display start address register(SA1L)
(00 H )
Set lower address of 1st screen display start address.
#
R8:2nd screen display start address register(SA1H)
(00 H )
Set upper address of 1st screen display start address.
R11:M output frequency variable register(MT)
(07 H )
Set suitable value for LCD.
(Set MT only when register is initialized.)
Set gray scale pattern.
R17 to R80:Gray scale patternregister
Note ) When access to R17 to R80, must be set DISP=OFF.
Can't access to R17 to R80 on DISP=ON.
Discontinuous address
R12,R13 or R15:VRAM address indexregister
Set display data to VRAM.
Continuous address
R14 or R16:Data port register
N
Complete?
Y
#
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
(45 H )
Set DISP=ON.
Display start
Setting example suppose LCD size = 320x240dots and display mode 3 (Single scan,Gray scale, 4bit transfer).
# Can change R1(DISP,REV,LCDE),R7(SA1L),R6(SA1h) registers value during display on.
34