AGILENT HPFC-5000

hH
TACHYON*
Fibre Channel
Interface Controller
Product Overview
HPFC-5000
Description
TACHYON is a fundamental
building block compatible with
Hewlett-Packard’s Fibre Channel solution which includes
interface controllers, physical
link modules, adapters, switches
and disk drives.
The TACHYON architecture
supports both networking and
mass storage connections to
provide a low cost, high performance solution with low host
overhead.
DATA STRUCTURES IN THE HOST
SFS
INBOUND MFS
MESSAGE BUFFER BUFFER
QUEUE QUEUE QUEUE
INBOUND
DATA
INBOUND
BLOCK
MOVER
INBOUND
MESSAGE
CHANNEL
SCSI
EXCHANGE
STATE
TABLE
INBOUND
SFS & MFS
BUFFER
CHANNELS
* TACHYON (tak' - e - än)
1. a subatomic particle that only exists at
speeds faster than the speed of light.
2. HP’s Fibre Channel Interface chip.
OUTBOUND
DATA
BACKPLANE
INTERFACE
SCSI
READ/WRITE
CHANNEL
OUTBOUND
MESSAGE
CHANNEL
OUTBOUND
BLOCK
MOVER
FCP ASSISTS
SCSI
BUFFER
MANAGER
SCSI
EXCHANGE
MANAGER
Features
• Single chip Fibre Channel
interface (no I/O processor
required)
• Supports 1062.5, 531, and 266
MBaud links
• Supports 3 topologies; direct
connect, fabric, and Fibre
Channel Arbitrated Loop
(FC-AL)
• Supports Fibre Channel Class
1, 2, and 3 Services
• Supports up to 2-Kbyte frame
payload for all classes of service
• Sequence segmentation/
reassembly in hardware
HIGH
OUTBOUND PRIORITY
COMMAND COMMAND
QUEUE
QUEUE
INBOUND
DATA
MANAGER
INBOUND
SEQUENCE
MANAGER
INBOUND
DATA
FIFO
SEQUENCE MANAGEMENT
OUTBOUND
SEQUENCE
MANAGER
ACKs
ACKs
ACK
FIFO
OUTBOUND
FRAME
FIFO
TRANSMIT
RECEIVE
20B/16B
DECODER
10B/20B
DE-MUX
OS PROCESSOR/
CRC CHECKER
ELASTIC STORE/
SMOOTHING
BUFFER
OS/CRC
GENERATOR
LOOP/
N_PORT
STATE
MACHINE
GIGABIT LINK MODULE
Figure 1. TACHYON Internal Block Diagram
16B/20B
ENCODER
20B/10B
MUX
hH
Features (continued)
• Automatic ACK frame generation and processing
• On-chip support of FCP for
SCSI Initiators and Targets
• Supports up to 16,384 concurrent SCSI I/O transactions
• Compliant with Internet MIBII network management
• Direct interface to industry
standard 10 and 20-bit Gigabit Link Modules (GLM)
• Hardware assists for TCP/
UDP/IP networking
• Parity protection on internal
data path
• Eight internal DMA channels
• Full duplex internal architecture that allows TACHYON to
process inbound and outbound
data simultaneously
TACHYON
BACKPLANE
INTERFACE
GIGABIT
LINK MODULE
INTERFACE
GIGABIT
LINK
MODULE
PAR_ID [1:0]
TAD [31:0]
PARITY
RX [19:0]
AVCS_L
TYPE [2:0]
RBC
READY_L
RX
COM_DET
PREFETCH_L
BACKPLANE
RETRY_L
L_UNUSE
ERROR_L
LCKREF_L
INT_L
EWRAP
RESET_L
FAULT
TBR_L [1:0]
TX
TX [19:0]
TBG_L
SCLK
Specifications
System Clock Frequency:
24-40 MHz backplane
operation
Operating Temperature:
0-50°C @ 0 m/s airflow,
0-70°C @ 1.5 m/s airflow
Testability:
Full internal scan path. IEEE
Standard 1149.1 Boundary
Scan
Packaging:
208-pin metal quad flat pack
Standards:
Intended to be compliant with
ANSI standards and FCSI/
FCA profile definitions
SCAN TEST
INTERFACE
TBC
TDI
TXCLK_SEL
CLOCK
GENERATOR
TDO
TCK
LP2
TRST
RC
TMS
Figure 3. TACHYON Pin-out Block Diagram
For technical assistance or the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Americas/Canada: 1-800-235-0312 or
(408) 654-8675
BACKPLANE
INTERFACE
CHIP
GIGABIT
LINK
MODULE
TACHYON
CLK
Far East/Australasia: (65) 290-6305
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data Subject to Change
Copyright © 1996 Hewlett-Packard Co.
Printed in U.S.A. 5965-1215E (7/96)
Figure 2. System Adapter Card Block Diagram