CXB1586AR 10 Bit 1.0625 Gbaud Transceiver For the availability of this product, please contact the sales office. Description The CXB1586AR is a transceiver IC with a built-in PLL for Fibre Channel. For a receiver 1.0625 Gbaud serial data is received and output it as the 10-bit parallel data; for transmitter 1.0625 Gbaud 10bit parallel data is output as the serial data. Features • Transmitter and receiver in a single chip • ANSI X3T11 Fibre Channel compatible (FC_0) at 1.0625 Gbaud • Conforms to 10-bit interface specification • TTL / ECL compatible • Single +3.3 V power supply • • • • • PLL for clock generation and clock / data recovery Byte sync detector (positive character of comma) Local loop back circuit Low power consumption (0.8 W typ.) 64-pin plastic LQFP package (10 mm × 10 mm) 64 pin LQFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC –0.3 to 4 V • Operating temperature Topr –55 to +70 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD to 1109 mW Operating Conditions Supply voltage VCC 3.14 to 3.46 V Applications 1.0625 Gbaud Fibre channel Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E97319C83-TE LCKREF∗ Block Diagram LBEN CXB1586AR SDOUT TX0-9 10 10 Pin REFCLK (106.25M) D Q REFCLK TX_PLL Sout P/S Conv. SDOUT∗ LCLK (106.25M) TCLK (1.0625G) LPF_TX0 SDIN LPF_TX1 1 RDATA 0 RCLK (1.0625G) RX0-9 SDIN∗ PX_PLL LPF_RX0 1/10 10 S/P Conv. LPF_RX1 BYTSYNC BYTSYNCEN RBC1 1/2 RBC0 FCLK (106.25M) LPF_RX0 BYTSYNC VEET RX0 RX1 RX2 VCCT RX3 RX4 RX5 RX6 VCCT RX7 RX8 RX9 VEET Pin Configuration (Top View) 48 40 33 49 32 56 24 17 64 1 8 16 VEET TX0 TX1 TX2 VCCG TX3 TX4 TX5 TX6 VCCG TX7 TX8 TX9 VEET VEEP_TX LPF_TX0 LPF_RX1 VCCP_RX VEEP_RX SDIN∗ VCCE SDIN VCCG VEEG VCCG VEEG VCCG VCCE SDOUT∗ SDOUT VCCE VEEE —2— VEET RBC0 RBC1 VCCT VCCG LCKREF∗ TEST∗ VEEG BYTSYNCEN VCCG REFCLK VEEG VCCG LBEN VCCP_TX LPF_TX1 CXB1586AR DC Characteristics (under the recommended conditions) Item TTL high level input voltage TTL low level input voltage TTL high level input current TTL low level input current TTL high level output voltage TTL low level output voltage ECL high level input voltage ECL low level input voltage ECL peak-to-peak differential input voltage swing VCC–1.17 VCC–1.81 0.5 VCC–0.88 VCC–1.48 Unit V V µA µA V V V V VIS_E 1) 400 2000 mV ECL high level output voltage VOH_E VCC–1.05 VCC–0.81 V ECL low level output voltage VOL_E VCC–1.81 VCC–1.55 V VOS_E 2) 1200 1900 mV 320 1109 mA mW ECL peak-to-peak differential output voltage swing Current consumption Power dissipation Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T VIH_E VIL_E Min. 2 0 Typ. Max. 5.5 0.8 20 –400 2.2 ICC PD 250 825 Note : 1) ECL peak-to-peak differential input voltage swing 2) ECL peak-to-peak differential output voltage swing Voltage VCC signal-in+ VIH_E Vi1 Vi2 VIL_E signal-in– VEE=GND 1) VIS_E= |Vi1| + |Vi2| Voltage VCC signal-out+ VOH_E Vo1 VOL_E signal-out– VEE=GND 2) VOS_E= |Vo1| + |Vo2| —3— Vo2 Conditions Vin=VCC Vin=0 IOH=–0.4 mA IOL=2 mA AC coupling input 50 Ω terminated to VCC–2 V 50 Ω terminated to VCC–2 V Output pins open Output pins open CXB1586AR AC Characteristics Item TTL input rise time of TX TTL input fall time of TX TTL input rise time of REFCLK TTL input fall time of REFCLK (under the recommended operating conditions) Symbol Tir_TX Tif_TX Tir_REF Tif_REF Min. 0.7 0.7 0.7 0.7 Typ. Max. 4.8 4.8 2.4 2.4 Unit ns ns ns ns TTL output rise time Tor_T 3.5 ns TTL output fall time Tof_T 3.5 ns 400 400 9.56 60 100 ECL output rise time ECL output fall time REFCLK period REFCLK duty cycle REFCLK frequency tolerance TX setup time to REFCLK TX hold time to REFCLK RX setup time to RBC RX hold time to RBC Skew between RBC0 and 1 RBC duty cycle Tor_E Tof_E Tp_REF 9.26 DC_REF 40 Ftol_REF –100 Ts_TX 2 Th_TX 1.5 Ts_RX 3 Th_RX 1.5 Tsk_RBC Tp/2–0.5 DC_RBC 40 Tp/2 Tp/2+0.5 60 ps ps ns % ppm ns ns ns ns ns % 9.41 Deterministic jitter (p-p) DJ 0.02 0.07 UI Random jitter (p-p) Jitter tolerance RJ JT 0.18 0.23 0.7 UI UI —4— Conditions 0.8 V to 2.0 V 2.0 V to 0.8V 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 V to 2.0 V, CL=10 pF 2.0 V to 0.8 V, CL=10 pF 20 % to 80 %, CL=2 pF 20 % to 80 %, CL=2 pF Tp is period of RBC in frequency lock Serial data output (k28.5) Serial data output Serial data input CXB1586AR PLL AC Characteristics Item Frequency acquisition time of TX and RX PLL Bit synchronization time of RX PLL (under the recommended operating conditions) Symbol Min. Typ. Max. Unit Tfa 500 µs Tbs 2500 bit Absolute Maximum Ratings Item Power supply voltage (Except VCCT5) TTL DC input voltage ECL DC input voltage ECL peak-to-peak differential input voltage swing TTL output current (High level) TTL output current (Low level) ECL output current Ambient temperature Storage temperature Conditions Loop damping capacitor=0.01 µF (VEEE, VEET, VEEG, VEEP=GND) Symbol Min. VCC Typ. Max. Unit –0.3 4 V VI_T VI_E –0.5 VCC–2 5.5 VCC V V VIS_E –4 4 V IOH_T IOL_T IO_E Ta Tstg –20 0 –30 –55 –65 0 20 0 70 150 mA mA mA °C °C Remarks Under bias Recommended Operating Conditions Item Supply voltage (Including VCCT5) Ambient temperature Symbol Min. Typ. Max. Unit VCC 3.135 3.3 3.465 V Ta 0 70 °C —5— Remarks CXB1586AR Pin description Pin No. Symbol Type VEET PS TX0-9 I_TTL 1, 14, 32, 33, 46 2-4, 6-9, 11-13 5, 10, 20, 23, 28, 55, 57, 59 15 16 17 18 VCCG PS VEEP_TX LPF_TX0 LPF_TX1 VCCP_TX PS 19 LBEN I_TTL VEEG PS REFCLK I_TTL 24 BYTSYNCEN I_TTL 26 TEST∗ I_TTL 27 LCKREF∗ I_TTL 29, 37, 42 VCCT PS 30 31 RBC1 RBC0 O_TTL 34-36, 38-41, 43-45 RX0-9 O_TTL 47 BYTSYNC O_TTL 48 49 50 51 LPF_RX0 LPF_RX1 VCCP_RX VEEP_RX 21, 25, 56, 58 22 EX PS EX PS PS Description Equivalent circuit Ground for TTL output : Normally 0 V. — Parallel transmit data inputs to be serialized. TX0 is serialized first and TX9 is last. (a) Power supply for internal logic gates : Normally 3.3 V. — Ground for TX PLL : Normally 0 V. Connect to external loop filter of TX PLL. Connect a capacitor (0.01 µF) between LPF_TX0 and LPF_TX1. Power supply for TX PLL : Normally 3.3 V. Loop back enable : When high, TX serializer output internally connects to RX deserializer input, SDOUT/SDOUT∗ is held low/high, and SDIN/SDIN∗ is disabled. When low, SDOUT/SDOUT ∗ and SDIN/SDIN∗ are enabled. Power supply for internal logic gates : Normally 0 V. Reference clock for PLL and transmit byte clock (106.25 MHz). Supplied by the host system. Byte synchronization enable : When high, the positive comma character (0011111) detection circuit is enabled to establish byte synchronization (see Timing Chart). Test pin : Normally 3.3 V or open. Lock to reference clock : An active low input. LCKREF∗ forces the PLL lock to the REFCLK supplied by the host system. Power supply for TTL output : Normally 3.3 V. Receive byte clocks recovered from the serial data (53.125 MHz). These clocks are 180 degrees out of phase, and RX0-9 are alternatively clocked on the rising edge of these clocks (see Timing Chart) Parallel receive data output : RX0 is received first and RX9 is last. Byte synchronization indicator : High when a positive comma character is detected (see Timing Chart) Connect to external loop filter of RX PLL. Connect a capacitor (0.01 µF) between LPF_RX0 and LPF_RX1. Power supply for RX PLL : Normally 3.3 V. Ground for RX PLL : Normally 0 V. —6— — (e) — (a) — (a) (a) (a) (a) — (b) (b) (b) (e) — — CXB1586AR Pin No. Symbol Type 52 54 SDIN∗ SDIN I_ECL (Diff.) 53, 60, 63 VCCE PS 61 62 SDOUT∗ SDOUT O_ECL (Diff.) 64 VEEE PS Description Serial receive data inputs : These inputs are enabled when LBEN is low. Power supply for ECL output : Normally 3.3 V Serial transmit data output : These outputs are enabled when LBEN is low. When LBEN is high, SDOUT/SDOUT∗ is held to low/high. Ground for ECL output : Normally 0 V. Pin Type Definition Type PS I_TTL O_TTL I_ECL O_ECL EX Definition Power supply or ground Input TTL Output TTL Input ECL Output ECL External circuit node —7— Equivalent circuit (c) — (d) — CXB1586AR Equivalent Circuit VCCG VCCT3 TTL-OUT TTL-IN VEET VEET VEET (a) TTL input (b) TTL output VCCE VCCE VCCG ECL-IN ECL-OUT VCCE - 1.3V ECL-IN∗ ECL-OUT∗ VEEE VEEE VEEG (d) ECL output (c) ECL input VCCP LPF0 LPF1 VEEP2 VEEP1 (e) LPF0/LPF1-pin —8— CXB1586AR Timing Chart Tir_TX Tif_TX 2.0V TX_a 1.4V TX_b 0.8V TX0 - 9 Ts_TX Th_TX 2.0V 1.4V 0.8V REFCLK Tir_REF Tif_REF TX0_a TX1_a TX2_a TX3_a TX4_a TX5_a TX6_a TX7_a TX8_a TX9_a TX0_b TX1_b TX2_b SDOUT (a) Transmiter Section Timing Tskew 2.0V 1.4V HOLD 0.8V RBC0 Tor_T Tof_T 2.0V 1.4V HOLD 0.8V RBC1 Ts_RX Th_RX 2.0V COMMA (+) VALID DATA COMMA (+) VALID DATA VALID DATA 1.4V 0.8V RX0 - 9 Ts_RX Th_RX 2.0V 1.4V 0.8V BYTSYNC (b) Receiver Section Timing —9— CXB1586AR Notes on Operation 1. External loop filters for PLLs The CXB1586AR has two PLLs. One is for the transmitter and locks to the reference clock from REFCLK input pin. Another one is for the receiver and locks to the received serial data from SDIN/SDIN∗ input pins. They need external capacitors for the their loop filters. Typical values of the external capacitors are indicated below. C2 48 49 17 16 C1 : 0.01µF C2 : 0.01µF C1 2. Example of power supply circuit 3.3V A 22µF VCCT 0.1µF A 22µF VCCG VCCE 0.1µF VEEG VEEE VEET —10— A 22µF VCCP 0.1µF VEEP CXB1586AR 3. High-speed ECL differential input The high-speed ECL differential input pins are biased to VBB (VCC–1.3V) via a 18 kΩ resistor in the IC. See the figures below for ECL differential input methods. AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA VCC=3.3V, VEE=GND AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA 160Ω 160Ω 3.3V ECL output buffer 18kΩ 18kΩ VCC=3.3V, VEE=GND VBB (VCC–1.3V) ECL differential input buffer (a) ECL differential signal from 3.3V ECL output buffer 0.01µF 330Ω 330Ω ECL 100K output buffer 18kΩ 0.01µF 18kΩ VCC=3.3V, VEE=GND VBB (VCC–1.3V) VCC=GND, VEE=–4.5V ECL differential input buffer VEE (b) ECL differential signal from ECL 100K output buffer 75Ω TRANS. LINE 0.01µF 75Ω 75Ω 18kΩ 0.01µF 18kΩ VCC=3.3V, VEE=GND VBB (VCC–1.3V) ECL differential input buffer (c) differential signal from 75Ω transmission line (AC/DC termination) 0.01µF 75Ω TRANS. LINE 0.01µF 75Ω 75Ω 18kΩ 18kΩ VCC=3.3V, VEE=GND VBB (VCC–1.3V) ECL differential input buffer 0.01µF (d) differential signal from 75Ω transmission line (AC termination) —11— CXB1586AR AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA 50Ω TRANS. LINE 50Ω 0.01µF 50Ω VTT (VCC–2V) 18kΩ 0.01µF 18kΩ VCC=3.3V, VEE=GND VBB (VCC–1.3V) ECL differential input buffer (e) ECL differential signal from 50Ω transmission line 50Ω TRANS. LINE 50Ω VTT (VCC–2V) 0.01µF 18kΩ 0.01µF 18kΩ VCC=3.3V, VEE=GND VBB (VCC–1.3V) ECL differential input buffer (f) ECL single signal from 50Ω transmission line —12— CXB1586AR Electrical Characteristics Measurement Circuit II_T Device under test A TTL_IN TTL_OUT IO_T VI_T V VO_T (a) TTL I/O DC characteristics measurement circuit Device under test Probe Pulse generator TTL_IN Oscilloscope TTL_OUT CL CL=10pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E Device under test A ECL_IN ECL_OUT VI_TE 50Ω V VO_E VCCE–2V (c) ECL I/O DC characteristics measurement circuit VCCE–2V 50Ω 0.1µF Pulse generator VCCE–2V ECL_IN ECL_IN∗ 50Ω 50Ω Device under test ECL_OUT ECL_OUT∗ 50Ω 0.1µF VCCE–2V 50Ω Transmission line Oscilloscope VCCE–2V CL≤2pF (input capacitance of the measurement equipment and floating capacitance) (d) ECL I/O AC characteristics measurement circuit —13— CXB1586AR VCCE–2V 50Ω parallel data 10bit 0.1µF SDIN 531.25MHz Pulse pattern generator RX0-9 SDIN∗ 0.1µF 50Ω Device under test VCCE–2V Oscilloscope SDOUT 531.25MHz 50Ω SDOUT∗ REFCLK TX0-9 50Ω TRIG VCCE–2V VCCE–2V 106.25MHz (e) TX random jitter measurement circuit Attenuate VCCE–2V 50Ω 1.0625Gbps CLKOUT DATAOUT∗ Random pattern 2 ^ 7-1 or 2 ^ 23-1 Error rate counter RX0-9 SDIN DATAOUT CLKOUT∗ parallel data 10bit 0.1µF SDIN∗ 0.1µF 50Ω Device under test VCCE–2V DATAIN SDOUT CLKIN 50Ω 1.0625Gbps SDOUT∗ REFCLK TX0-9 50Ω VCCE–2V VCCE–2V Pulse pattern generator 106.25MHz (f) Error rate measurement circuit VCCE–2V CLKOUT Pulse pattern generator 50Ω 531.25MHz parallel data 10bit 0.1µF RX0-9 SDIN SDIN∗ 0.1µF 50Ω Jitter analyzer Device under test VCCE–2V CLKIN DATAOUT SDOUT 50Ω 531.25MHz SDOUT∗ REFCLK TX0-9 50Ω VCCE–2V VCCE–2V modulate 106.25MHz (g) TX jitter transfer measurement circuit —14— CXB1586AR Example of Representative Characteristics Example of TX Rj measurement (SDOUT) C1 = C2 = 0.01µF Rj = 9.6psec SDIN input 1.0625Gbps (Transition Density : 100%) REFCLK input 106.25MHz x : 30psec / div y : 100mV / div TX Eye Pattern (SDOUT 1.0625GHz operation) VOH_E VOL_E C1 = C2 = 0.01µF SDIN input 1.0625Gbps Random pattern REFCLK input 106.25MHz x : 200psec / div y : 200mV / div —15— CXB1586AR Input Template (Tx jitter transfer) Modulation amplitude (UIp-p) 10 1 10 0 10 –1 10 –2 10 100 1k 10k 100k 1M 10M 100M REFCLK modulation frequency (Hz) C1=C2=0.01µF Ta=27°C Tx Jitter Transfer 5.0 SDIN input 1.0625Gbps (transition density : 100%) SDOUT output 531.25MHz REFCLK input 106.25MHz Jitter Transfer (dB) 0.0 –5.0 –10.0 –15.0 –20.0 10 100 1k 10k 100k REFCLK modulation frequency (Hz) —16— 1M 10M 100M CXB1586AR C1=C2=0.01µF Ta=27°C Error rate 10–3 SDIN 1.0625Gbps Random pattern 2^7-1 Random pattern 2^23-1 SDOUT output 1.0625MHz REFCLK input 106.25MHz 10–4 input 10–5 Error rate 10–6 10–7 2^7-1 2^23-1 10–8 10–9 10–10 10–11 6.0 7.0 8.0 9.0 SDIN-Vin (mV) —17— 10.0 11.0 CXB1586AR Unit : mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 + 0.08 0.18 – 0.03 16 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE —18—