CXB1583Q 266Mbaud Fibre Channel Transceiver IC For the availability of this product, please contact the sales office. Description The CXB1583Q is a transceiver IC with the built-in PLLs into a single chip. For receiver, the 265.625Mbaud serial data is received and it is output as a 10-bit parallel data; for transmitter, the 265.625Mbaud 10-bit parallel data is received and it is output as a serial data after conversion. 80 pin QFP (Plastic) Applications 265.625Mbaud fibre channel VCCG VEEG SDIN SDIN∗ VCCE VEEE TXSOUT TXSOUT∗ ECK∗ ECK Structure Bipolar silicon monolithic IC VCCP LPFA LPFB VEEP1 REXT VEEP2 TJMON LPFC LPFD Pin Configuration LCKREF∗ Features • Transmitter/receiver into a single chip • Conforms to ANSI X3T11 fibre channel standard • PLL for a clock synthesizing and for clock recovery • Single 3.3V power supply • Low power consumption: 860mW (Typ.) • 80-pin plastic package • Comma signal detector • Test pattern (±K28.5) generation circuit • Loop-back circuit • Supports data rage of 200Mbaud 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 MS1 SDOUT 61 SDOUT∗ 62 39 MS0 VCCE 63 38 CDETENB VEEE 64 37 VCCT 36 POR∗ TXSIN 65 TXSIN∗ 66 35 TXLKDT LOL 67 34 RXLKDT VEEG 68 33 VEET VCCG 69 32 PCLKOUT0 ECKENB∗ 70 31 PCLKOUT1 VEEG 71 30 VEEG VCCG 72 29 VCCG LPBK 73 ALTENB∗ 74 TPGEN∗ 75 27 PDO9 28 CDET 26 PDO8 25 VEET TXSER 76 24 PDO7 REFCLK 77 PDI7 PDI8 PDO6 PDI6 VEET PDI5 PDO5 9 10 11 12 13 14 15 16 17 18 19 20 PDO4 8 PDO3 7 VCCT 6 PDO2 5 VEET 4 PDO1 3 PDO0 2 PDI9 1 PDI4 21 VEEG PDI3 22 VCCG VEEG 80 PDI2 VCCG 79 PDI1 23 VCCT PDI0 VEET 78 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96501-ST CXB1583Q Absolute Maximum Ratings Item (VEEE, VEET, VEEG, VEEP = 0V) Symbol Min. Typ. Max. Unit Power supply VCC –0.3 4 V TTL DC input voltage VI_T –0.5 5.5 V ECL DC input voltage VI_E VCC – 2 VCC V ECL differential input voltage VIS_E –2 2 V TTL output current (high level) IOH_T –20 0 mA TTL output current (low level) IOL_T 0 20 mA ECL output current IO_E –30 0 mA Operating ambient temperature Ta –55 70 °C Storage temperature Tstg –65 150 °C Recommended Operating Conditions Item (VEEE, VEET, VEEG, VEEP = 0V) Symbol Min. Typ. Max. Unit 3.3 3.465 V 70 °C Supply voltage VCC 3.135 Ambient temperature Ta 0 –2– CXB1583Q TXSIN∗ TXSIN TXSER TPGEN∗ Block Diagram TXSOUT TXSOUT∗ 10 10 D Q PDI (0 to 9) 26.6Mbps K28.5 Gen. 1 0 Pin Sout P/S 0 1 SDOUT SDOUT∗ ALTENB∗ TXCLK (26.6MHz) REFCLK (26.6MHz) REFCLK TXLOAD (266MHz) TX_PLL TXLKDT LPBK LPFA SDIN LPFB RTDATA REXT RX_PLL 1 0 SDIN∗ RXCLK (266MHz) RPCLK (26.6M) VEEP 10 PDO (0 to 9) 26.6Mbps LOL S/P CDET RXLKDT PCLKOUT0 –3– LCKREF∗ LPFD LPFC CDETENB PCLKOUT1 CXB1583Q Pin Description Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 1 to 10 PDI0 to 9 TTL input TTL level Parallel data input. TTL-IN VEET VEEG VCCT 11, 12, 14, 16, TTL 17, 19, PDO0 to 9 output 20, 24, 26, 27 TTL-OUT TTL level Parallel data output. VEET 13, 18, 25, 33, VEET 78 Power supply 0V — Negative power supply for TTL input/output. 15, 23, VCCT 37 Power supply 3.3V — Positive power supply for TTL output. 21, 30, 42, 68, VEEG 71, 80 Power supply 0V — Negative power supply for internal logic gate. 22, 29, 41, 69, VCCG 72, 79 Power supply 3.3V — Positive power supply for internal logic gate. VCCT 28 CDET TTL output TTL-OUT TTL level VEET –4– Byte synchronization output. Outputs high level when +Comma (0011111) or –Comma (1100000) is detected to the serial data. CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCT 32 PCLKOUT0 TTL output TTL-OUT TTL level Receive byte clock 0 output. This clock is used to take the parallel data (PDO0 to 9) at the next-stage system. VEET VCCT 31 TTL PCLKOUT1 output TTL-OUT TTL level Receive byte clock 1 output. PCLKOUT0 inverted clock. VEET VCCT 34 RXLKDT TTL output TTL-OUT TTL level VEET VCCT 35 TXLKDT TTL output TTL-OUT TTL level VEET –5– RX_PLL lock detection signal output. Outputs high level when the PLL is locked to the serial data or the serial data has no signal; Outputs low level when the PLL is not locked. RXLKDT output may sporadically go high when the PLL starts to lock to the serial data. TX_PLL lock detection signal output. Outputs high level when the PLL is locked to REFCLK and operating normally; Outputs low level when the PLL is not operating normally. CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCT 36 POR∗ TTL output TTL-OUT TTL level Power-on reset signal output. Outputs high level after the power is turned on and low level is held for approximately 100ns. VEET VCCG 38 CDETENB TTL input TTL level TTL-IN VEET VEEG Byte synchronization enable signal input. When high level is input, +Comma (0011111) or –Comma (1100000) is detected and the parallel data is synchronized with this byte. (See the Timing Chart.) When low level is input, byte synchronization is not performed. VCCG 39, 40 MS0, MS1 TTL input 3.3 V or TTL high level Test pin. Connect to Vcc. TTL-IN VEET VEEG VCCE 43, 44 SDIN SDIN∗ ECL input (differential) VCCG ECL-IN ECL level VCCE – 1.3V Serial data input. ECL-IN∗ VEEE VEEG 45, 63 VCCE Power supply 3.3V — Positive power supply for ECL input/output. 46, 64 VEEE Power supply 0V — Negative power supply for ECL input/output. –6– CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCE 47, 48 ECL TXSOUT output TXSOUT∗ (differential) ECL-OUT ECL level ECL-OUT∗ Parallel/serial conversion output. This output is enabled when TXSER is high. VEEE VCCE 49, 50 ECK ECK∗ One is left ECL open; another output is connected (differto Vcc via ential) 47kΩ. VCCG ECL-IN VCCE – 1.3V ECL-IN∗ VEEE 51 VCCP Power supply Test pin. Connect either of these pins to Vcc via a 47kΩ resistor. VEEG 3.3V Positive power supply for internal PLL. — VCCP 52, 53 LPFA LPFB External part connection LPF_C RX_PLL external loop filter connection. (See Fig. 1 of the Notes on Operation.) LPF_D — VEEP2 54, 55 VEEP1 VEEP2 Power supply VEEP1 Negative power supply for internal PLL. — 0V VCCP 56 REXT External part connection — REXT VEEP2 –7– Connects the resistor which determines the VCO center frequency. (See Fig. 1 of the Notes on Operation.) CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCP 57 TJMON Test pin TJMON Junction temperature measurement. 0V VEEE2 VCCP 58, 59 LPFC LPFD External part connection LPF_C TX_PLL external loop filter connection. (See Fig. 1 of the Notes on Operation.) LPF_D — VEEP2 VEEP1 VCCG 60 LCKREF∗ TTL input TTL level Lock-to-reference signal input. When this pin is set to low level, RX_PLL is forcibly locked to REFCLK. TTL-IN VEET VEEG VCCE 61, 62 SDOUT SDOUT∗ ECL output (differential) ECL-OUT ECL level ECL-OUT∗ VEEE –8– Serial data output for transmission. The serial data order is PDI0 → PDI9. CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit VCCE 65, 66 TXSIN TXSIN∗ ECL input (differential) VCCG ECL-IN ECL level VCCE – 1.3V ECL-IN∗ VEEE LOL ECL input Open or ECL (single level phase) Serial ECL data input. When TXSER is high, this input signal is output from SDOUT. VEEG VCCE 67 Description VCCG ECL-IN VCCE – 1.3V VEEE Lost-of-light signal input. Low level when this pin is left open. VEEG VCCG 70 ECKENB∗ TTL input 3.3V or TTL high level Test pin. TTL-IN VEET VEEG VCCG 73 LPBK TTL input TTL level TTL-IN VEET VEEG –9– Loop-back enable. If LPBK is set to high, the signal output from SDOUT when LPBK is low is transmitted to the RX input with the internal connection. In this time, SDOUT/ SDOUT∗ are fixed to low/high respectively and SDIN/SDIN∗ are both disabled. CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 74 ALTENB∗ TTL input TTL level TTL-IN VEET VEEG Alternate disparity test pattern generation enable. When ALTENB∗ is set to low with TPGEN∗ low, K28.5 (+K28.5, –K28.5) is generated for the data stream output. When this pin is high, +K28.5 is generated. VCCG 75 TPGEN∗ TTL input TTL level Test pattern generation enable. When this pin is low, +K28.5 (ALTENB∗: high) or ±K28.5 (ALTENB∗: low) is generated for the data stream output. TTL-IN VEET VEEG VCCG 76 TXSER TTL input TTL level Transmit serial data selector. When this pin is high, the serial data input from TXSIN is output from SDOUT and the serialized PDI0 to 9 signals are output from TXSOUT. TTL-IN VEET VEEG VCCG 77 REFCLK TTL input TTL level TTL-IN VEET VEEG – 10 – Transmit byte clock. This clock is used to take the PDI0 to 9 signals in the TXPLL. The RXPLL takes the frequency from REFCLK when LCKREF∗ is low. REFCLK is necessary after LCKREF∗ is set to high and the RXPLL is locked to the serial data. CXB1583Q CXB1583Q Functions 1. Data map to the 8b/10b alphabet notation PDI0 is the start bit. PDI, PDO 8b/10b alphabet notation 0 1 2 3 4 5 6 7 8 9 a b c d e i f g h j 2. COMMA DETECT When CDETENB is high and the SDIN input data row includes K28.5, PDO0 to 9 are synchronized with K28.5 and output. Byte synchronization is also performed to ±Comma. PDO0 a b c d e i f g h PDO9 j +K28.5 0 0 1 1 1 1 1 0 1 0 Comma (positive) 0 0 1 1 1 1 1 X X X Comma (negative) 1 1 0 0 0 0 0 X X X –K28.5 1 1 0 0 0 0 0 1 0 1 Serial Data 3. TXSER, LPBK operation modes Input TXSER Output LPBK TXSOUT SDOUT PDO0 to 9 Low Low Disabled/Static Serialized PDI SDIN Low High Disabled/Static Disabled/Static PDI High Low Serialized PDI TXSIN SDIN High High Serialized PDI Disabled/Static TXSIN 4. LCKREF∗ operation modes LCKREF input level RXPLL comparison signal High SDIN, SDIN∗ Low REFCLK 5. CDETENB CDETENB input level Operation High Byte synchronization with the Comma signal Low Byte synchronization function stop – 11 – CXB1583Q Electrical Characteristics DC Characteristics (under the recommended operating conditions) Item Symbol Min. Typ. Max. Unit Conditions TTL high level input voltage VIH_T 2 5.5 V TTL low level input voltage VIL_T 0 0.8 V TTL high level input current IIH_T 20 µA VIH = VCC TTL low level input current IIL_T –400 µA VIL = 0 2.2 V IOH = –0.4mA 0.5 V IOL = 2mA TTL high level output voltage VOH_T TTL low level output voltage VOL_T ECL high level input voltage VIH_E VCC – 1.17 VCC – 0.88 V ECL low level input voltage VIL_E VCC – 1.81 VCC – 1.48 V ECL differential input voltage VIS_E 200 1000 mV AC coupling input ECL high level output voltage VOH_E VCC – 1.05 VCC – 0.81 V 50Ω terminated to Vcc – 2 V ECL low level output voltage VOL_E VCC – 1.81 VCC – 1.55 V 50Ω terminated to Vcc – 2 V mV 50Ω terminated to Vcc – 2 V ECL output amplitude VOS_E 650 Current consumption ICC 260 341 mA Output pins open Power consumption PD 0.86 1.18 W Output pins open – 12 – CXB1583Q AC Characteristics (under the recommended operating conditions) Item Symbol Min. Typ. Max. Unit Conditions PDI rise time Tir_PDI 10 ns 0.8 to 2.0V PDI fall time Tif_PDI 10 ns 2.0 to 0.8V REFCLK rise time Tir_RFCK 0.375 5 ns 0.8 to 2.0V REFCLK fall time Tif_RFCK 0.375 5 ns 2.0 to 0.8V TTL output rise time Tor_T 5 ns 0.8 to 2.0V, CL = 10pF TTL output fall time Tof_T 5 ns 2.0 to 0.8V, CL = 10pF ECL output rise time Tor_E 500 ps 20 to 80%, CL = 2pF ECL output fall time Tof_E 500 ps 20 to 80%, CL = 2pF SDIN data rate R_SDIN 190 280 Mbaud REFCLK cycle tolerance Ttol_RFCK –200 200 ppm REFCLK duty cycle DC_RFCK 40 60 % PCLKOUT0 and 1 skew Tskew –3 3 ns PDI setup time Ti_s 4 ns REFCLK reference PDI hold time Ti_h 3 ns REFCLK reference PDO setup time To_s 10 ns PCLKOUT0 reference PDO hold time To_h 12 ns PCLKOUT0 reference TX deterministic jitter (p-p) DJ 0.08 UI Serial data output TX random jitter (p-p) RJ 0.15 UI Serial data output RX jitter tolerance JT 0.7 UI Serial data input 0 SDIN cycle reference PLL AC Characteristics (under the recommended operating conditions) Item Symbol Min. Typ. Max. Unit Conditions Loop damping capacitance = 0.01µF TX/PX PLL frequency acquisition time Tfa 500 µs RX PLL bit synchronization time Tbs 2500 bit – 13 – CXB1583Q Timing Chart for TX 2.0V 1.5V 0.8V Tir_RFCK REFCLK Ti_s Tif_RFCK Ti_h 2.0V VALID VALID 1.5V 0.8V PDI0 to 9 Tir_PDI Tif_PDI Timing Chart for RX 1.5V Tskew PCLKOUT1 Th_PCK Tl_PCK 2.2V 1.5V 0.6V Tor_PCK PCLKOUT0 To_s Tof_PCK To_h 2.2V VALID VALID 0.6V PDO0 to 9 Tor_PDO Tof_PDO – 14 – CXB1583Q Electrical Characteristics Measurement Circuit (See “Fig. 3 Power Supply Circuit” regarding the power supply.) II_T A Measurement device TTL_IN TTL_OUT VI_T V VO_T IO_T (a) TTL I/O DC characteristics measurement circuit Measurement device Pulse generator TTL_IN Probe TTL_OUT Oscilloscope CL CL = 10 pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E A Measurement device ECL_IN ECL_OUT VI_TE 50Ω V VO_E VCCE – 2V (c) ECL I/O DC characteristics measurement circuit VCCE – 2V 50Ω VCCE – 2V Measurement device ECL_IN ECL_IN∗ Pulse generator 50Ω ECL_OUT ECL_OUT∗ Oscilloscope 50Ω 50Ω VCCE – 2V VCCE – 2V 50Ω Transmission Line C ≤ 2 pF (input capacitance of the measurement equipment and floating capacitance) (d) ECL I/O AC characteristics measurement circuit VCCE – 2V Measurement device Triger 6.640625MHz 50Ω SDIN Pulse pattern generator 265.625MBPS SDIN∗ SOUT SOUT∗ Oscilloscope 265.625Mbps 50Ω VCCE – 2V (e) Jitter characteristics measurement circuit – 15 – CXB1583Q Notes on Operation 1. Clock synthesizer (PLL) The CXB1583Q has a PLL-based clock synthesizer for generating the serial data transfer frequency (transmission bit clock) and clock recovery circuit for recovering the clock from the reception serial data. These circuits require the external loop filters and external resistors which determine the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the pins which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. 53 52 R1 58 56 R2 R5 59 R3 C1 R4 C2 C1 : 0.01µF C2 : 0.01µF R1 : 1.8kΩ R2 : 1.8kΩ R3 : 2.0kΩ R4 : 2.0kΩ R5 : 2.2kΩ Fig. 1. External Part Circuit and Recommended Constants – 16 – CXB1583Q 2. ECL input circuit The ECL differential input pins are biased to VBB (VCC – 1.3 V) via an 18kΩ resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 18kΩ 82Ω 82Ω 3.3V ECL output buffer ECL differential input buffer (a) ECL differrential signal from 3.3V ECL output buffer VCC = 3.3V, VEE = GND VCC = GND, VEE = –4.5V VBB (VCC – 1.3V) 0.01µF 0.01µF 330Ω ECL100K output buffer 18kΩ 18kΩ 330Ω ECL differential input buffer VEE (b) ECL differrential signal from ECL 100K output buffer VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 50Ω TRANS. LINE 50Ω 0.01µF 18kΩ 0.01µF 18kΩ 50Ω ECL differential input buffer VTT (VCC – 2V) (c) ECL differrential signal from 50Ω transmission line VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 0.01µF 50W TRANS. LINE 50Ω 0.01µF 18kΩ 18kΩ VTT (VCC – 2V) ECL differential input buffer (d) ECL single signal from 50Ω transmission line Fig. 2. ECL Input Circuits – 17 – CXB1583Q 3. Example of power supply circuit VCCG VCCE VCCT 3.3V 22µF 0.1µF 22µF 0.1µF VCCP 22µF VEEG VEEE VEET 0.1µF VEEP Fig. 3. Example of power supply circuit 4. Power-on reset signal (POR∗) The CXB1583Q has the power-on reset signal (POR∗). This signal functions as a system reset signal when the power is turned on, the low level of signal is output for approximately 100ns and then the high level results. Tpor POR∗ Output Power On Fig. 4. Power-on reset signal – 18 – CXB1583Q Example of Representative Characteristics [ 100mV/div ] Example of Rj measurement (RX recovered clock, 266MHz operation) TX input (PDI0 to 9): Random data RX input (SDIN): ±K28.5 Ta = 27°C Rj = 26.3ps (RMS) [ 100ps/div ] [ 100mV/div ] Example of Rj measurement (RX recovered clock, 200MHz operation) TX input (PDI0 to 9): Random data RX input (SDIN): ±K28.5 Ta = 27°C Rj = 36.9ps (RMS) [ 100ps/div ] – 19 – CXB1583Q [ 100mV/div ] Example of Rj measurement (SDOUT, 266Mbps operation) TX input (PDI0 to 9): Random data Ta = 27°C Rj = 17.6ps (RMS) [ 100ps/div ] [ 100mV/div ] Example of Rj measurement (SDOUT 200Mbps operation) TX input (PDI0 to 9): Random data Ta = 27°C Rj = 24.3ps (RMS) [ 100ps/div ] – 20 – CXB1583Q [ 200mV/div ] Eye pattern (TX SDOUT, 266Mbps operation) Ta = 27°C [ 1ns/div ] [ 200mV/div ] Eye pattern (TX SDOUT, 200Mbps operation) Ta = 27°C [ 1ns/div ] – 21 – CXB1583Q [ 200mV/div ] Eye pattern (RX retimed data, 266Mbps operation) Ta = 27°C [ 1ns/div ] [ 200mV/div ] Eye pattern (RX retimed data, 200Mbps operation) Ta = 27°C [ 1ns/div ] – 22 – CXB1583Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 0.1 41 40 80 21 (15.0) 61 + 0.15 0.3 – 0.1 20 ± 0.12 M 0° to 10° 0.5 ± 0.2 1 0.65 + 0.15 0.1 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-80P-L03 LEAD TREATMENT EIAJ CODE LQFP080-P-1414 LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.6g JEDEC CODE – 23 –