CXB1582Q Fibre Channel Receiver Description The CXB1582Q is a receiver IC with a built-in PLL clock recovery circuit for high-speed serial data reception. It can be used together with the transmitter IC CXB1581Q as a chip set, and 1062.5Mbaud, 20bit or 531.25Mbaud, 10-bit operation can be selected. 80 pin QFP (Plastic) Applications Fibre channel 1062.5Mbaud and 531.25Mbaud communications VEEG VCCG VCCE SDIN SDIN∗ LBIN LBIN∗ EXCLK VCCP REXT Structure Bipolar silicon monolithic IC VEEP1 VEEP2 LPF_A LPF_B PTEST VEEE TJMON VCCE SOUT∗ Pin Configuration SOUT Features • Conforms to ANSI X3T11 Fibre channel standard • Supports GLM (Gigabaud Link Module) interface • Built-in low-jitter PLL clock recovery circuit • Single 3.3V power supply or dual 3.3V/5V power supply (for 5V TTL interface) operation can be selected. • Low power consumption: 910mW (Typ.) when operating with a single 3.3V power supply • 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit operation can be selected. • PLL lock detection circuit • Power-on reset signal output circuit 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VEEG 61 40 ECLKSEL∗ VCCG 62 39 PDTEST LBEN 63 38 SSEL0 SHD 64 LCKREF∗ 65 37 SSEL1 ∗ 36 LKDT SYNCEN 66 35 SYNC SDRSEL 67 34 RBC1 PPSEL 68 33 RBC0 32 VEET REFCLK 69 31 VCCT5 RTCAP 70 POR∗ 71 30 VCCT3 VCCT5 72 29 VEET VCCT3 73 28 RX0 VEET 74 27 RX1 VEEG 75 26 VEEG RX4 RX5 RX11 VEET 9 10 11 12 13 14 15 16 17 18 19 20 RX6 8 RX7 7 VCCT5 6 VCCT3 5 RX8 4 RX9 3 RX10 2 VEET 1 RX12 21 RX3 RX13 RX17 80 VCCT5 22 RX2 VCCT3 23 VCCT3 RX18 79 RX14 RX19 78 RX15 24 VCCT5 VEET 25 VCCG VCCG 77 RX16 VCCG 76 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95930-ST CXB1582Q Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V) Item Symbol Max. Unit –0.3 4 V VCCG – 2, or –0.3 VCCG + 5, or 5.5 V Min. Typ. Supply voltage (excluding VCCT5) VCC Supply voltage for TTL output VCCT5 TTL DC input voltage VI_T –0.5 5.5 V ECL DC input voltage VI_E VCC – 2 VCC V ECL differential input voltage VIS_E –2 2 V TTL output current (High level) IOH_T –20 0 mA TTL output current (Low level) IOL_T 0 20 mA ECL output current IO_E –30 0 mA Operating ambient temperature Ta –55 70 °C Storage temperature Tstg –65 150 °C Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V) During single 3.3V power supply operation Item Symbol Min. Typ. Max. Unit 3.3 3.465 V 70 °C Supply voltage (including VCCT5) VCC 3.135 Ambient temperature Ta 0 During dual 3.3V/5V power supply operation (VCCT3 open) Item Symbol Min. Typ. Max. Unit Supply voltage (excluding VCCT5) VCC 3.135 3.3 3.465 V Power supply for TTL output VCCT5 4.75 5 5.25 V Ambient temperature Ta 70 °C –2– 0 CXB1582Q PPSEL SSEL1 ECL Output Selector SHD LBEN SSEL0 Block Diagram SDIN/SDIN∗ LBIN/LBIN∗ 0 1 SOUT/SOUT∗ 53.125Mbaud DFF S/P Converter 20 Data Output Controll 531.25 or 1062.5MHz RX00 to 09 10 10 53.125Mbaud Byte Sync RX10 to 19 53.125MHz SYNC 53.125MHz REFCLK PLL RBC0 Parallel Clock Generator LPF_A 1 0 RBC1 LPF_B LKDT∗ REXT SYNCEN ECLKSEL∗ SDRSEL LCKREF∗ EXCLK –3– Power On Reset Output Generator POR∗ RTCAP CXB1582Q Pin Description Pin No. Symbol 1, 10, 19, 29, VEET 32, 74 Type Typical pin I/O voltage Equivalent circuit Power supply 0V — Description Negative power supplies for TTL output. VCCT5 78 to 80, RX19 to RX17, 2 to 4, RX16 to RX14, 7 to 9, RX13 to RX11, 11 RX10 12 RX09, 13, RX08, 16 to 18, RX07 to RX05, 20 to 22, RX04 to RX02, 27 RX01, 28 RX00 VCCT3 TTL output TTL level RX10 to 19 Parallel data outputs (Byte_1). VEET VCCT5 VCCT3 TTL output TTL level RX00 to 09 Parallel data outputs (Byte_0). The first data of the serial data is RX00 and the last data is RX19 (RX09 during 531Mbaud mode). VEET VCCT5 5, 14, 23, 30 VCCT3 73 VCCT3 Power 3.3V or open supply VCCG VEET Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; leave open when using the IC with a dual 3.3V/5V power supply. VCCT5 6, 15, 24, 31 VCCT5 72 Power supply VCCT5 3.3V or 5V VCCG VEET –4– Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; to 5V when using the IC with a dual 3.3V/5V power supply. CXB1582Q Pin No. Type Typical pin I/O voltage Equivalent circuit Description 25, 42, 62, 76, VCCG 77 Power supply 3.3V — Positive power supplies for internal logic gate. 26, 41, VEEG 61, 75 Power supply 0V — Negative power supplies for internal logic gate. Symbol VCCT5 VCCT3 33 RBC0 TTL output TTL level RBC0 Receive byte clock 0 output. This clock is used when loading parallel data (RX00 to RX19) using the system in the next stage. VEET VCCT5 VCCT3 34 RBC1 TTL output TTL level RBC1 Receive byte clock 1 output. Inverse of the RBC0 clock. VEET VCCT5 VCCT3 35 SYNC TTL output TTL level SYNC VEET –5– Byte sync output. This pin outputs high level when +Comma (0011111) or –Comma (1100000) is detected in the serial data. (See the Timing Charts.) CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCT5 VCCT3 36 LKDT∗ TTL output PLL lock detection signal output. This pin outputs low level when the PLL is locked to the serial data and high level when the PLL becomes unlocked. LKDT∗ TTL level VEET VCCG 37 38 SSEL1 SSEL0 TTL input TTL level SOUT/SOUT∗ output signal selection. (See Table 1.) SSEL0 SSEL1 VEET VEET VCCG 39 PDTEST TTL input 0V Test. Connect to VEEG. PDTEST VEET VEET VCCG 40 TTL ECLKSEL∗ input TTL high level or 3.3V External clock selection. When this pin is set to low level, the clock input to EXCLK is used as the bit rate clock. ECLKSEL∗ VEET VEET –6– CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit VCCE 43 44 SDIN∗ SDIN ECL input (differen -tial) VCCG SDIN VCCE – 1.3V ECL level SDIN∗ VEEE 45, 58 VCCE Power supply 46 47 LBIN∗ LBIN 3.3V VCCG LBIN VCCE – 1.3V ECL level LBIN∗ VCCG VCCE – 1.3V EXCLK EXCLK ECL level VEEE 49 VCCP Power supply Serial data inputs for loop-back test. These input pins are enabled when LBEN is set to high level. VEEG VCCE ECL input Positive power supplies for ECL I/O. — VEEE 48 Serial data inputs. These input pins are enabled when SHD is set to low level. VEEG VCCE ECL input (differen -tial) Description VEEG Positive power supply for internal PLL. — 3.3V External clock input. When ECLKSEL∗ is set to low level, the clock input to this pin is used as the bit rate clock. This pin is biased to become low level when left open. VCCP 50 REXT External part connec -tion pin — REXT VEEP2 Connects the resistor which determines the VCO center frequency. Connect a 4.7kΩ resistor between this pin and VEEP1. (See Notes on Operation and Fig. 1.) 51 VEEP1 Power supply 0V — Negative power supply for internal PLL. 52 VEEP2 Power supply 0V — Negative power supply for internal PLL. –7– CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCP 53 LPF_A External part connec -tion pin LPF_A External loop filter connection. (See Notes on Operation and Fig. 1.) LPF_B — VEEP2 VEEP1 VCCP 54 LPF_B External part connec -tion pin LPF_A External loop filter connection. (See Notes on Operation and Fig. 1.) LPF_B — VEEP2 VEEP1 VCCE VCCG TJMON 55 PTEST TTL input Test. Connect to VEEP1. 0V PTEST VEEE VEEG VCCE VCCG TJMON 56 TJMON Test pin Junction temperature measurement. Connect to VEEP. 0V PTEST VEEE 57 VEEE Power supply VEEG 0V — –8– Negative power supply for ECL I/O. CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCE 59 60 SOUT∗ SOUT ECL output (differen -tial) SOUT ECL level SOUT∗ High-speed signal monitor. The monitored signal can be selected with SSEL0/1. (See Table 1.) VEEE VCCG 63 LBEN TTL input TTL level Loop-back enable. When this pin is set to high level, LBIN functions as a serial data input. LBEN VEET VEET VCCG 64 SHD TTL input TTL level Serial data input shutdown. When this pin is set to high level, the serial data is fixed to low level regardless of the signal input to SDIN. SHD VEET VEET VCCG 65 LCKREF∗ TTL input TTL level Lock-to-reference signal input. Setting this pin to low level forcibly locks the PLL to REFCLK. LCKREF∗ VEET VEET –9– CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 66 SYNCEN TTL input TTL level SYNCEN VEET VEET Byte sync enable signal input. When this pin is set to high level, +Comma (0011111) or –Comma (1100000) is detected and the parallel data is synchronized to this byte. (See the Timing Charts.) When this pin is set to low level, byte synchronization is not performed. VCCG 67 SDRSEL TTL input TTL level Serial data rate selection. Setting this pin to low level selects 531.25Mbaud mode and to high level selects 1.0625Gbaud mode. SDRSEL VEET VEET VCCG 68 PPSEL TTL input TTL level PPSEL VEET VEET – 10 – Ping-Pong mode selection. When this signal is set to high level during 1.0625Gbaud mode (SDRSEL = high), parallel data is output during PingPong mode. In other words, byte 0 is output in sync with the rise of RBC0, and byte 1 with the rise of RBC1. (See the Timing Charts.) CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 69 REFCLK TTL input TTL level REFCLK VEET VEET VCCG 70 RTCAP External part connec -tion pin Reference clock input. This pin is used for PLL frequency pull-in. Input the clock with 1/20 frequency of the serial data rate during 1.0625Gbaud mode or with 1/10 frequency of the serial data rate during 531.25Mbaud mode (around 53.125MHz in either case). VCCT5 RTCAP — VEEG Connects the capacitor which determines the POR∗ (power-on reset signal) low time. (See Notes on Operation and Fig. 4.) VEET VCCT5 VCCT3 71 POR∗ TTL output POR∗ TTL level VEET – 11 – Power-on reset signal output. When the power is turned on, POR∗ maintains low level for approximately 100ns and then goes to high level. (See Notes on Operation and Fig. 4.) CXB1582Q SOUT/SOUT∗ SSEL0 SSEL1 0 0 Non Retimed Serial Data. 1 0 Retimed Serial Data. 0 1 Recovered Bit Rate Clock 1 1 Testing output. Fixed to low. Table 1. Monitor Output (SOUT) Selection Table – 12 – CXB1582Q Timing Charts VTH_H 1.5V VTH_L RBC0 Tof_T Tor_T Tskew RBC1 Ts Th Ts Th VTH_H COMMA CHARACTER 1.5V Valid VTH_L RX00 to 19 or RX00 to 09 during Ping-Pong mode Tof_T Tor_T VTH_H 1.5V VTH_L SYNC Ts Th VTH_H Valid Valid 1.5V VTH_L RX10 to 19 during Ping-Pong mode Tof_T Tor_T During single 3.3V power supply operation: VTH_L = 0.8V, VTH_H = 2.0V During dual 3.3V/5.0V power supply operation: VTH_L = 0.6V, VTH_H = 2.2V – 13 – CXB1582Q Electrical Characteristics DC Characteristics (under the recommended operating conditions) Item Symbol Min. Typ. Max. Unit Conditions TTL high level input voltage VIH_T 2 5.5 V TTL low level input voltage VIL_T 0 0.8 V TTL high level input current IIH_T 20 µA VIH = VCC TTL low level input current IIL_T –400 µA VIL = 0 2.2 V IOH = –0.4mA 2.6 V IOH = –0.4mA 0.5 V IOL = 2mA 0.5 V IOL = 4mA TTL high level output voltage Single 3.3V power supply VOH-T Dual 3.3V/5V power supply TTL low level output voltage Single 3.3V power supply VOL_T Dual 3.3V/5V power supply ECL high level input voltage VIH_E VCC – 1.17 VCC – 0.88 V ECL low level input voltage VIL_E VCC – 1.81 VCC – 1.48 V 200 1000 mV VOH_E VCC – 1.05 VCC – 0.81 V 50Ω terminated to VCC – 2V ECL low level output voltage VOL_E VCC – 1.81 VCC – 1.55 V 50Ω terminated to VCC – 2V mV 50Ω terminated to VCC – 2V ECL differential input voltage VIS_E ECL high level output voltage ECL output amplitude VOS_E 650 Output pins open Current consumption Single 3.3V power supply ICC Dual 3.3V/5V power supply 274 343 mA 182 99 228 124 mA mA Dual 3.3V/5V power supply 3.3V power supply 5V power supply (VCCT5) Output pins open Power consumption Single 3.3V power supply AC coupling input PD 0.91 1.19 W 1.10 1.44 W – 14 – CXB1582Q AC Characteristics (under the recommended operating conditions) Item Symbol Min. Typ. Max. Unit Conditions REFCLK rise time Tir_RC 4.8 ns 0.8 to 2.0V REFCLK fall time Tif_RC 4.8 ns 2.0 to 0.8V Tor_T 3.5 ns 0.8 to 2.0V, CL = 10pF 3.2 ns 0.6 to 2.2V, CL = 10pF 3.5 ns 2.0 to 0.8V, CL = 10pF 3.2 ns 2.2 to 0.6V, CL = 10pF TTL output rise time Single 3.3V power supply Dual 3.3V/5V power supply TTL output fall time Single 3.3V power supply Tof_T Dual 3.3V/5V power supply ECL output rise time Tor_E 400 ps 20 to 80%, CL ≤ 2pF ECL output fall time Tof_E 400 ps 20 to 80%, CL ≤ 2pF Mbaud SDIN data rate 531.25Mbaud mode R_SDIN 1062.5Mbaud mode REFCLK cycle tolerance Ttol_RC RBC0/1 skew Tskew RBC duty cycle 500 531.25 550 1000 1062.5 1100 Mbaud –100 0 Using the SDIN cycle as a reference 100 ppm –1 1 ns DC_RBC 40 60 % RX setup time Ts 3 ns RBC reference RX hold time Th 7.53 ns RBC reference Jitter tolerance JT 0.7 UI Bit sync time Tbs 2500 bit FC Idle Pattern Frequency acquisition time Tfa 500 µs Loop Damping Capacitor C1 = 0.01µF – 15 – CXB1582Q Electrical Characteristics Measurement Circuit (See Fig. 3 Power Supply Circuits regarding the power supply.) II_T A Measurement device TTL_IN TTL_OUT VI_T V Vo_T Io_T (a) TTL I/O DC characteristics measurement circuit Measurement device Pulse generator TTL_IN Probe TTL_OUT Oscilloscope CL CL = 10pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E A Measurement device ECL_IN ECL_OUT VI_TE V VO_E 50Ω VCCE – 2V (c) ECL I/O DC characteristics measurement circuit VCCE – 2V 50Ω Pulse generator VCCE – 2V Measurement device ECL_IN ECL_IN∗ 50Ω ECL_OUT ECL_OUT∗ Oscilloscope 50Ω 50Ω VCCE – 2V VCCE – 2V 50Ω Transmission Line CL ≤ 2pF (input capacitance of the measurement instrument and floating capacitance) (d) ECL I/O AC characteristics measurement circuit 26.5625MHz VCCE – 2V Measurement device Triger 50Ω Pulse pattern generator SDIN 1.0625Gbps SOUT Oscilloscope 1.0625Gbps SDIN∗ SOUT∗ 50Ω VCCE – 2V (e) Jitter characteristics measurement circuit – 16 – CXB1582Q Notes on Operation 1. Clock synthesizer (PLL) The CXB1582Q has a built-in PLL-based clock recovery circuit which recovers the clock from the serial data. This clock recovery circuit requires an external loop filter and an external resistor which determines the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the IC pins (Pins 50, 53 and 54) which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. In addition, resistor R3 should have a small temperature coefficient to reduce the temperature dependence of the VCO oscillation frequency. 50 51 53 52 R3 54 R1 R2 C1 R1: 200Ω R2: 200Ω R3: 4.7kΩ C1: 0.01µF Fig. 1. External Part Circuit and Recommended Constants – 17 – CXB1582Q 2. ECL input circuit The ECL differential input pins of the CXB1582Q are biased to VBB (Vcc – 1.3V) via an 18kΩ resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 18kΩ 160Ω 160Ω 3.3V ECL output buffer ECL differential input buffer (a) ECL differential signal from 3.3V ECL output buffer VCC = GND, VEE = –4.5V 0.01µF 0.01µF 330Ω ECL100K output buffer VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 18kΩ 330Ω ECL differential input buffer VEE (b) ECL differential signal from ECL100K output buffer VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 0.01µF 18kΩ 0.01µF 18kΩ 50Ω TRANS. LINE 50Ω 50Ω ECL differential input buffer VTT (VCC – 2V) (c) ECL differential signal from 50Ω transmission line VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 50Ω TRANS. LINE 50Ω 0.01µF 18kΩ 0.01µF 18kΩ VTT (VCC – 2V) ECL differential input buffer (d) ECL single signal from 50Ω transmission line Fig. 2. ECL Input Circuits – 18 – CXB1582Q 3. Power supply Power can be supplied to the CXB1582Q by either a single 3.3V power supply or a dual 3.3V/5V power supply. When a TTL output high level of 2.2V is sufficient (for example, when only interfacing with a 3.3V CMOS), use a single 3.3V power supply. When a TTL output high level of greater than 2.2V is required (for example, when interfacing with a 5V TTL/CMOS), use a dual 3.3V/5V power supply. VCCT5 VCCT3 VCCE VCCG 3mH 3.3V 22µF 3mH 0.1µF 22µF VEET VCCP VEEE 0.1µF VEEG 22µF 0.1µF VEEP1 VEEP2 (a) Single 3.3V power supply VCCT5 VCCE VCCG VCCP 3mH 5.0V 22µF 0.1µF VEET 3.3V 22µF VEEE 0.1µF VEEG (b) Dual 3.3V/5V power supply Fig. 3. Power Supply Circuits – 19 – 22µF 0.1µF VEEP1 VEEP2 CXB1582Q 4. Power-on reset signal (POR∗) The CXB1582Q has a power-on reset signal output (POR∗). As shown in figure (a) below, this signal is output at low level for approximately 100ns after the power is turned on, after which it goes to high level and can be used as the system reset signal. The low level time Tpor can be adjusted by capacitance Crt connected to the RTCAP pin as shown in figure (b) below. Tpor conforms roughly to the following equation. Tpor = 90ns × (1 + Crt/10pf) POR∗ 71 Tpor POR∗ Output RTCAP 70 Crt Power ON (a) (b) Fig. 4. Power-on Reset Signal Setting – 20 – CXB1582Q Example of Representative Characteristics Jitter transfer (1.0625GHz operation) 5 R1 = R2 = 300Ω 0 Jitter transfer [dB] R1 = R2 = 200Ω –5 R1 = R2 = 100Ω –10 –15 C1 = 0.01µF, R3 = 4.7kΩ, Ta = 27°C Pattern: Fibre Channel Idle Pattern (Transition Density = 80%) –20 103 104 105 106 107 108 Modulation frequency [Hz] Bit sync time (1.0625GHz operation) 5000 C1 = 0.01µF, R1 = R2 = 200Ω, R3 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel Idle Pattern (1.0625Gbps) Bit sync time [ns] 4000 3000 2000 1000 0 52 52.5 53 REFCLK [MHz] – 21 – 53.5 54 CXB1582Q Example of RJ measurement (recovery clock, 1.0625GHz operation) C1 = 0.01µF, R1 = R2 = 200Ω, R3 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel Idle Pattern (Transition Density = 80%) RJ = 9.5ps (RMS) [50ps/div] [200mV/div] Eye pattern (retimed data, 1.0625GHz operation) C1 = 0.01µF, R1 = R2 = 200Ω, R3 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel Idle Pattern (Transition Density = 80%) [200ps/div] – 22 – CXB1582Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 0.1 41 40 80 21 (15.0) 61 + 0.15 0.3 – 0.1 20 ± 0.12 M 0° to 10° 0.5 ± 0.2 1 0.65 + 0.15 0.1 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-80P-L03 LEAD TREATMENT EIAJ CODE LQFP080-P-1414 LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.6g JEDEC CODE – 23 –