ASAHI KASEI [AKD4702] AKD4702 Evaluation board Rev.A for AK4702 GENERAL DESCRIPTION AKD4702 is an evaluation board for quickly evaluating the AK4702 , 2ch DAC with AV SCART switch. Evaluation requires a audio/video analog analyzer, an analog video signal source, a digital audio signal source, and a power supply. AKM’s ADC evaluation board can be also used for the audio source. Also included is a AK4112B digital audio interface receiver which receives SPDIF compatible audio data. The digital audio data is available via optical connector or BNC. AKD4702 --- Evaluation board for AK4702 (Cable for connecting with printer port of IBM-AT compatible PC and control software are enclosed with board.) FUNCTION VVD2 D5V VVD1 +12V +5V MONOOUT < BNC connectors for analog audio input/output < BNC connectors for analog video input/output < On-board clock generator < BNC connector for an external clock input < Compatible with 2 types of digital interface 1. Serial interface: Direct interface with evaluation boards for AKM’s A/D converter evaluation boards. 2. S/PDIF: On-board AK4112BVF as DIR that accepts optical input or BNC input < 10pin header for serial control interface Gnd JP10 TVOUTL Reg. JP11 (Digital) JP8 Control Data TVOUTR PORT3 µ P-IF JP9 10pin Heder Port1 VCROUTL AD DATA ROM DATA 10pin Header JP6 VCROUTR JP2~ 5 RX DIR PORT2 Opt In µ MONOIN TVINL TVINR TVFB JP12 ENCB ENCRC ENCG ENCV ENCC TVVIN ENCY VCRFB VCRVIN VCRINR TVG VCRINL TVVOUT VCRVOUT VCRC TVRC TVB AK4702 Clock Generator RFV JP1 J1 EXT VCRG VCRRC VCRSB VCRB TVSB Figure 1. AKD4702 Block Diagram l Circuit diagram and PCB layout are attached at the end of this manual. <KM067304> 2002/12 -1- ASAHI KASEI [AKD4702] n Operation sequence 1) Set up the power supply lines. (Note 1) [+12V] [+5V] [D5V] [VVD1] [VVD2] [AGND] [DGND] [VVSS2] (Orange) (Red) (Red) (Red) (Blue) (Black) (Black) (Black) = +11.4 ∼ +12.6V = +4.75 ∼ +5.25V (Note 2) = +4.75∼ +5.25V (Note 3) = +4.75∼ VVD2 (Note 4) = VDD1∼ +5.25V (Note 4) = 0V = 0V = 0V Note: 1. Each supply line should be distributed from the power supply unit. 2. JP9 (REG) should be open when the “+5V” jack is used. 3. JP8 (D-A) should be open when the “D5V” jack is used. 4. JP10 (VDD1) / JP11 (VDD2) should be open when the “VDD1” jack / “VDD2” jack are used respectively. 2) Set-up the evaluation modes, jumper pins and DIP-switches. (Refer following sections.) 3) Connect the PORT3 (=µP-I/F) with PC by the enclosed 10-wire flat cable. 4) Set up the PC and execute the enclosed control software. (See “CONTROL SOFTWARE MANUAL”.) 5) Turn the power on. 6) Reset the AK4702 once by bringing the SW1 (PDN) “L”, and turn it to “H”. <KM067304> 2002/12 -2- ASAHI KASEI [AKD4702] n Evaluation mode 1) S/PDIF mode (Optical Link or BNC: default) When the CM0 (DIP-switch S1_1 on board) is “L”, the AK4112B (DIR) generates MCLK, BICK, LRCK and SDATA from the received bitstream through PORT2 (TORX176: optical link) or J2 (BNC). This mode is used for the evaluation using CD test disk. The PORT1 (EXT) should be open. 1)-1. DIP-switch set-up No. 1 2 3 4 CM0 “L” “L” “L” “L” DIF1 “L” “L” “H” “H” DIF0 “L” “H” “L” “H” Audio Data Format of AK4112B 16bit LSB justified 18bit LSB justified MSB justified I 2S Notes 1 2 3 4 Table 1. DIP-switch set-up 2 Please match the data format of AK4702 via I C-bus control as following notes. Note 1. 16bit LSB justified Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of AK4702 by enclosed software as follows. Note 2. 18bit LSB justified Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of AK4702 by enclosed software as follows. <KM067304> 2002/12 -3- ASAHI KASEI [AKD4702] Note 3. MSB justified Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of AK4702 by enclosed software as follows. Note 4. I2S Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of AK4702 by enclosed software as follows. <KM067304> 2002/12 -4- ASAHI KASEI [AKD4702] 1)-2. Jumper pins set up JP2 MCLK JP1 EXT JP3 BICK JP4 SDTI JP5 LRCK The JP6 selects the input port of S/P DIF bitstream form Port2 (TOTX176) or J2 (BNC RX). JP6 JP6 RX RX TORX TORX BNC BNC Using TORX Using BNC <KM067304> 2002/12 -5- ASAHI KASEI [AKD4702] 2) On-board X’tal mode/ Feeding external MCLK via BNC When the CM0 (DIP-switch S1_1 on board) is “H”, the AK4112B generates MCLK, BICK and LRCK from on-board X’tal or external clock form J1. SDATA should be fed via PORT1. 2)-1. DIP-switch set-up No. 1 CM0 “H” DIF1 Don’t care DIF0 Don’t care Table 2. DIP-switch set-up 2)-2. Jumper pins set up 2)-2-a. Using on-board X’tal JP1 JP2 JP3 JP4 JP5 EXT MCLK BICK SDTI LRCK JP6: Don’t care. 2)-2-b. Using external clock via BNC connector J1 JP1 JP2 JP3 JP4 JP5 EXT MCLK BICK SDTI LRCK JP6: Don’t care. Remove the on-board X’tal. <KM067304> 2002/12 -6- ASAHI KASEI [AKD4702] 3) Feeding all clocks from external Under the following set-up, all external signals can be fed to AK4702 through POTR1 (EXT). The AKM’s evaluation board for ADC can be used. 3)-1. DIP-switch set-up No. 1 CM0 Don’t care DIF1 Don’t care DIF0 Don’t care Table 3. DIP-switch set-up 3)-2. Jumper pins set up JP1 JP2 JP3 JP4 JP5 EXT MCLK BICK SDTI LRCK JP6: Don’t care. n Other jumper pins set up [JP12](VCRRC): Input Jack selection for the VCRRC pin of AK4702 When the VCRC pin of AK4702 outputs 0V by setting CIO bit to “1”, the signal can be fed through the J27 (VCRCOUT) to VCRRC pin. “I”: The signal is fed through the J18(VCRRC) to VCRRC pin. (Default) “I/O”: The signal is fed through the J27(VCRCOUT) to VCRRC pin. The CIO bit of AK4702 should be set to “1”. [JP7](GND): Analog ground and digital ground Open: separated. (Default) Short: connected. (The jack “DGND” can be open.) JP7 DGND AGND <KM067304> 2002/12 -7- ASAHI KASEI [AKD4702] n DIP-switch (S1) List No. 1 2 3 4 5 Switch Name CM0 DIF0 DIF2 - Default OFF OFF OFF OFF OFF Function Refer the “n Evaluation mode” (Reserved) (Reserved) Table 4. DIP-switch list n Jumper List No. Jumper Name Function MCLK source set-up when CM0=”H”. 1 2,3, 4,5 EXT MCLK, BICK, LRCK, SDTI Short: X’tal (default). Open: External clock via BNC (J1). Remove the on-board X’tal. Clock source set-up Short: Connect the DIR (AK4112B). (default) Open: Separate the DIR. Supply clocks via Port1. S/PDIF’s port set-up when CM0=”L”. 6 RX 7 GND 8 D-A 9 REG TORX: Optical connector PORT2. (default) BNC: BNC connector J2. Analog ground and digital ground Open: separated (default). Short: connected (The connector “DGND” can be open.). Power supply source set-up for digital section of AKD4702. Open: from the “D5V” Jack. (default) Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “D5V” Jack.(default) Power supply source set-up for VD of AK4702. Open: from the “+5V” Jack. Short: from the regulator. Don’t connect anything the “+5V” Jack. (default) Power supply source set-up for VVD1 of AK4702. 10 VVD1 Open: from the “VVD1” Jack. Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD1” Jack. (default) Power supply source set-up for VVD1 of AK4702. 11 VVD2 Open: from the “VVD2” Jack. Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD2” Jack. (default) Input Selection for VCRRC 12 VCRRC “I” side: Input to VCRRC from VCRRC jack. “I/O” side: Input to VCRC from VCRC jack. (Note: Refer CIO bit of AK4702) Table 5. Jumper list <KM067304> 2002/12 -8- ASAHI KASEI [AKD4702] n Serial Control The AK4702 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (µP-IF) with PC by 10 wire flat cable packed with the AKD4702. Be careful connector direction. Flat cable should be connected 10-pin header, red line put on 10pin header 5 and 6 pin. 1 10 SCL Connect SDA PC AKD4702 SDA(ACK) RED 10 wire flat cable 5 10 pin Connector PORT3 µP-IF 6 10 pin Header Figure 2. Connection of 10 pin flat cable for PORT3 n Input/Output port List Table 6. Input/Output port List Slow Blanking Input Output Signal Name J5 (VCRINL), J3 (VCRINR), J9 (TVINL), J8 (TVINR) J11 (MONOIN) J12 (VCROUTL), J10 (VCROUTR), J6 (TVOUTL), J7 (TVOUTR), J4 (MONOOUT) Port2 (TORX176) or J2 BNC (RX) J13 (ENCB), J15 (ENCG), J17 (ENCRC), J19 (ENCC), J21 (ENCV), J23(ENCY), J25(TVVIN), J14(VCRVIN), J18(VCRRC; Note), J20(VCRG), J22(VCRB) J27 (VCRCOUT; Note), J29 (TVVOUT), J30 (TVRC), J31 (TVG), J32 (TVB), J33 (RFV), J34 (VCRVOUT) J24 (VCRSB) J24 (VCRSB) , J28 (TVSB) Fast Blanking Input Output J16 (VCRFB) J26 (TVFB) Input Audio Output Digital Input Input Video Output Notes Max: 2Vrms Max: 1Vrm Max: 3Vrm Max: D5V+0.3V Max: 1.5Vp-p Max: 3Vp-p Max: VP+0.3V Max: VP Max: VVD1+0.3V Max: VVD2 Note: Refer JP12 and CIO bit of AK4702. n The indication content for LED LED turns on during each output is “H”. [LE1] (Unlock and Parity Error on S/P DIF): ERF of DIR (AK4112B). Normally off. [LE2] (Validity Flag): V of DIR (AK4112B). Normally off. n Toggle switch (SW1 on board) operation “H”: AK4702 is Active. “L”: AK4702 is Powered Down . (Note; When the power of AKD4702 is ON at first, SW1 should be switched from “L” to “H”.) <KM067304> 2002/12 -9- ASAHI KASEI [AKD4702] MEASUREMENT RESULTS n Audio [Measurement condition] • Measurement unit : Audio Precision System two Cascade • MCLK : 256fs • BICK : 64fs : 48kHz • fs : 10Hz∼20kHz • BW : 18bit • Bit • Power Supply : VD=5V, VDD1=5V, VDD2=5V, VP=12V • Interface : DIR • Temperature : Room • Volume#0=Volume#1=0dB • Measurement signal line path: DAC → Volume#0 → Volume#1 → TVOUTL/R Parameter S/(N+D) at 2Vrms Output DR S/N Input signal 1kHz, 0dBFS 1kHz, -60dBFS “0” data Measurement filter 20kLPF 22kLPF, A-weighted 22kLPF, A-weighted Results [dB] 91.5 96.0 96.0 Plots Figure 1-1. FFT (1kHz, 0dBFS input) at 2Vrms output Figure 1-2. FFT (1kHz, -60dBFS input) Figure 1-3. FFT (Noise floor) Figure 1-4. FFT (Out-of band noise) Figure 1-5. THD+N vs. Input Level (fin=1kHz) Figure 1-6. THD+N vs. fin (Input Level=0dBFS) Figure 1-7. Linearity (fin=1kHz) Figure 1-8. Frequency Response (Input Level=0dBFS) Figure 1-9. Crosstalk (Input Level=0dBFS) <KM067304> 2002/12 - 10 - ASAHI KASEI [AKD4702] n Video [Measurement condition] • Signal Generator : Sony Tectonics TG2000 • Measurement unit : Sony Tectonics VM700T : VD=5V, VDD1=5V, VDD2=5V, VP=12V • Power Supply : BNC • Interface : Room • Temperature • Measurement signal line path: ENCV → TVVOUT, ENCRC → TVRC Parameter S/N Crosstalk DG DP Measurement conditions Input = 0% flat field Filter = Uni-weighted, BW= 15kHz to 5MHz Input = 100%red(ENCRC), Measured at TVVOUT Input = Modulated Lamp Input = Modulated Lamp Results 75.8 Unit dB -52 dB -0.1 to +0.24 0 to +0.40 % deg. Plots Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted) Figure 2-2. Frequency Response (Input= Multi Burst) Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT) Figure 2-4 DG, DP (Input= Modulated Lamp) <KM067304> 2002/12 - 11 - ASAHI KASEI [AKD4702] Plots (Audio) AKM AK4702 FFT (DAC->TVOUT: fs=48kHz, sigal = 1kHz/0dB) +0 -10 -20 -30 -40 -50 -60 d B r -70 -80 A -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure1-1. FFT (fin=1kHz Input Level=0dBFS) AKM AK4702 FFT (DAC->TVOUT: fs=48kHz, sigal = 1kHz/-60dB) +0 -10 -20 -30 -40 -50 -60 d B r -70 -80 A -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k Hz Figure-1-2. FFT (fin=1kHz Input Level=-60dBFS) <KM067304> 2002/12 - 12 - ASAHI KASEI [AKD4702] AKM AK4702 FFT (DAC->TVOUT: fs=48kHz, no sigal) +0 -10 -20 -30 -40 -50 -60 d B r -70 -80 A -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure1-3. FFT (Noise Floor) AKM AK4702 FFT (DAC->TVOUT: fs=48kHz, no sigal, out of band) +0 -10 -20 -30 -40 -50 -60 d B r -70 -80 A -90 -100 -110 -120 -130 -140 -150 100 200 500 1k 2k 5k 10k 20k Hz Figure1-4. FFT (Outband Noise) <KM067304> 2002/12 - 13 - ASAHI KASEI [AKD4702] AKM AK4702 THD+N vs. Level (DAC->TVOUT: fs=48kHz, signal= 1kHz ) -80 -82 -84 -86 -88 d B r -90 A -92 -94 -96 -98 -100 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure1-5. THD+N vs. Input level (fin=1kHz) AKM AK4702 THD+N vs. Input Frequency (DAC->TVOUT: fs=48kHz, signal= 0dB ) -80 -82 -84 -86 -88 d B r -90 A -92 -94 -96 -98 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure1-6. THD+N vs. Input Frequency (Input level=0dBFS) <KM067304> 2002/12 - 14 - ASAHI KASEI [AKD4702] AKM AK4702 Linearity (D A C ->TVOUT: fs=48kHz, signal= 1kHz ) +0 -10 -20 -30 -40 d B r -50 -60 A -70 -80 -90 -100 -110 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure1-7.Linearity (fin=1kHz) AKM AK4702 Frequency response (DAC->TVOUT: fs=48kHz, signal= 0dB ) +0.5 +0.4 +0.3 +0.2 +0.1 d B r +0 A -0.1 -0.2 -0.3 -0.4 -0.5 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure1-8. Frequency Response (Input level=0dBFS) <KM067304> 2002/12 - 15 - ASAHI KASEI [AKD4702] AKM AK4702 Crosstalk (DAC->TVOUT: fs=48kHz, signal= 0dB ) -60 -65 -70 -75 -80 d B r A -85 -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure1-9. Crosstalk (Input level=0dBFS) <KM067304> 2002/12 - 16 - ASAHI KASEI [AKD4702] Plots(Video) Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted) Figure 2-2. Frequency Response (Input= Multi Burst) <KM067304> 2002/12 - 17 - ASAHI KASEI [AKD4702] Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT) Figure 2-4 DG, DP (Input= Modulated Lamp) <KM067304> 2002/12 - 18 - ASAHI KASEI [AKD4702] CONTROL SOFTWARE MANUAL n Introduction This is a manual of software that controls the AK4702, 2ch DAC with AV SCART switch. The enclosed software AKD4702.exe can control the registers of AK4702 using I2C control I/F. n System Requirements To use this software, the followings are required for PC.: • Windows 95/98/ME/2000/XP. (This software does not operate on Windows NT.) • Printer port n Set-up of evaluation board and control software 1. 2. 3. Set up the AKD4702. Insert Connect IBM-AT compatible PC with AKD4702 by 10-line type flat cable (packed with AKD4702). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM disk when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) The CD-ROM disk labeled “AKD4702 Control Program ver 1.0” into the CD-ROM disk drive. n Operations [1] Execute the AKD4702.exe. Then the following window opens. The function of each button is shown below. Clicking the button does each operation in the alone. Write defalt to all resisters. Read all resisters. Close this window. “ ”means “1”. Write each byte. Space means “0”. Read the address in this box. Read 08H. Write the DATA to the address in this box. <KM067304> 2002/12 - 19 - ASAHI KASEI [AKD4702] [2] Write/Read Register There are two ways to Write/Read register. (1) Check box After checking each box of each bit, click the “Write” or “Read” button in the right end. “ ” in each check box means “1” and no check means “0”. Each check mark toggles by clicking. The address 08H is Read-only. (2) Edit box There is an edit box in the left bottom. All register can be written and read using the edit box. When writing register, input the DATA and the Address in the box and click “Write” button. When reading register, input the Address in the box and click “Read” button. <KM067304> 2002/12 - 20 - ASAHI KASEI [AKD4702] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM067304> 2002/12 - 21 - ASAHI KASEI [AKD4702] <KM067304> 2002/12 - 22 - 5 4 3 2 1 R1 4112B_3.3V C1 5.1 0.1u 10u C3 + U2A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 JP1 2 2 EXT 74HCU04 22p C5 J1 BNC (OPEN) 22p 12.288MHz 1 C6 X1 R3 75 C (OPEN) CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCK01 MCK02 DAUX BICK SDTO LRCK ERF FS96 P/S AUTO DVDD DVSS TVDD V/TX XTI XTO PDN R AVDD AVSS RX1 DIF0/RX2 DIF1/RX3 DIF2/RX4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INTRUPT JP2 MCLK JP3 JP4 JP5 BICK SDTI LRCK 3 CM0 DIF0 DIF2 18k 4112B_3.3V C7 + 10u B C8 0.1u 47u MCLK C ERF 1k LE2 R5 6 74HCU04 10 9 8 7 6 LE1 R4 1k V U2D Logic 9 8 74HCU04 5 4 3 2 1 L1 300 SW DIP-5 RP1 Logic 5 AK4112B 1 2 3 4 5 CM0 DIF0 DIF2 6 5 5 GND VCC GND OUT 11 10 74HCU04 C9 TORX176 0.1u R7 A U2F R-PACK5R 4 3 2 1 13 10u JP6 RX 470 TORX BNC(RX) C11 BNC A Title 0.1u 75 Size Document Number Date: 4 3 AKD4702 AK4112B A 5 12 74HCU04 C10 + J2 R8 B U2E PORT2 6 D 4 U2C S1 DIF2 Logic 10k Logic 74HCU04 R6 R2 EXT BICK SDTI LRCK U2B DIF0 PORT1 10 9 8 7 6 R82 10k R83 AK4112BVF PDN 1 2 3 4 5 Logic U1 0.1u Logic 1 CM0 C4 10u D MCLK BICK LRCK SDATA C2 + Sheet 2 Rev A 1 of 1 6 5 4 3 2 1 JP7 SCL VCRC 2 VVSS2 3 TVVOUT 4 VVD2 5 TVRC 6 TVG Video Block input/output VD 37 38 R9 100 MCLK 39 R12 100 40 BICK 100 41 SDTI 100 42 LRCK 43 SCL 44 SDA 46 45 PDN 35 VP 34 MONOOUT 33 U3 TVOUTL 32 AK 4702 TVOUTR 31 VCROUTL 30 9 ENCB MONOIN 28 VCRINR TVSB 23 22 21 20 18 17 VCRSB 26 INTRUPT TVINR VCRB ENCRC VCRG TVINL 11 VCRRC ENCG 27 VCRFB 10 ENCC D C18 +C19 0.1u 10u +12V VCRINL C20 +C21 0.1u 10u C 29 (VVSS) MONOOUT Analog output TVOUTL TVOUTR VCROUTL VCROUTR B MONOIN 25 TVINL TVINR Analog input VCRINL VCRINR VCRSB ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB Video Block input INTRUPT A DVCOM VCROUTR 12 10u (VVSS) (VVSS) 36 VCRVIN Video Block output VCRC TVVOUT TVRC TVG TVB RFV VCRVOUT TVFB TVSB 10u VVD1 TVVIN (VVSS2) +C16 0.1u PVCOM 16 10u C17 TVB ENCV 0.1u +C13 0.1u (VVSS) 8 13 B +C15 C12 +5V 7 15 VVD1 C 47 R10 1 RFV TVFB (VVSS2) VCRVOUT 10u ENCY 0.1u 14 +C23 48 C22 R11 Digital Ground 19 Analog Ground PDN DAC input 24 VVD2 SDA D C14 LRCK SDTI BICK MCLK Resister Contorol VSS GND A Title Size Document Number AK4702 A Date: 5 4 3 AKD4702 Sheet 2 Rev A 2 of 1 6 5 C24 2 10u R18 300 10k (VVSS) (VVSS) C26 (VVSS) J6 R20 C27 R19 10u VCRINL R21 0.47u D MONOOUT + J5 VCRINL MONOOUT 300 TVOUTL 300 + (VVSS) J4 R16 C25 R15 VCRINR R17 0.47u (open) 1 + J3 VCRINR 3 + D 4 TVOUTL R22 300 10k (open) C29 C28 R24 10u + R26 0.47u 300 (open) (VVSS) J9 TVINL C30 C R25 10k (VVSS) (VVSS) J10 R28 C31 R27 10u + TVINL R29 0.47u TVOUTR 300 TVOUTR VCROUTL 300 + (VVSS) FOR Analog input TVINR (VVSS) J7 R23 + C (VVSS) (VVSS) From Analog output (VVSS) J8 TVINR VCROUTL R30 300 10k (open) (VVSS) (VVSS) J11 MONOIN C32 10u + MONOIN R33 0.47u (open) (VVSS) J12 R32 C33 R31 B (VVSS) (VVSS) VCROUTR 300 + B VCROUTR R34 300 10k (VVSS) (VVSS) (VVSS) A A Title Size Document Number 5 4 3 Rev Analog Input/Output Circuit A Date: AKD4702 Friday, April 11, 2003 2 Sheet 3 of 1 A 6 5 4 R35 3 U4 R36 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 1 19 G1 G2 Logic D PORT3 1 2 3 4 5 10 9 8 7 6 10k 470 R39 R40 10k 470 SCL SDA SDA(ACK) R41 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 2 100 R37 18 17 16 15 14 13 12 11 SCL Logic D1 R38 10k U5A 1 H L U5B 2 3 74HCT14 D 4 PDN 74HCT14 C34 SW1 74HCT541 51 1 0.1u PDN uP-I/F 1 U6A 2 74LS07 3 U6B 4 74LS07 U5C 5 6 74HCT14 U5D R42 U6C 6 74LS07 5 C 9 Logic 10k R43 74HCT14 U5E 11 10 SDA (short) SDA(ACK) D5V +5V 3 Logic D-A REG 10u B +C39 47u IN 0.1u 0.1u Short C36 Logic JP10 R14 C46 47u IN + 2 C49 0.1u OUT GND 1 4112B_3.3V VVD1 3 C41 C42 C43 C44 C45 + C40 0.1u 0.1u 0.1u 0.1u 0.1u 47u Logic C47 + C48 47u 0.1u for 74HCT14, 74HCU04, 74LS07, 74HCT541 VDD1 A VVD2 Title R13 JP11 short VDD2 Size VVD2 Document Number 4 3 AKD4702 Rev POWER SUPPLY A Date: 5 B 47u T2 LP2950A Short 5.1 13 47u +5V A 74HCT14 C +12V + R45 VVD1 11 1 C35 C37 C38 OUT 2 + 74HCT14 U5F 13 12 U6D 8 74LS07 U6E 10 74LS07 U6F 12 74LS07 R44 JP9 L2 9 +12V T1 NJM78M05FA GND JP8 8 Sheet 2 A 4 of 1 6 5 4 J13 ENCB R70 3 2 J14 VCRVIN C50 1 C51 R77 ENCB (short) R46 75 D VCRVIN R47 75 0.1u (VVSS2) (VVSS2) J15 ENCG (VVSS2) R71 (short) (VVSS2) D J16 VCRFB C52 0.1u R78 ENCG R48 (short) VCRFB R49 75 0.1u 75 (VVSS2) (VVSS2) (VVSS2) J17 ENCRC R72 300 (VVSS2) JP12 J18 VCRRC C53 I R79 C54 (short) 0.1u ENCRC R50 75 (short) VCRRC I/O VCRRC R51 75 0.1u VCRCOUT C (VVSS2) (VVSS2) (VVSS2) J19 ENCC R73 J20 VCRG C55 C56 R80 ENCC R52 75 (VVSS2) (short) VCRG R53 75 0.1u (VVSS2) J21 ENCV (VVSS2) R74 C57 (short) 0.1u (short) 0.1u R81 C58 (short) 0.1u (VVSS2) J22 VCRB ENCV B R54 75 (VVSS2) VCRB R55 75 (VVSS2) (VVSS2) J23 ENCY R75 J24 VCRSB C59 (VVSS2) A (short) R56 VCRSB R58 10K 0.1u (VVSS2) J25 TVVIN (VVSS) R76 (VVSS2) (short) 300 (VVSS) C60 A TVVIN R59 75 Title 0.1u Size A (VVSS2) Document Number 4 3 AKD4702 Video Block Input Circuit Date: 5 B (VVSS2) ENCY R57 75 C (VVSS2) Sheet 2 Rev A 5 of 1 6 5 4 3 1 J27 R61 R67 VCRCOUT 75 300 VCRC D 2 J33 RFV RFV VCRCOUT D (VVSS2) (VVSS2) J29 R63 TVVOUT 75 R60 TVVOUT J26 75 TVFB R62 J28 TVFB (VVSS2) J30 R64 (VVSS2) TVRC 75 TVRC 300 TVSB TVSB C C (VVSS2) J31 R65 (VVSS2) TVG 75 TVG (VVSS2) J32 R66 TVB 75 TVB B B (VVSS2) J34 R68 VCRVOUT 75 VCRVOUT (VVSS2) A A Title Size Document Number Date: 4 3 Rev Video Block Output Circuit A 5 AKD4702 Sheet 2 6 of 1 A 6