A7101 Preliminary 2.4GHz FSK Transceiver Document Title 2.4GHz FSK Transceiver Revision History Rev. No. History Issue Date Remark 0.0 Initial issue August 2, 2002 Preliminary 0.1 Modify current consumption, Tx output power, sensitivity, October 16, 2002 Preliminary June 9, 2003 Preliminary RSSI range, frequency deviation, data rate, SPI interface, and pin description. 0.2 Modify X’TAL Settling Time, Tx output power (Hi power) Application Circuit, and delete X’TAL accuracy 0.3 Modify Tx output power (Hi power) Dec. 30 2003 Preliminary 0.4 Modify data rate and calibration mode March 10, 2004 Preliminary Important Notice: AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC products in such applications is understood to be fully at the risk of the customer. PRELIMINARY (March 2004, Version 0.4) AMIC Technology, Corp. A7101 Preliminary 2.4GHz FSK Transceiver Typical Applications Wireless Mouse and Keyboard 2.4GHz ISM Band Communication System Two way wireless Transceiver Wireless toy Wireless Modem General Description The A7101 is a monolithic CMOS integrated circuit intended for use as a low cost FSK transceiver in wireless applications. The device is provided in 48-lead plastic QFN7X7 packaging and is designed to function as a complete FSK transceiver. It is intended for wireless applications in the 2.4GHz to 2.5GHz ISM band. This chip features a fully programmable frequency synthesizer with integrated VCO circuitry. RSSI MUTE 38 37 LPFINN 42 TANK2 LPFOUT 43 39 CAP3_AFC 44 LPFINP CAP1_AFC 45 TANK1 CAP2_AFC 46 40 EN_AFC 47 41 CMPVIP 48 Pin Configurations VDD_A 1 36 LIM2INN RXDATA 2 35 LIM2INP BR_RX 3 34 LIM1OUT NC 4 33 LIM1INN RFIO 5 32 LIM1INP BP_BUF 6 31 MIXOUT TXDATAIN 7 30 VDD_VCO XTAL1 8 29 BP_VCO XTAL2 9 28 VT XTALOUT 10 27 BR_VCO CAPSW 11 26 CHPOUT BP_REG 12 25 LD 21 22 REGFB EN_REG 24 20 MODSEL0 23 19 SPI_LATCH VIN 18 MODSEL1 17 16 VUOT SPI_DATA 15 SPI_CLOCK 14 LVIN VDD_D LVOUT 13 A7101 Figure 1. QFN Package Top View PRELIMINARY (March 2004, Version 0.4) 1 AMIC Technology, Corp. A7101 Block Diagram 32 LPFOUT 48 2 RXDATA 43 CMPVIP 42 LPFINN 41 LPFINP 40 TANK1 39 LIM1INN Data Slicer LPF DEMOD LIM1INP Limiter1 31 38 TANK2 MUTE 37 RSSI 36 LIM2INN LIM1OUT 33 35 LIM2INP 34 Limiter2 Integrator MIXOUT EN_AFC LNA 5 CAP2_AFC RFIO CAP1_AFC PA CAP3_AFC VCO 7 11 8 TXDATAIN CAPSW FSK Modulation Circuit BP_VCO VT Buffer 47 46 45 44 29 28 XTAL1 ÷ 32 BR_VCO Bias 33 27 OSC CHPOUT LD 26 25 XTALOUT 14 16 23 17 18 SPI_LATCH SPI_CLOCK SPI_DATA VIN EN_REG 22 19 MODSEL1 13 Mode Selection SPI MODSEL0 12 VOUT Voltage Regulator & Low voltage detector REGFB BP_REG 21 Phase Detector Charge Pump Counter LVIN 10 XTAL2 LVOUT 9 20 24 Figure 2. System Block Diagram PRELIMINARY (March 2004, Version 0.4) 2 AMIC Technology, Corp. A7101 Specification Parameter Description Min. General Storage Temperature Operating Temperature Supply Voltage Current Consumption Transceiver Circuit Current Consumption Embedded Regulator Phase Locked Loop Reference Frequency X’TAL Settling Time Operation Frequency Number of Channels PLL Settling Time RF Front End (TX mode) TX Power RF Output Impedance RF Front End (RX mode) RF Input Impedance Sensitivity Max. Unit -20 70 °C 0 50 °C V mA mA mA mA 2.2 Active (RX Mode) Active (TX Mode @high power) Active (TX Mode @low power) Stand By Mode Sleep Mode 2.5 30 17 14 1.5 5 Active @VIN = 3.3V 150 µA Stand By 5 µA MHz ms MHz @ 2MHz spacing @Loop bandwidth = 100KHz 4,6,8,10,12,14,16 5 2416~2478 32 150 High Power Low Power @2.45GHz -6 -16 50 dBm dBm Ohm @2.45GHz @BER=0.001 50 -80 Ohm dBm -30 dBm @12MHz, cap. Load = 20pF Cascaded IIP3 TBM IF Section Intermediate Frequency RSSI Range Modulation / Demodulation Scheme Data rate Frequency Deviation Typ. 5 µA µs 10.7 @RF input -90 FSK @ Crystal modulation @ VCO modulation @ Crystal modulation @ VCO modulation Regulator Supply voltage Output voltage Drop out voltage Load current Battery-Low indicator reference -50 64 Kbps Kbps KHz KHz 5 V V V mA V 100 50 150 2.5 0.2 50 1.2 MHz dBm Table 1. PRELIMINARY (March 2004, Version 0.4) 3 AMIC Technology, Corp. A7101 RF - Baseband Interface Pin Number Pin Name Description 23 VIN Supply voltage. GND Ground. Note Please see Pin Descriptions section for detail. 7 TXDATAIN Transmitter data input. 2 RXDATA Receiver data output. 17 SPI_DATA Data for SPI interface. 18 SPI_CLOCK Clock for SPI interface. 19 SPI_LATCH Latch for SPI interface. 20 MODSEL0 Chip operation mode selection (LSB). Option. 24 MODSEL1 Chip operation mode selection (MSB). Option. 25 LD PLL locked detect Indicator output. Option. 22 EN_REG Voltage regulator enable pin. Option. 13 LVOUT Battery-low indicator output. Option. 37 MUTE Receiver mute control output pin. Option. 47 EN_AFC AFC circuit control pin. Option. Table 2. PRELIMINARY (March 2004, Version 0.4) 4 AMIC Technology, Corp. A7101 Pin Descriptions (I: input O: output OD: open drain output) Pin No. Symbol I/O Function Description 1 VDD_A I 2 RXDATA OD 3 BR_RX O 4 NC 5 RFIO I/O RF input/output port. 6 BP_BUF O Noise bypass. Connect to external noise rejection capacitor. 7 TXDATAIN I Transmitter data input. 8 XTAL1 I Colpitts crystal oscillator node 1. Connect to external feedback capacitor. 9 XTAL2 I Colpitts crystal oscillator node 2. Connect to external feedback capacitor. 10 XTALOUT O Buffered crystal oscillator output. 11 CAPSW I Modulation switch input. 12 BP_REG O Regulator band gap bypass output. Connect to external noise rejection capacitor. Typical output voltage is 1.2V. 13 LVOUT O Battery-Low voltage indicator output. This pin is active low when LVIN is below BP_REG voltage level. 14 LVIN I Input for battery-low voltage indicator. The indicator compares LVIN with the threshold voltage, BP_REG. 15 VDD_D I Digital supply voltage input. 16 VOUT O Regulator output voltage. Nominal voltage output is 2.5V. 17 SPI_DATA I/OD 18 SPI_CLOCK I Clock input for SPI interface. 19 SPI_LATCH I Latch input for SPI interface. Analog supply voltage input. Recovered data output. This pin is an open drain output. Receiver band gap bias output. Connect to external resistor to set bias current. This pin must be open. Data for SPI interface. This pin operates as an Input pin when SPI is in Write mode. This pin operates as an open drain output when SPI is in Read mode. Transceiver (embedded regulator is not included) operation mode selection inputs. 20 MODSEL0 24 MODSEL1 MODSEL[1:0] = 00: Sleep mode. Transceiver circuit is turned off. I MODSEL[1:0] = 01: Stand-by mode. X’TAL oscillator is turned on. MODSEL[1:0] = 10: Transmit mode. MODSEL[1:0] = 11: Receive mode. 21 REGFB O Output from regulator feedback network. VOUT is set to nominal voltage when this pin is opened. If other voltage is required, connect it to external resistor to adjust VOUT. 22 EN_REG I Voltage regulator enable pin. Signal is active high. 23 VIN I Supply voltage for the internal voltage regulator. 25 LD OD 26 CHPOUT O Charge-pump output. This pin charges external capacitor to adjust VCO frequency. 27 BR_VCO O VCO band gap bias output. Connect to external resistor to set bias current. Output from PLL lock detector. This pin is active high (Open drain) when PLL is locked. 28 VT I VCO tuning voltage input. The VCO frequency increases as VT increases. 29 BP_VCO O Noise bypass. Connect to external noise rejection capacitor. 30 VDD_VCO I VCO supply voltage input. PRELIMINARY (March 2004, Version 0.4) 5 AMIC Technology, Corp. A7101 Pin Descriptions (I: input O: output OD: open drain output)(continued) Pin No. Symbol I/O Function Description 31 MIXOUT O Single-ended Mixer output. 32 LIM1INP I First Limiter differential positive input. 33 LIM1INN I First Limiter differential negative input. 34 LIM1OUT O First Limiter single-ended output. 35 LIM2INP I Second Limiter differential positive input. 36 LIM2INN I Second Limiter differential negative input. 37 MUTE OD 38 RSSI O Received Signal Strength Indicator output. RSSI output voltage is inversely proportional to the received RF signal power level. 39 TANK2 I Demodulator Tank 2 input. 40 TANK1 I Demodulator Tank 1 input. 41 LPFINP I Low pass filter differential positive input. 42 LPFINN I Low pass filter differential negative input. Receiver mute control output. Open drain output. This pin is active low when received RF signal is under threshold level. 43 LPFOUT O Low pass filter single-ended output. 44 CAP3_AFC O Auto frequency control circuit output bypass pin3. Connect to external capacitor. 45 CAP1_AFC O Auto frequency control circuit output bypass pin 1. Connect to external capacitor. 46 CAP2_AFC O Auto frequency control circuit output bypass pin 2. Connect to external capacitor. 47 EN_AFC I AFC circuit control input. Signal is active high. 48 CMPVIP I Positive input for data slicer. Table 3. PRELIMINARY (March 2004, Version 0.4) 6 AMIC Technology, Corp. A7101 Absolute Maximum Rating* Parameter With respect to Rating Unit Supply voltage range (VDD) GND -0.3 to 5.5 Vdc Other I/O pins range GND -0.3 to VDD+0.3 Vdc 0 dBm -20 ~ +70 °C Maximum input RF level Storage temperature range Table 4. *Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PRELIMINARY (March 2004, Version 0.4) 7 AMIC Technology, Corp. A7101 Circuit Description 1. Low Noise Amplifier The first stage of the receiver is a low noise amplifier. The main function of the LNA is to provide enough gain to overcome noise generated by subsequent stages. In order to make the circuit less sensitive to parasitic parameters, and more tolerant to common mode disturbances, differential pair is used. The LNA operates at very low power consumption with modest 20dB voltage gain. It is internally matched to 50ohm. No other external components are required. 2. RF Mixer The RF mixer is designed to translate incoming RF signal to intermediate frequency (IF). The mixer is a conventional double balanced Gilbert cell mixer. Its output impedance is matched to 330ohm. A conventional 330ohm ceramic filter should be connected between the mixer and the first limiter to filter out all un-wanted noise. 3. IF Limiter The IF limiter consists of two stages: The first IF limiter stage consists of 3 differential amplifiers and a single-ended output buffer. The output impedance of the single-ended buffer is matched internally to 330 ohm, permitting direct connection to a 330ohm ceramic filter. A second filter can be connected between the first limiter and the second limiter to increase the receiver selectivity. Minimum input level of approximately 100mVRMS is required at the first limiter to generate a limited signal at the output of the second IF limiter. The first IF limiter provides a gain of approximately 34dB. A by-pass capacitor of 10nF should be used to connect LIM1INN to ground. The second IF limiter consists of 4 differential amplifiers and a differential output buffer. The second IF limiter provides an overall gain of approximately 40 dB. A by-pass capacitor of 10nF should be used to connect LIM2INN to ground. The limiter output is fed directly to the FSK demodulator. 4. Demodulator The demodulator demodulates the FSK signal. It consists of a quadrature multiplier, external LC tank circuit and a tuning circuit to adjust the tank resonant frequency. 5. Low Pass Filter (LPF) An internal operational amplifier connected with external RC components makes up the LPF. The bandwidth of LPF can be determined by external RC values. 6. Data Slicer The data slicer compares the output of low pass filter with internal reference voltage threshold, VREF and provides binary logic signals. The data slicer output is open drain type and will be pull high when data is muted. 7. RESET When SPI_CLOCK and SPI _LATCH are both held high simultaneously, bit 4 through bit 9 of the Mode Select Register will be reset to “Low” state. PRELIMINARY (March 2004, Version 0.4) 8 AMIC Technology, Corp. A7101 8. Serial to Parallel Interface (SPI) The SPI bus consists of three signals: SPI_DATA, SPI_CLOCK, and SPI_LATCH. This interface is used for external baseband controller to communicate with transmitter’s internal data and control registers. The contents of the registers are shown in the following register description sections. After setting SPI_LATCH signal to “Low” state, data on SPI_DATA is shifted into the internal shift register on the rising edge of SPI_CLOCK with MSB going in first. SPI_LATCH should be asserted at the end to latch the data packet into the register according to the address bits, bit 0 through bit 3, for each of the registers. All registers can only be written into except the Status Register which can only be read. When the content of the Status Register need to be fetched by external controller, external baseband controller need to make sure that the address bits are pointing to address location 0x0 for proper read operation. After the address bits are shifted into the SPI interface and latched by asserting SPI_LATCH, the SPI interface will be in Read Mode and the content of the Status Register will be shifted out on SPI_DATA pin. When all 12 status bits have been shifted out, the SPI bus will be put back to Write Mode automatically. A. Register Description Note: Convention used: 1: Logic level “ONE”. 0: Logic level “ZERO”. X: Don’t care. Synthesizer Configuration Register I (Write only / Address 0xf) Bit 15 Bit 14 Bit 13 MB6 MB5 MB4 Bit12 MB3 Bit11 MB2 Bit10 MB1 Bit9 MB0 Bit8 MA4 Bit7 MA3 Bit6 MA2 Bit5 MA1 Bit4 MA0 Bit3 1 Bit2 1 Bit 1 1 Bit 0 1 Bit6 R2 Bit5 R1 Bit4 R0 Bit3 0 Bit2 1 Bit 1 1 Bit 0 1 Synthesizer Configuration Register II (Write only / Address 0x7) Bit 15 Bit 14 Bit 13 X MB9 MB8 Bit12 MB7 Bit11 R7 Bit10 R6 Bit9 R5 Bit8 R4 Bit7 R3 Synthesizer Configuration Register I and Synthesizer Configuration Register II control synthesizer frequency settings where MA[4:0]: A counter[4:0], MB[9:0]: B counter[9:0], R[7:0]: R counter[7:0]. Valid range is from 2 to 255. The content of A, B and R registers are in unsigned binary format (i.e., 111112 = 3110). The equation for setting the synthesizer frequency is: (B must be greater than A). fvco = fcrystal * (32*B + A) / R fref =fcrystal / R Crystal Control Register (Write only / Address 0xb) Bit 15 Bit 14 Bit 13 Bit12 Bit11 Bit10 0 DP TXH2 TXH1 TXH0 TXL2 Bit9 TXL1 Bit8 TXL0 Bit7 FX3 Bit6 FX2 Bit5 FX1 Bit4 FX0 Bit3 1 Bit2 0 Bit 1 1 Bit 0 1 DP: Data Polarity. This control bit sets data output polarity. 0: Data is inverted. 1: Normal. TXH[2:0]: Reserved. Must be set to 0x0 for proper operation. TXL[2:0]: Reserved. Must be set to 0x0 for proper operation. FX[3:0]: Reserved. Must be set to 0x0 for proper operation. PRELIMINARY (March 2004, Version 0.4) 9 AMIC Technology, Corp. A7101 VCO Control Register (Write only / Address 0x3) Bit 15 Bit 14 Bit 13 VTH2 VTH1 VTH0 Bit12 T1 Bit11 T0 Bit10 HP0 Bit9 CP2 Bit8 CP1 Bit7 CP0 Bit6 VC2 Bit5 VC1 Bit4 VC0 Bit3 0 Bit2 0 Bit 1 1 Bit 0 1 VTH[2:0]: Set VCO tuning voltage range. Valid range is from 0x7 to 0x0. The setting of VTH varies inversely with the tuning voltage range such that when VTH = 0x0 tuning voltage range is from 0.3V to VDD-0.3V and when VTH = 0x7 tuning voltage range is from 1V to VDD-1V. T[1:0]: Reserved. Must be set to 0x0 for proper operation. HP0: RF output power level control. 0: Low power output (-16 dBm). 1: High power output (-6 dBm). CP[2]: Reserved. Must be set to 0x0 for proper operation. CP[1:0]: Charge pump output current control. Valid range is from 0x3 to 0x0. The setting of CP varies linearly with the output current level such that when CP = 0x0 output current = 100uA and when CP = 0x3 output current = 700uA. VC[2:0]: VCO band selection. RX Control Register (Write only / Address 0xd) Bit 15 Bit 14 Bit 13 T2 T1 T0 Bit12 MT2 Bit11 MT1 Bit10 MT0 Bit9 MTC Bit8 DM4 Bit7 DM3 Bit6 DM2 Bit5 DMI Bit4 DM0 Bit3 1 Bit2 1 Bit 1 0 Bit 0 1 T[2:0]: Reserved. Must be set to 0x3 for proper operation. MT[2:0]: Internal voltage threshold level for mute output (pin 37). Valid range is from 0x7 to 0x0. The setting of MT varies linearly with the voltage reference level such that when MT = 0x0 voltage reference = 1.44V and when MT = 0x7 voltage reference = 0.32V. MTC: RXDATA mute function enable. 0: Disable mute function. 1: Enable mute function. When RSSI output voltage level is higher than the threshold set by MT[2:0], RXDATA becomes inactive and pull high. DM[4:0]: Reference voltage level for demodulator tank center frequency tuning. Valid range is from 0x1f to 0x6. The setting of DM varies with the voltage reference level such that when DM = 0x6 voltage reference = 0.9V and when DM = 0x1f voltage reference = 2.4V. Note: When AFC function is used, set DM[4:0] to 0x0. PRELIMINARY (March 2004, Version 0.4) 10 AMIC Technology, Corp. A7101 Mode Select Register (Write only / Address 0x5) Bit 15 Bit 14 Bit 13 X X X Bit12 X Bit11 X Bit10 SC1 Bit9 SC0 Bit8 XOE Bit7 CM Bit6 EXTB Bit5 MD1 Bit4 MD0 Bit3 0 Bit2 1 Bit 1 0 Bit 0 1 SC[1:0]: Status Register bit 6 control. Depends on the setting of SC[1:0], bit 6 of the Status Register can represent system error flag, Battery-low detect or PLL lock detect. [1:0] = 10: System Error. [1:0] = 11: Battery-low detect. [1:0] = 0X: PLL lock detect. XOE: Crystal oscillator buffer output enable. 0: Output enable. 1: Output disable. The output will be forced to low level at this setting. CM: Calibration mode setting for VCO band selection. 0: manual calibration mode. Please see application note for detail description. 1: auto calibration mode. EXTB: Operating mode selection. 0: external mode. Operation mode is determined by external pin MODSEL0 and MODSEL1. 1: internal mode. Operation mode is determined by setting of MD[1:0]. MD[1:0]: Internal mode selection. [1:0] = 00: Sleep mode. Transceiver circuit is turned off. [1:0] = 01: Stand-by mode. X’TAL oscillator is turned on. [1:0] = 10: Transmit mode. [1:0] = 11: Receive mode. Status Register (Read only / Address 0x0) SR15 SR14 SR13 SR12 SR11 SR10 X X X X X X SR9 X SR8 X SR7 X SR6 S/B/P SR5 X SR4 X SR3 0 SR2 0 SR1 0 SR0 0 S/B/P: Depends on the setting of SC[1:0] in Mode Select Register, this bit can be used to reflect the status of System Error, Battery-low detect or PLL lock detect. System Error: 0: Normal; 1: Error. Battery-low detect: 0: Battery supply voltage below threshold. 1: Normal. PLL lock detect: 0: Unlock. 1: Lock. SR[3:0] address bits. PRELIMINARY (March 2004, Version 0.4) 11 AMIC Technology, Corp. A7101 B. SPI Timing Diagram Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 VH SPI_DATA VI SPI_CLOCK tCS tCH tCWH tCWL SPI_LATCH tEW tES Figure 3. SPI WRITE mode timing diagram After reading 12 bits, SPI is set to write mode SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 SR11 SR12 SR13 SR14 SR15 Bit15 Bit14 SPI_DATA SPI_CLOCK SPI_LATCH Figure 4. SPI READ mode timing diagram PRELIMINARY (March 2004, Version 0.4) 12 AMIC Technology, Corp. A7101 C. SPI Timing Specification Units Value Symbol Parameter Conditions Min Typ Max VH The High level of voltage Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Vl The low level of voltage Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram tCE SPI_DATA to SPI_CLOCK setup time Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram 50 ns tCH SPI_CLOCK to SPI_DATA hold time Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram 10 ns tCWH SPI_CLOCK pulse width high Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram 50 ns tCWL SPI_CLOCK pulse width low Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram 50 ns tES SPI_CLOCK to SPI_LATCH setup time Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram 50 ns tEW SPI_LATCH pulse width Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram 50 ns VCC-0.4 V 0.4 V Table 5. 9. PLL Section The sub-block diagram of PLL is shown in the following: R Counter 8 bit Input from reference crystal OSC. M Counter VCO input PRESCALER 32/33 A Counter 5 bit B Counter 10 bit Phase Detector CHPOUT Charge Pump Control Logic Figure 5. Phase Lock Loop Block Diagram PRELIMINARY (March 2004, Version 0.4) 13 AMIC Technology, Corp. A7101 A. M Counter The M counter consists of a 32/33 pre-scalar, a 5-bit A counter and a 10-bit B counter (where M = B*32+A). B. A and B counters A and B counters can be programmed through the Synthesizer Configuration Register I and II. The corresponding relations between the division ratio counters and Synthesizer Configuration Register are shown in the following table: M counter (DEC) 24000 24001 . 24031 24032 24033 . 24063 24064 . . 24992 24993 24994 24995 24996 24997 24998 24999 25000 B counter A counter B counter (binary) A counter (binary) (DEC) (DEC) MB9 MB8 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 MA4 MA3 MA2 MA1 MA0 750 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 750 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . 750 31 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 751 0 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 751 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 1 . . . . . . . . . . . . . . . . . 751 31 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 752 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 781 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 781 2 1 1 0 0 0 0 1 1 0 1 0 0 0 1 0 781 3 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 781 4 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 781 5 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 781 6 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 781 7 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 781 8 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 Table 6. C. R counter R counter division R (DEC) 2 3 . 100 101 102 . 120 . 255 R7 0 0 . 0 0 0 . 0 . 1 R6 0 0 . 1 1 1 . 1 . 1 R counter R4 R3 0 0 0 0 . . 0 0 0 0 0 0 . . 1 1 . . 1 1 R5 0 0 . 1 1 1 . 1 . 1 Note: Valid range of R counter is from 2 to 255. R2 0 0 . 1 1 1 . 0 . 1 R1 1 1 . 0 0 1 . 1 . 1 R0 0 1 . 0 1 0 . 1 . 1 Table 7. The equation for setting the synthesizer frequency is: fvco = fcrystal X (32 X B + A) / R PRELIMINARY (March 2004, Version 0.4) (B must be greater than A). 14 AMIC Technology, Corp. A7101 D. Phase Frequency Detector (PFD) and Charge Pump Phase Frequency Detector takes inputs from R counter and M counter, and produces an output proportional to the phase and frequency difference. The following shows a simplified schematic: VDD D1 DN Q1 VCK CLR Charge Pump Delay Element VDD CLR D1 Q1 CHPOUT UP RCK Figure 6. Phase Detector Block Diagram The PFD output waveform is shown below. VCK RCK UP DN CHPOUT LD Locked Figure 7. The PFD output waveform PRELIMINARY (March 2004, Version 0.4) 15 AMIC Technology, Corp. A7101 10. Crystal Oscillator and FSK modulation Section As shown in the following figure, it is a Colpitts type Crystal oscillator(XOSC). The FSK modulation is achieved by switching the external capacitor CX in the XOSC circuit. Internal External Output buffer XTALOUT XTAL1 Cx XTAL2 TXDATAIN CAPSW Figure 8. Crystal Oscillator and FSK modulation Circuit PRELIMINARY (March 2004, Version 0.4) 16 AMIC Technology, Corp. A7101 12.Chip setup procedure: (1) Auto calibration: For Transmitter Operation Step 1: Supply DC voltage to Pin 23, VIN. Step 2: Set Pin 20, MODSEL0 and Pin 24, MODSEL1 to logic 0 (ground) to ensure the IC is operating in external sleep mode after reset. Step 3: Reset IC by setting Pin 18, SPI_CLOCK and Pin 19, SPI _LATCH to logic high simultaneously for more than 1 us. Step 4: Setup IC’s internal control registers by configuring the followings: Synthesizer Configuration Register I, Synthesizer Configuration Register II, Crystal Control Register, and VCO Control Register. All registers should be written to in the order specified above. a. Synthesizer Configuration Register I and II: Set VCO center frequency. b. Crystal Control Register: Set TXDATA polarity. c. VCO Control Register: Set VCO tuning range and charge pump output current. Step 5: Set IC to TX mode. For internal mode operation, set Mode Select Register to 0x05E5. For external mode operation, set Pin 24, MODSEL1 to “logic 1”, Pin 20, MODSEL0 to “logic 0” and set Mode Select Register to 0x05A5. Whenever frequency is to be changed, or system error has been detected (by reading from the Status Register) the IC must be reset by repeating step 2, 3, 4-a, and 5. For Receiver Operation Step 1: Supply DC voltage to Pin 23, VIN. Step 2: Set Pin 20, MODSEL0 and Pin 24, MODSEL1 to logic 0 (ground) to ensure the IC is operating in external sleep mode after reset. Step 3: Reset IC by setting Pin 18, SPI_CLOCK and Pin 19, SPI _LATCH to logic high simultaneously for more than 1 us. Step 4: Setup IC’s internal control registers by configuring the followings: Synthesizer Configuration Register I, Synthesizer Configuration Register II, VCO Control Register, RX Control Register, and the Mode Select Register. All registers should be written to in the order specified above. a. Synthesizer Configuration Register I and II: Set VCO center frequency. b. VCO Control Register: Set VCO tuning range and charge pump output current. c. RX Control Register: Set mute threshold level, RXDATA mute function and reference voltage for demodulator tank center frequency tuning. When AFC function is used, DM[4:0] must be set to 0x0 for proper operation. Step 5: Set IC to RX mode. For internal mode operation, set Mode Select Register to 0x05F5. For external mode operation, set Pin 24, MODSEL1 to “logic 1”, Pin 20, MODSEL0 to “logic 1” and set Mode Select Register to 0x05B5. Whenever frequency is to be changed, or system error has been detected (by reading from the Status Register) the IC must be reset by repeating step 2, 3, 4-a, and 5. (2) Manual calibration: Please see application note (AN_CAL_A7101) for detail description. PRELIMINARY (March 2004, Version 0.4) 17 AMIC Technology, Corp. A7101 Application Circuit C26 C22 R14 C20 NC 56p 0 NC C19 27p R13 68K L1 4.7u R12 C23 C25 NC 4.7K 1n C18 1n TP1 TP2 C24 C21 10n 4 5 6 9 37 39 40 38 RSSI TANK2 41 TANK1 LPFINP 44 42 LPFOUT LPFINN 45 46 43 CAP3_AFC MUTE 30 VDD 28 27 26 100n R4 5.6p R5 0 100K 25 R6 C10 82K 56p C9 NC TP3 J1 CON16 24 23 22 21 20 19 18 17 16 15 13 82 + C13 10u/16V C11 100n R21 3.9K R7 SK107MA C12 LD MODSEL1 22p VIN LVOUT C28 10n 1 2 3 29 CHPOUT BP_REG C33 C30 30p CAP1_AFC CAPSW 12 32 BR_VCO EN_REG X1 12M 330 SK107MA 31 VT XTALOUT 11 C14 R8 CF1 BP_VCO XTAL2 10 C15 10n 33 MIXOUT REGFB C6 100p 10n 1 2 3 34 VDD_VCO XTAL1 MODSEL0 C5 47p R20 10K A7101 TXDATAIN 8 470P LIM1INP BP_BUF 7 C29 RFIO SPI_LATCH 1n SPI_CLOCK C4 LIM1INN SPI_DATA 1 IN 35 LIM2INP NC 330 CF2 LIM1OUT 14 OUT C16 R9 C17 10n 36 LIM2INN BR_RX U2 BPF U1 RXDATA VOUT 3 VDD_D 2 VDD_A LVIN 100n 100K 1% CAP2_AFC CMPVIP 1 2 EN_AFC C1 R1 47 48 NC VDD ANTENNA NC R2 VDD R11 30K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD TP4 C7 C27 100n 10u 16V R18 C31 75K 100p R19 100K C8 100n MODSEL1(option) MODSEL0(option) VIN EN_REG(option) SPI_LATCH SPI_CLOCK SPI_DATA GND LVOUT(option) LD(option) GND TXDATAIN MUTE(option) EN_AFC(option) XTALOUT(option) RXDATA Figure 10. Application Circuit for Transceiver (Data rate = 64Kbps) C3 C5 10p 20p C1 R2 68K L1 5.6p 4.7u R3 C4 680 1n TP1 C7 1n TP2 C2 R4 8 C20 22p 9 10 X1 12M C21 68p 11 12 RSSI 37 MUTE 39 40 38 TANK2 TANK1 41 LPFINP 42 LPFINN 44 43 LPFOUT CAP3_AFC 47 45 46 LIM1INN RFIO LIM1INP A7101 BP_BUF TXDATAIN MIXOUT VDD_VCO XTAL1 BP_VCO XTAL2 VT XTALOUT BR_VCO CAPSW CHPOUT BP_REG C22 MODSEL1 7 NC VIN 6 LIM1OUT EN_REG 10n LD 36 C13 10n 470 10n R8 CF1 35 33 C11 10n IF FILTER R7 32 C16 R30 470 C14 10n 31 VDD 82 C17 10U/16V 1 2 3 34 10n 62K C26 10p 30 C12 29 C18 28 27 26 R9 10n R11 100K R12 1K 100n 1M C19 20p R29 18K 25 R13 47K C27 20p C25 470p 24 23 22 21 20 19 18 17 16 VDD 15 14 13 100n J1 C23 100n C15 R6 BR_RX REGFB C9 U1 LIM2INP MODSEL0 5 TRX_OUT RXDATA SPI_LATCH 4 1 ANTENNA 30K LIM2INN SPI_CLOCK 3 SPI_DATA 2 VOUT 100n 100K 1% VDD_D R5 LVIN RXDATA VDD_A LVOUT 1 CAP1_AFC C10 CAP2_AFC CMPVIP VDD EN_AFC 48 10n C24 10u/16V R17 NC R16 NC C28 RXDATA 100n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN EN_REG SPI_LATCH SPI_CLOCK SPI_DATA LVOUT LD(option) TXDATA MUTE EN_AFC XTALOUT RXDATA GND CON15 Figure 11. Application Circuit for Transceiver (Data rate = 250Kbps) PRELIMINARY (March 2004, Version 0.4) 18 AMIC Technology, Corp. A7101 C26 C22 R14 C20 NC 56p 0 NC C19 27p R13 68K L1 4.7u R12 C23 C25 NC 4.7K 1n C18 1n TP1 TP2 C24 C21 10n R2 VDD 37 39 38 RSSI TANK2 TANK1 42 41 43 44 45 40 LPFINP LPFINN LPFOUT CAP3_AFC CAP1_AFC MUTE LD C17 10n 330 10n CF2 35 1 2 3 34 33 C15 10n 330 SK107MA 1 2 3 31 28 27 26 10n R4 22p R5 0 100K 25 R6 56K C10 220p C9 NC J1 CON16 C31 75K VDD + C13 10u/16V C11 100n R18 82 C12 C27 10u 16V R7 SK107MA 30 29 TP4 R19 100K 10n CF1 32 VDD C7 C14 R8 24 23 22 36 TP3 100n 21 C30 47p R21 NC BP_REG 13 NC CHPOUT MODSEL1 C28 BR_VCO CAPSW VIN C33 VT XTALOUT EN_REG 12 XTAL2 REGFB 11 MODSEL0 9 10 VDD_VCO BP_VCO 20 C6 100p MIXOUT XTAL1 19 R20 10K A7101 TXDATAIN 18 470P X1 12M LIM1INP BP_BUF SPI_LATCH 8 C5 47p RFIO SPI_CLOCK 7 C29 LIM1INN SPI_DATA 6 LIM1OUT NC VOUT 0.1u BR_RX 17 C4 BPF C16 R9 LIM2INN LIM2INP 16 IN 5 U1 RXDATA 15 OUT 1 46 48 4 U2 2 EN_AFC CMPVIP 3 VDD_D 2 LVIN 100n 100K 1% 14 R1 VDD_A LVOUT 1 CAP2_AFC C1 47 NC VDD ANTENNA R11 30K NC 100p C8 100n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MODSEL1(option MODSEL0(option VIN EN_REG(option) SPI_LATCH SPI_CLOCK SPI_DATA GND LVOUT(option) LD(option) GND TXDATAIN MUTE(option) EN_AFC(option) XTALOUT(option RXDATA Figure 12. Application Circuit for Receiver PRELIMINARY (March 2004, Version 0.4) 19 AMIC Technology, Corp. A7101 Ordering Information Part No. Package A71P024P01Q QFN 48L PRELIMINARY (March 2004, Version 0.4) 20 AMIC Technology, Corp. A7101 Package Information unit: inches/mm aaa C QFN 48L (7 x 7mm) Outline Dimensions θ C A3 C L A1 E1 E A A A2 D D D1 B b Detail B 0.05 C A A2 D See Detail B Seating Plane bbb M C A B C E2 b D2 0.6max See Detail A 0.6max b Symbol Detail A e Dimensions in inches Min Nom Max Min Nom Max A 0.031 0.033 0.039 0.80 0.85 1.00 A1 0.000 0.001 0.002 0.00 0.02 0.05 A2 - 0.026 0.039 - 0.65 1.00 A3 - 0.008 - - 0.20 - b 0.007 0.009 0.012 0.18 0.23 0.30 D 0.276 BSC D1 D2 7.00 BSC 0.266 BSC 0.089 0.185 6.75 BSC 0.207 2.25 4.70 E 0.276 BSC 7.00 BSC E1 0.266 BSC 6.75 BSC E2 0.089 e PRELIMINARY Dimensions in mm 0.185 0.207 2.25 0.020 BSC 4.70 5.25 5.25 0.5 BSC L 0.012 0.016 0.020 0.30 0.40 θ 0° - 12° 0° - 12° aaa - - 0.010 - - 0.25 bbb - - 0.004 - - 0.10 (March 2004, Version 0.4) 21 0.50 AMIC Technology, Corp.