DDR12 Series | Tracking Dual Output DC-DC Converters DDR12 SERIES Dual output High current dual-output power module for DDR memory Single compact module provides 25 A @ 2.5 V for Vddq supply and 8 A @ 1.25 V for Vtt termination Tracking dual output voltages (1.25 V @ 8 A, 2.5 V @ 25 A) Output voltage remote sense Sink capability for logic terminations Power good output signal Overvoltage protection Overcurrent protection Remote ON/OFF Available RoHS compliant The dual output DDR12-25D08-AJ is Remote sense on Vddq and remote specifically designed to meet the power ON/OFF facilities are included as standard, needs of double data rate memory DIMMS and the converter is protected against over- and associated memory control logic. The current and over-voltage conditions. Vtt output tracks the Vddq output, while the Vtt output can sink current as required by logic terminations.This converter offers typical efficiencies greater than 84% when operated at 50% load or greater. This model features a wide input range as well as trimmable output voltages. [ 2 YEAR WARRANTY ] 1 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 SeriesDual | 15W DC/DC DDR12 Series | SXA10 Tracking Output DC-DC Converters Stresses in excess of the maximum ratings can cause permanent damage to the device. Operation of the device is not implied at these or any other conditions in excess of those given in the specification. Exposure to absolute maximum ratings can adversely affect device reliability. Absolute Maximum Ratings Characteristic Symbol Min Input voltage - continuous Vin (cont) -0.3 Input voltage - nominal Vin (nom) Operating temperature Top Storage temperature Tstorage Output current Iddq (max) Itt (max) Typ Max Units Notes and Conditions 13.2 Vdc Vin(+) - Vin(-) 0 80 ºC Refer to derating guidelines and Note 1 -40 125 ºC 25 8 A A 12 All specifications are typical at Vin(nom), Vddq = 2.5 V, Vtt = 1.25 V and full load. Tests were performed at 25 ˚C unless otherwise stated. Input Characteristics Characteristic Symbol Min Typ Max Units Input voltage - operating Vin (oper) lin lin (off) 10.8 12 13.2 Vdc Characteristic Symbol Min Typ Input voltage - turn on Vin (on) 10 Input voltage - turn off Turn on delay - enabled, then power applied Vin (off) Tdelay (power) 9.7 Turn on delay - power applied, then enabled Tdelay (enable) 5 ms Output to POWER GOOD delay Tdelay 3 ms Rise time Trise 2 ms Input current - min. load Input current - Quiescent 400 20 Notes and Conditions mAdc mAdc Vin (min) - Vin (max), enabled Converter disabled Max Units Notes and Conditions 10.2 10.4 Vdc 9.9 5 10.1 Vdc ms Turn On/Off 2 With the enable signal asserted, this is the time from when the input voltage reaches the minimum specified operating voltage until the POWER GOOD is asserted high Vin = Vin (nom), then enabled. This is the time taken until the POWER GOOD is asserted high Output voltage in full regulation to POWER GOOD asserted high File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters Signal Electrical Interface Characteristic - Signal Name Symbol Min Typ Max Units At remote/control ON/OFF pin Open collector or equivalent compatible Notes and Conditions See Notes 2 and 3 See Application Note 133 for Remote ON/OFF details High level input voltage Vih Low level input voltage ViI Low level input current Iil (max) 2.0 0.80 1 V Converter guaranteed on when OUTEN pin is greater than Vih (max) V mA Converter guaranteed off when OUTEN pin is less than Vil (max) ViI = 0.0 V Units Notes and Conditions Hours Telcordia SR-332 Reliability and Service Life Characteristic Symbol Min Mean time between failure MTBF TBD 3 www.artesyn.com Typ Max File Name: lf_ddr12.pdf Rev: 29 Nov 2005 SeriesDual | 15W DC/DC DDR12 Series | SXA10 Tracking Output DC-DC Converters Other Specifications Characteristic Symbol Switching frequency Fsw Min Weight Typ Max Units Notes and Conditions 300 kHz Fixed frequency 34 g Referenced ETSI standards: ETS 300 019: Environmental conditions and environmental tests for telecommunications equipment ETS 300 019: Part 1-3 (1997) Classification of environmental conditions stationary use at weather protected locations ETS 300 019: Part 2-3 (1997) Specification of environmental tests stationary use at weather protected locations EMC Electromagnetic Compatibility Phenomenon Port Standard Test level Enclosure EN61000-4-2 6 kV contact 8 kV air Criteria Notes and conditions Immunity: ESD As per ETS 300 386-1 table 5 Performance criteria: NP: Normal Performance: EUT shall withstand applied test and operate within relevant limits as specified without damage. RP: Reduced Performance: EUT shall withstand applied test. Reduced performance is permitted within specified limits, resumption to normal performance shall occur at the cessation of the test. LFS: Loss of Function (self recovery): EUT shall withstand applied test without damage, temporary loss of function permitted during test. Unit will self recover to normal performance after test. Referenced ETSI standards: ETS 300 386-1 table 5 (1997): Public telecommunication network equipment, EMC requirements ETS 300 132-2 (1996): Power supply interface at the input to telecommunication equipment: Part 2 operated by direct current (dc) ETR 283 (1997): Transient voltages at interface A on telecommunication direct current (dc) power distributions Material Ratings Characteristic - Signal Name Notes and Conditions Flammability rating Material type UL94V-0 FR4 PCB Model Numbers Model Number DDR12-25D08-AJ 4 Input Voltage Output Voltage Output Current (Max.) Typical Efficiency Load Regulation 10.8-13.2 Vdc 2.32-2.75 Vdc 1.16-1.375 Vdc 25 A 8A 84% ±1.0% See Tracking Spec. File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters Input Characteristics Characteristic Symbol Min Typ Max Units Notes and Conditions Input current - operating Iin 7.2 Adc Reflected ripple current Iin (ripple) 35 50 Input capacitance - internal filter Cinput 420 mA rms measured with external filter. mA pk-pk See Application Note 133 for details µF Input capacitance - external filter Cbypass 10 µF Use large value ceramic Max Units Notes and Conditions 2.750 Vdc Vdc With no external trim resistor For details on trimming the output voltage see Application Note 133 Electrical Charact. - Vddq O/P Characteristic Symbol Min Nominal set-point voltage Output voltage range Vddq (nom) Vddq 2.316 Typ 2.316 Output set-point accuracy ±1.5 ±2.5 % Using 1% trim resistors measured at minimum load Load regulation +0/-1 +1/-2 % Vary load with line held constant (Voltage typically drops with load) Line regulation ±0.1 ±0.2 % Vary line with load held constant Cross regulation ±0.4 ±0.6 Vary load on Vtt with load on Vddq held constant Temperature co-efficient Ripple and noise 0.2 50 mV/ºC mV pk-pk With recommended external load capacitance and 5 Hz to 20 MHz bandwidth Load transient response peak deviation 3 % Peak deviation for 75% to 100% step load, di/dt = 0.04 A/µs Load transient response recovery 200 µs Settling time to within 1% of output setpoint voltage for 75% to 100% step load 3000 µF Recommended 3 x 560 µF with total ESR of 5 mΩ and additional high-quality ceramic capacitors. Consult factory for other capacitance Overshoot 2.0 % Nominal output at turn-on Undershoot 150 mVdc 25 Adc External load capacitance Cext (Vddq) Output current - continuous Iddq Output current - short circuit Isc-ddq 5 www.artesyn.com 1000 1680 1.5 0 A rms Latching short circuit protection power or enable needs to be cycled File Name: lf_ddr12.pdf Rev: 29 Nov 2005 SeriesDual | 15W DC/DC DDR12 Series | SXA10 Tracking Output DC-DC Converters Electrical Charact. - Vtt O/P Characteristic Symbol Min Tracking accuracy Typ Max Units Notes and Conditions 12 25 mV Measured at converter pins (=Vddq/2 - Vtt) 30 mV pk-pk With recommended external load capacitance and 5 Hz to 20 MHz bandwidth Ripple and noise Load transient response peak deviation 3 % Peak deviation for 75% to 100% step load, di/dt = 8 A/µs Load transient response recovery 200 µs Settling time to within 1% of output setpoint voltage for 75% to 100% step load µF Recommended 3 x 560 µF with total ESR of 5 mΩ and additional high-quality ceramic capacitors. External load capacitance Cext (Vtt) 1000 1680 3000 Consult factory for other capacitance Output current - continuous Itt Output current - short circuit Isc-tt 0 8 0 Adc A rms Latching short circuit protection power or enable needs to be cycled Units Notes and Conditions Protection and Control Features Characteristic Symbol Overcurrent limit inception Iddq Itt Min Typ Max 36 14 Adc Adc Efficiency Characteristic Symbol Efficiency η 6 Min Typ 84 Max Units Notes and Conditions % Full load File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output 92 25 20 0 m/s (0 LFM) 0.5 m/s (100 LFM) 1 m/s (200 LFM) 1.5 m/s (300 LFM) 2 m/s (400 LFM) 15 10 90 88 Low Line Nom Line High Line 86 84 82 5 20 30 40 50 60 70 80 AMBIENT TEMPERATURE (ºC) 7 EFFICIENCY (%) OUTPUT CURRENT (A) DC-DC Converters 0 20 40 60 80 100 FULL LOAD CURRENT (%) Figure 1: Thermal Derating Curve Figure 2: Efficiency vs Load and Line Figure 3: Typical Ripple & Noise Channel 1: Vddq Output Ripple, Channel 2: Vtt Output Ripple Figure 4: Typical Power-up Channel 1: Vddq Output Channel 2: Vtt Output Channel 3: Power Good Signal Figure 5: Transient Response 75-100% Vtt Source, Rising Edge (Channel 2: Vtt Output Voltage Deviation, Channel 4: Current load step at 1 A/div) Figure 6: Transient Response 75-100% Vtt Source, Falling Edge (Channel 2: Vtt Output Voltage Deviation, Channel 4: Current load step at 1 A/div) www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005 SeriesDual | 15W DC/DC DDR12 Series | SXA10 Tracking Output DC-DC Converters Figure 7: Transient Response 75-100% Vddq Rising Edge, (Channel 1: Vddq Output Voltage Deviation, Channel 4: Current load step at 2 A/div) Figure 8: Transient Response 75-100% Vddq Falling Edge, (Channel 1: Vddq Output Voltage Deviation, Channel 4: Current load step at 2 A/div) Figure 9: Input Ripple Voltage measurement, Vin = 12 V, Vddq = 25 A, Vtt = 8 A (Channel 1: Vin Ripple Voltage) 8 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output 0.062 (1.57) PCB 0.260 (6.71) 0.170 (4.39) 0.500 (12.67) Ref DC-DC Converters 3.000 (76.20) 1.200 (30.48) 0.150 (3.81) Typ 0.025 (0.64) TYP. PIN 1 PIN 7 PIN 8 0.025 (0.64) Typ 0.050 (1.30) TYP. PIN 22 0.100 (2.54) Typ 1.100 (27.94) 0.250 (6.35) Dimensions in Inches (mm) Tolerances (unless otherwise specified) 2 Places ±0.02 (±0.51) 3 Places ±0.010 (±0.25) Pin Connections Pin No. Function Pin No. Function J1-1 Power Good J2-5 Ground J1-2 Output Enable J2-6 Ground J1-3 Ground J2-7 Ground J1-4 Ground J2-8 Ground J1-5 12V Input J2-9 Vddq Sense - J1-6 12V Input J2-10 Vddq Sense + J1-7 12V Input J2-11 Vddq J2-1 Vtt Ref. J2-12 Vddq J2-2 Vtt J2-13 Vddq J2-3 Vtt J2-14 Vddq J2-4 Ground J2-15 Vddq Figure 10: Mechanical Drawing and Pinout Table 9 www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005 SeriesDual | 15W DC/DC DDR12 Series | SXA10 Tracking Output DC-DC Converters Note 1 For maximum reliability temperature at the Thermal Reference Point, shown in Figure 11, should not exceed 100 ºC. Thermal Reference Point Note 2 The control pin is referenced to Vin- Note 3 The DDR12 is supplied as standard with active High logic. Control input pulled low: Unit Disabled Control input left open: Unit Enabled Note 4 Thermal reference set up: Unit mounted on an edge card test board 215 mm x 115 mm. Test board mounted vertically. For test details and recommended set-up see Application Note 133. Figure 11: Thermal Reference Points CAUTION: Hazardous internal voltages and high temperatures. Ensure that unit is accessible only to trained personnel. The user must provide the recommended fusing in order to comply with safety approvals. 10 10 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters NORTH AMERICA e-mail: [email protected] 800 769 7274 + 508 628 5600 EUROPEAN LOCATIONS e-mail: [email protected] IRELAND + 353 24 93130 AUSTRIA + 43 1 80150 FAR EAST LOCATIONS e-mail: [email protected] HONG KONG + 852 2699 2868 Longform Datasheet © Artesyn Technologies® 2005 The information and specifications contained in this datasheet are believed to be correct at time of publication. However, Artesyn Technologies accepts no responsibility for consequences arising from printing errors or inaccuracies. Specifications are subject to change without notice. No rights under any patent accompany the sale of any such product(s) or information contained herein. 11 www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005