AVAGO ACPL

ACPL-267XL, ACPL-268KL, ACPL-560XL,
ACPL-563XL, 5962-08242*
Hermetically Sealed, 3.3V High Speed, High CMR,
Logic Gate Optocouplers
Data Sheet
*See Selection Guide for full matrix of part numbers.
Description
Features
These units are single and dual channel, hermetically
sealed optocouplers. The products are capable of operation and storage over the full military temperature range
and can be purchased as either standard commercial
product or with full MIL-PRF-38534 Class Level H or K
testing or from DLA Drawing 5962-08242. All devices are
manufactured and tested on a MIL-PRF-38534 certified
line and are included in the DLA Qualified Manufacturers
List QML-38534 for Hybrid Microcircuits.
 Low power consumption
Truth Table (Positive Logic)
 Performance guaranteed over full military
temperature range: -55°C to +125°C
Multichannel Devices
 3.3V supply voltages
 Dual marked with device part number and DLA drawing number
 Manufactured and tested on a MIL-PRF-38534
Certified Line
 QML-38534, Class H and K
 Three hermetically sealed package configurations
Input
Output
 High speed: 10 Mbd typical
On (H)
L
 CMR: > 10,000 V/μs typical
Off (L)
H
 1500 Vdc withstand test voltage
 TTL circuit compatibility
Single Channel DIP
 HCPL-260L/060L/263L/063L function compatibility
Input
Enable
Output
On (H)
H
L
Applications
Off (L)
H
H
 Military and aerospace
On (H)
L
H
 High reliability systems
Off (L)
L
H
 Transportation, medical, and life critical systems
 Line receiver
Functional Diagram
Multiple channel devices available
VCC
VE
VOUT
 Voltage level shifting
 Isolated input line receiver
 Isolated output line driver
 Logic ground isolation
 Harsh industrial environments
 Isolation for computer, communication, and test
equipment systems
GND
The connection of a 0.1 μF bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Each channel contains a GaAsP light emitting diode
which is optically coupled to an integrated high speed
photon detector. The output of the detector is an open
collector Schottky clamped transistor. Internal shields
provide a guaranteed common mode transient immunity specification of 1000 V/μs. Package styles for these
parts are 8 and 16 pin DIP through hole (case outlines
P and E respectively). Devices may be purchased with a
variety of lead bend and plating options. See Selection
Guide Table for details. Standard Microcircuit Drawing
(SMD) parts are available for each package and lead
style.
Because the same electrical die (emitters and detectors)
are used for each channel of each device listed in this
data sheet, absolute maximum ratings, recommended
operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts. Occasional exceptions exist due to
package variations and limitations, and are as noted.
Additionally, the same package assembly processes and
materials are used in all devices.
Selection Guide – Package Styles and Lead Configuration Options
Package
16 Pin DIP
8 Pin DIP
8 Pin DIP
Lead Style
Through Hole
Through Hole
Through Hole
Channels
2
1
2
Common Channel Wiring
VCC, GND
None
VCC, GND
Withstand Test Voltage
1500 Vdc
1500 Vdc
1500 Vdc
Avago Part # & Options
Standard Commercial
ACPL-2670L
ACPL-5600L
ACPL-5630L
MIL-PRF-38534, Class H
ACPL-2672L
ACPL-5601L
ACPL-5631L
MIL-PRF-38534, Class K
ACPL-268KL
ACPL-560KL
ACPL-563KL
Standard Lead Finish
Gold Plate
Gold Plate
Gold Plate
Solder Dipped*
Option -200
Option -200
Option -200
Butt Cut/Gold Plate
Option -100
Option -100
Option -100
Gull Wing/Soldered*
Option -300
Option -300
Option -300
Prescript for all below
5962-
5962-
5962-
Gold Plate
0824203HEC
0824201HPC
0824202HPC
Solder Dipped*
0824203HEA
0824201HPA
0824202HPA
Butt Cut/Gold Plate
0824203HUC
0824201HYC
0824202HYC
Butt Cut/Soldered*
0824203HUA
0824201HYA
0824202HYA
Gull Wing/Soldered*
0824203HTA
0824201HXA
0824202HXA
Prescript for all below
5962-
5962-
5962-
Gold Plate
0824203KEC
0824201KPC
0824202KPC
Solder Dipped*
0824203KEA
0824201KPA
0824202KPA
Butt Cut/Gold Plate
0824203KUC
0824201KYC
0824202KYC
Butt Cut/Soldered*
0824203KUA
0824201KYA
0824202KYA
Gull Wing/Soldered*
0824203KTA
0824201KXA
0824202KXA
Class H SMD Part #
Class K SMD Part #
* Solder contains lead.
2
Functional Diagrams
16 Pin DIP
8 Pin DIP
8 Pin DIP
Through Hole
Through Hole
Through Hole
2 Channels
1 Channel
2 Channels
1
16
2
V CC
15
3
V O1
14
4
V CC
1
VE
2
13
V O2
5
6
12
11
GND
7
10
V OUT
3
4
GND
8
1
7
2
VCC
VO1
VO2
3
6
4
5
GND
8
7
6
5
9
8
Note: Dual channel devices have common VCC and ground. Single channel DIP has an
enable pin 7. All diagrams are “top view.”
Outline Drawings
;;;;;
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
0.51 (0.020)
MIN.
4.45 (0.175)
MAX.
3.81 (0.150)
MIN.
2.29 (0.090)
2.79 (0.110)
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
8 Pin DIP Through Hole, 1 and 2 Channels
Device Marking
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
Avago LOGO
Avago P/N
DLA SMD [1]
DLA SMD [1]
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
* 50434
Note 1. Qualified parts only
3.81 (0.150)
MIN.
0.51 (0.020)
MIN.
0.51 (0.020)
MAX.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3
COMPLIANCE INDICATOR, [1]
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Avago CAGE CODE [1]
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available
on standard commercial, class H & class K product in 8 and 16 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
Lead finish is solder dipped rather than gold plated. This option is available on standard commercial, class H
and class K products in 8 and 16 pin DIP. DLA Drawing part numbers contain provisions for lead finish.
300
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on standard commercial, class H & class K product in 8 and 16 pin DIP (see drawings below for details).
This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
5° MAX.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Solder contains lead.
4
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
1.07 (0.042)
1.32 (0.052)
Absolute Maximum Ratings
No derating required up to +125°C.
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-65
+150
°C
Operating Temperature
TA
-55
+125
°C
Case Temperature
TC
+170
°C
Junction Temperature
TJ
+175
°C
260 for 10 sec
°C
Lead Solder Temperature
Peak Forward Input Current
(each channel, ≤1 ms duration)
IF(PEAK)
40
mA
Average Input Forward Current (each channel)
IF(AVG)
20
mA
35
mW
Reverse Input Voltage (each channel
VR
5
V
Supply Voltage (1 minute maximum)
VCC
7.0
V
Output Current (each channel)
IO
25
mA
Output Voltage (each channel)
VO
7
V
Output Power Dissipation (each channel)
PO
40
mW
Package Power Dissipation (each channel)
PD
200
mW
VE
3.6
V
Input Power Dissipation (each channel)
Single Channel Product Only
Enable Input Voltage
8 Pin Ceramic DIP Single Channel Schematic
Note enable pin 7. An external 0.01 μF to 0.1 μF bypass capacitor must
be connected between VCC and ground for each package type.
ESD Classification
MIL-PRF-38534 and MIL-STD-883, Method 3015
ACPL-560L/01L/0KL, 5962-0824201
(B), Class 1B
ACPL-5630L/31L/3KL, 5962-0824202
(A), Class 3A
ACPL-2670L/72L/268KL, 5962-0824203
(), Class 2
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level, Each Channel
IFL
0
250
μA
Input Current, High Level, Each Channel
IFH
10
20
mA
Supply Voltage, Output
VCC
3.0
3.6
V
Fan Out (TTL Load) Each Channel
N
5
6
Recommended Operating Conditions (cont’d.)
Single Channel Product Only[10]
Parameter
Symbol
Min.
Max.
Units
High Level Enable Voltage
VEH
2.0
VCC
V
Low Level Enable Voltage
VEL
0
0.8
V
Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
High Level
Output Current
IOH
VCC = 3.3 V, VO = 3.3 V,
IF = 250 μA
Low Level
Output Voltage
VOL
Current Transfer
Ratio
Logic
High
Supply
Current
Single
Channel
Logic
low
Supply
Current
Single
Channel
Group
A[13]
Subgroups
Typ.*
Max.
Units
Fig.
Note
1, 2, 3
6
250
μA
1
1
VCC = 3.3 V, IF = 10 mA,
IOL (Sinking) = 10 mA
1, 2, 3
0.3
0.6
V
2
1, 8
hF CTR
VO = 0.6 V, IF = 10 mA,
VCC = 3.3 V
1, 2, 3
ICCH
VCC = 3.3 V, IF = 0 mA
1, 2, 3
Min.
100
VCC = 3.3 V,
IF1 = IF2 = 0 mA
Dual
Channel
ICCL
VCC = 3.3 V,
IF = 20 mA
1, 2, 3
VCC = 3.3 V,
IF1 = IF2 = 20 mA
Dual
Channel
IF = 20 mA
1, 2
Input Forward
Voltage
VF
Input Reverse
Breakdown Voltage
BVR
IR = 10 μA
Input-Output
Leakage Current
II-O
RH ≤ 65%, TA = 25°C
t = 5 s, VI-O = 1500 Vdc
1
Capacitance Between
Input/ Output
CI-O
f = 1 MHz, TC = 25°C
4
1, 2, 3
%
1
1
5
11
mA
10
22
mA
6
15
mA
12
30
mA
1.75
V
1.55
3
*All typical values are at VCC = 3.3 V, TA = 25°C.
6
Limits
1
3
1
1.85
5
1.0
V
1
1.0
μA
2, 7
4.0
pF
1, 3,
13
Electrical Characteristics (cont’d) TA = -55°C to +125°C unless otherwise specified
Group A[13]
Subgroups
Parameter
Symbol
Test Conditions
Propagation Delay
Time to High Output
Level
tPLH
VCC = 3.3 V, RL = 510 Ω,
CL = 50 pF, IF = 13 mA
Propagation Delay
Time to Low Output
Level
tPHL
Limits
Min.
9
Typ.*
Max.
Units
Fig.
Note
43
100
ns
4, 5, 6
1, 5
10, 11
140
9
54
10, 11
100
ns
120
RL = 510 Ω, CL = 50 pF,
IF = 13 mA
9, 10, 11
|CMH|
VCM = 50 V (PEAK),
VCC = 3.3 V,
VO (min.) = 2 V,
RL = 510 Ω, IF = 0 mA
9, 10, 11
1000
>10000
V/μs
7
1, 6,
13
|CML|
VCM = 50 V (PEAK),
VCC = 3.3 V,
VO (max.) = 0.8 V,
RL = 510 Ω, IF = 10 mA
9, 10, 11
1000
>10000
V/μs
7
1, 6,
13
1, 2, 3
-2.0
-0.54
mA
2.0
Output Rise Time
tLH
Output Fall Time
tHL
Common Mode
Transient
Immunity at
High Output
Level
Common Mode
Transient
Immunity at Low
Output Level
20
90
8
40
ns
1
Single Channel Product Only
Low Level
Enable Current
IEL
VCC = 3.3 V,
VE = 0.5 V
High Level
Enable Voltage
VEH
1, 2, 3
Low Level
Enable Voltage
VEL
1, 2, 3
V
0.8
9
V
*All typical values are at VCC = 3.3 V, TA = 25°C.
Typical Characteristics, TA = 25°C, VCC = 3.3 V
Parameter
Sym.
Typ.
Units
Test Conditions
Fig.
Note
Input Capacitance
CIN
60
pF
VF = 0 V, f = 1 MHz
1
Input Diode Temperature
Coefficient
ΔVF
ΔTA
-1.5
mV/°C
IF = 20 mA
1
Resistance (Input-Output)
RI-O
1012
Ω
VI-O = 500 V
2
Propagation Delay Time of
Enable from VEH to VEL
tELH
32
ns
Propagation Delay Time of
Enable from VEL to VEH
tEHL
28
ns
RL = 510 Ω, CL = 50 pF
IF = 13 mA, VEH = 3 V,
VEL = 0V
Input-Input
Leakage Current
II-I
0.5
nA
Relative Humidity ≤ 65%
VI-I = 500 V, t = 5 s
4
Resistance (Input-Input)
RI-I
1012
Ω
VI-I = 500 V
4
Capacitance (Input-Input)
CI-I
0.55
pF
f = 1 MHz
4
Single Channel Product Only
8, 9
1, 10
1, 11
Dual Channel Product Only
7
Notes:
1. Each channel.
2. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all output
leads or terminals shorted together.
3. Measured between each input pair shorted together and all output connections for that channel shorted together.
4. Measured between adjacent input pairs shorted together for each multichannel device.
5. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of
the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point
on the trailing edge of the output pulse.
6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic
high state (VO > 2.0 V).
7. This is a momentary withstand test, not an operating condition.
8. It is essential that a bypass capacitor (0.01 to 0.1 μF, ceramic) be connected from VCC to ground. Total lead length between both ends of
this external capacitor and the isolator connections should not exceed 20 mm.
9. No external pull up is required for a high logic state on the enable input.
10. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on
the trailing edge of the output pulse.
11. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on
the leading edge of the output pulse.
12. Standard commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). Class H and K parts receive 100% testing at 25, 125, and
-55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits
specified for all lots not specifically tested.
80
60
40
20
0
-60 -40 -20 0
20 40 60 80 100 120 140
TA - TEMPERATURE - °C
Figure 1. High Level Output Current vs. Temperature.
8
5
VCC = 3.3 V
VO = 3.3 V
IF = 250 μA
VCC = 3.3 V
TA = 25 °C
4
VO - OUTPUT VOLTAGE -V
IOH - HIGH LEVEL OUTPUT CURRENT - uA
100
3
RL
510 Ω
2
1 kΩ
4 kΩ
1
0
1
2
3
4
5
6
7
IF - INPUT DIODE FORWARD CURRENT - mA
Figure 2. Input-Output Characteristics.
Figure 3. Input Diode Forward Characteristics.
D.U.T.
VCC
INPUT
MONITORING
NODE
IF
VO
120
VO
100
RL
0.01 μF
BYPASS
CL*
PROPAGATION DELAY - ns
PULSE
GENERATOR
ZO = 50Ω
tH = 5 ns
3.3 V
GND
Rm
* CLINCLUDES PROBE AND STRAY WIRING CAPACITANCE.
VCC = 3.3 V
R L = 510 Ω
TA = 25°C
80
tPLH
60
40
tPHL
20
0
10 11 12 13 14 15 16 17 18 19 20
IF - PULSE INPUT CURRENT - mA
Figure 5. Propagation Delay, tPHL and tPLH vs. Pulse Input
Current, IFH.
Figure 4. Test Circuit for tPHL and tPLH.*
D.U.T.
B
II
A
120
PROPAGATION DELAY - ns
100
VCC
+3.3 V
510 Ω
OUTPUT VO
MONITORING
0.01 μF NODE
BYPASS
VCC = 3.3 V
IF = 13 mA
RL = 510 Ω
GND
80
VFF
tPLH
+
PULSE GEN.
60
40
VCM
tPHL
20
0
-60 -40 -20 0
20 40 60 80 100 120 140
TA - TEMPERATURE - °C
Figure 6. Propagation Delay vs. Temperature.
9
Figure 7. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms.
OUTPUT VE
MONITORING
NODE
+3.3 V
D.U.T.
VCC
VE
IF = 13 mA
RL
VOUT
0.01 μF
BYPASS
OUTPUT VO
MONITORING
CL* NODE
GND
* CL INCLUDES PROBE AND
STRAY WIRING CAPACITANCE.
tE - ENABLE PROPAGATION DELAY - ns
80
PULSE
GENERATOR
ZO = 50 Ω
tr = 5 ns
VCC = 3.3 V
70 VEH = 3.0 V
VEL = 0 V
60 IF = 13 mA
50
t ELH
40
30
t EHL
20
10
0
-60 -40 -20 0
20 40 60 80 100 120 140
TA - TEMPERATURE - °C
Figure 9. Enable Propagation Delay vs. Temperature.
Figure 8. Test Circuit for tEHL and tELH.
VCC
+5.5 V
VOC
+5.5 V
D.U.T.*
VCC
(EACH INPUT)
+
VIN
0.01 μF
200 Ω
5.3 V
(EACH OUTPUT)
GND
200 Ω
(EACH OUTPUT)
CONDITIONS: IF = 20 mA
IO = 25 mA
TA = +125 oC
* ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 10. Operating Circuit for Burn-In and Steady State Life Tests.
10
MIL-PRF-38534 Class H, Class K, and
DLA SMD Test Program
Avago’s Hi-Rel Optocouplers are in compliance with MILPRF-38534 Classes H and K. Class H and Class K devices
are also in compliance with DLA drawing 5962-08242.
Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534.
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies Limited. All rights reserved.
AV02-1327EN - October 2, 2012