ADS7863
AD
S7
863
AD
S
786
3
SBAS383 – JUNE 2007
Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
•
•
•
Four Fully- or Six Pseudo-Differential Inputs
SINAD: 70dB (min), THD: –75dB (max)
Programmable and Buffered Internal 2.5V
Reference
Flexible Power-Down Features
Variable Power Supply Ranges
Low Power Operation: 40mW at 5V
Operating Temperature Range: –40°C to
+125°C
Pin-Compatible with ADS7861 and ADS8361
(SSOP package)
The ADS7863 is a dual, 12-bit, 1.5MSPS,
analog-to-digital converter (ADC) with four fully
differential input channels grouped into two pairs for
high-speed, simultaneous signal acquisition. Inputs
to the sample-and-hold (S/H) amplifiers are fully
differential and are maintained differential to the input
of the ADC. This architecture provides excellent
common-mode rejection of 80dB at 50kHz, which is
a critical performance characteristic in noisy
environments.
The ADS7863 is pin-compatible with the ADS8361,
but offers additional features such as a
programmable reference output, flexible supply
voltage (2.7V to 5.5V for AVDD and 1.65V to 5.5V for
BVDD), a pseudo-differential input multiplexer with
three channels per ADC, and several power-down
features.
APPLICATIONS
•
•
•
Motor Control
Multi-Axis Positioning Systems
Three-Phase Power Control
The high-speed, dual serial interface is also
pin-compatible with the ADS7861 while offering
additional flexibility. The ADS7863 is offered in an
SSOP-24 and a 4x4mm QFN-24 package. It is
specified over the extended operating temperature
range of –40°C to +125°C.
SAR
BVDD
AVDD
SDOA
CHA0+
CHA1+
SDOB
Input
MUX
S/H
M0
CDAC
CHA1-
Comparator
CHB0+
CHB0CHB1+
Input
MUX
S/H
CDAC
CHB1-
Serial Interface
CHA0-
M1
SDI
CLOCK
CS
RD
Comparator
BUSY
CONVST
REFIN
SAR
REFOUT
10-Bit DAC
BGND
2.5V Reference
AGND
Functional Block Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007, Texas Instruments Incorporated
PRODUCT PREVIEW
•
•
•
DESCRIPTION
ADS7863
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SBAS383 – JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SSOP-24
DBQ
4x4 QFN-24
RGE
ORDERING NUMBER
ADS7863I
(1)
TRANSPORT MEDIA,
QUANTITY
ADS7863IDBQ
Tube, 56
ADS7863IDBQR
Tape and Reel, 2500
ADS7863IRGE
Tape and Reel, 250
ADS7863IRGER
Tape and Reel, 3000
For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI
web site at www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
PRODUCT PREVIEW
ADS7863
UNIT
Supply voltage, AVDD to AGND
–0.3 to +6
V
Supply voltage, BVDD to BGND
–0.3 to +6
V
1.5 × AVDD
V
Analog and reference input voltage with respect to AGND
AGND – 0.3 to AVDD + 0.3
V
Digital input voltage with respect to BGND
BGND – 0.3 to BVDD + 0.3
V
Supply voltage, BVDD to AVDD
Ground voltage difference |AGND – BGND|
+0.3
V
Input current to any pin except supply pins
–10 to +10
mA
Operating virtual junction temperature range, TJ
–40 to +150
°C
Storage temperature range, TSTG
–65 to +150
°C
+250
°C
Lead temperature 1.6mm (1/16in) from case for 10s
(1)
2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
ADS7863
PARAMETER
Supply voltage, AVDD to AGND
Low voltage levels
Supply voltage, BVDD to BGND
MIN
NOM
MAX
2.7
5.0
5.5
1.65
5V logic levels
Reference input voltage on REFIN
Analog differential input voltage (CHxx+) – (CHxx–)
Operating ambient temperature range, TA
UNIT
V
3.6
V
4.5
5.0
5.5
0.5
2.5
2.525
V
–VREF
+VREF
mV
–40
+125
°C
DISSIPATION RATINGS
PACKAGE
DERATING FACTOR ABOVE
TA = +25°C
TA ≤ +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
TA = +125°C
POWER RATING
SSOP-24
10mW/°C
1250mW
800mW
650mW
250mW
QFN-24
(4mm x 4mm)
22mW/°C
2740mW
1750mW
1420mW
540mW
PRODUCT PREVIEW
THERMAL CHARACTERISTICS (1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
θJA
Junction-to-air thermal resistance
θJC
Junction-to-case thermal resistance
PDISS
Device power dissipation at 5V
(1)
SSOP-24
QFN-24
UNIT
Low-K thermal resistance
99.8
45.6
High-K thermal resistance
61.0
33.1
23.3
35
°C/W
40
40
mW
°C/W
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.
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SBAS383 – JUNE 2007
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +125°C, and AVDD = 5V, BVDD = 3.3V, VREF = 2.5V (internal), fCLK = 24MHz, and fSAMPLE = 1.5MSPS, unless
otherwise noted.
ADS7863
PARAMETER
TEST CONDITIONS
RESOLUTION
MIN
TYP (1)
MAX
12
UNIT
Bits
ANALOG INPUT
FSR
Full-scale differential input range
VIN
Absolute input voltage
CHxx+ or CHxx+ to AGND
(CHxx+) – (CHxx–)
CIN
Input capacitance
CHxx+ or CHxx– to AGND
CID
Differential input capacitance
IIL
Input leakage current
CMRR
Common-mode rejection ratio
–VREF
+VREF
–0.1
AVDD + 0.1
2
V
pF
4
–1
V
pF
+1
80
nA
dB
DC ACCURACY
INL
Integral nonlinearity
–1
+1
Differential nonlinearity (2)
–1
+1
Input offset error
–1
+1
INL match
DNL
LSB
DNL match
VOS
LSB
LSB
LSB
PRODUCT PREVIEW
VOS match
Asynchronous to Synchronous
dVOS/dT
Input offset thermal drift
GERR
Gain error (2)
LSB
LSB
μV/°C
0.25
GERR match
%
%
GERR/dT
Gain error thermal drift
PSRR
Power-supply rejection ratio
ppm/°C
2.7V < AVDD < 5.5V
70
dB
AC ACCURACY
SINAD
Signal-to-noise + distortion
VIN = 5VPP at 100kHz
70
SNR
Signal-to-noise ratio
VIN = 5VPP at 100kHz
THD
Total harmonic distortion
VIN = 5VPP at 100kHz
SFDR
Spurious-free dynamic range
VIN = 5VPP at 100kHz
75
1MHz < fCLK ≤ 24MHz
0.542
dB
dB
–75
dB
dB
SAMPLING DYNAMICS
tCONV
Conversion time per ADC
tACQ
Acquisition time
tDATA
Throughput rate
tA
Aperture delay
13
125
1MHz < fCLK ≤ 24MHz
ns
62.5
1500
6
tA match
50
tAJIT
Aperture jitter
fCLK
Clock frequency on CLOCK
μs
ns
ps
50
1
kSPS
ps
24
MHz
INTERNAL VOLTAGE REFERENCE
Resolution
VREFOUT
Reference output voltage
dVREFOUT/dT
Reference voltage drift
DNLDAC
DAC differential nonlinearity
INLDAC
DAC integral nonlinearity
VOSDAC
(1)
(2)
4
Reference output DAC resolution
DAC offset error
10
Over 20%...100% DAC range
0.496
DAC = 0x3FF,
–40°C < TA < +125°C
2.480
DAC = 0x3FF at +25°C
2.485
Bits
2.520
V
2.500
2.520
V
2.500
2.515
±10
–9.76
9.76
mV
–4
4
LSB
–9.76
9.76
mV
4
LSB
–4
VREFOUT = 0.5V
All typical values at TA = +25°C.
Ensured by design, not production tested.
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V
ppm/°C
9.76
mV
4
LSB
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SBAS383 – JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +125°C, and AVDD = 5V, BVDD = 3.3V, VREF = 2.5V (internal), fCLK = 24MHz, and fSAMPLE = 1.5MSPS, unless
otherwise noted.
ADS7863
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
INTERNAL VOLTAGE REFERENCE, continued
PSRR
Power-supply rejection ratio
IREFOUT
Reference output dc current
IREFSC
Reference output short-circuit current
tREFON
Reference output settling time
dB
1
mA
mA
100
μs
VOLTAGE REFERENCE INPUT
VREF
Reference input voltage range
IREF
Reference input current
0.5
2.5
50
2.525
μA
V
CREF
Reference input capacitance
10
pF
DIGITAL INPUTS
CMOS
VIH
High-level input voltage
0.7 × BVDD
BVDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 × BVDD
V
IIN
Input current
–50
+50
nA
CIN
Input capacitance
VIN = BVDD to BGND
5
V
PRODUCT PREVIEW
Logic family
pF
DIGITAL OUTPUTS
Logic family
CMOS
VOH
High-level output voltage
IOH = –100μA
VOL
Low-level output voltage
IOH = 100μA
IOZ
High-impedance-state output current
COUT
Output capacitance
CLOAD
Load capacitance
VIN = BVDD to BGND
BVDD – 0.2
V
–50
0.2
V
+50
nA
5
pF
30
pF
POWER SUPPLY
AVDD
Analog supply voltage
AVDD to AGND
2.7
5.0
5.5
V
BVDD
Buffer I/O supply voltage
BVDD to BGND
1.65
3.3
5.5
V
AVDD = 3V
6
7
AVDD = 5.5V
7
8
AIDD
Analog supply current
AVDD = 3V, NAP power-down
μA
AVDD = 5.5V, NAP power-down
AVDD = 3V, deep power-down
AVDD = 5.5V, deep power-down
BIDD
PDISS
μA
Buffer I/O supply current
Power dissipation
AVDD = 3V
AVDD = 5.5V
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18.9
40
μW
5
ADS7863
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SBAS383 – JUNE 2007
DEVICE INFORMATION
ADS7863IDBQ
SSOP-24 (DBQ)
(TOP VIEW)
19
CS
CHA1-
7
18
RD
PRODUCT PREVIEW
CHA0+
8
17
CONVST
CHA0-
9
16
SDI
REFIN
10
15
M0
REFOUT
11
14
M1
AGND
12
13
AVDD
CHB0-
CHB0+
CHB1-
21
20
19
16
BVDD
15
SDOA
REFOUT
3
AGND
4
AVDD
5
14
SDOB
M1
6
13
BUSY
ADS7863
12
6
BGND
CLOCK
CHA1+
CHB1+
17
11
CLOCK
18
2
10
20
1
REFIN
CS
5
CHA0-
RD
CHB0-
CHA1+
BUSY
CHA1-
CHB0+
23
SDOB
21
22
22
4
9
3
SDI
CHB1-
CONVST
SDOA
CHA0+
BVDD
23
8
24
2
7
1
M0
BGND
CHB1+
24
ADS7863IRG
4 x 4 QFN-24 (RGE)
(TOP VIEW)
PIN DESCRIPTIONS
PIN NUMBER
6
SSOP
QFN
NAME
DESCRIPTION
1
17
BGND
Buffer I/O ground. Connect to digital ground plane.
2
18
CHB1+
Noninverting analog input channel B1
3
19
CHB1–
Inverting analog input channel B1
4
20
CHB0+
Noninverting analog input channel B0
5
21
CHB0–
Inverting analog input channel B0
6
22
CHA1+
Noninverting analog input channel A1
7
23
CHA1–
Inverting analog input channel A1
8
24
CHA0+
Noninverting analog input channel A0
9
1
CHA0–
Inverting analog input channel A0
10
2
REFIN
Reference voltage input. A ceramic capacitor of 470nF (min) is required at this terminal.
11
3
REFOUT
12
4
AGND
Analog ground. Connect to analog ground plane.
13
5
AVDD
Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1μF ceramic capacitor.
14
6
M1
Mode pin 1. Selects between the SDOx digital outputs (see Table 7).
15
7
M0
Mode pin 0. Selects between analog input channels (see Table 7).
16
8
SDI
Serial data input. This pin allows the additional features of the ADS7863 to be used but can also be used
in ADS7861-compatible manner.
17
9
CONVST
Conversion start. The ADC switches from the sample into the hold mode on the rising edge of CONVST,
independent of the status of CLOCK.
18
10
RD
Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low.
19
11
CS
Chip select. When low, the SDOx outputs are active; when high, the SDOx outputs are tri-stated.
20
12
CLOCK
21
13
BUSY
ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the
conversion has been finished.
22
14
SDOB
Serial data output for converter B. Data are valid on the falling edge of CLOCK.
23
15
SDOA
Serial data output for converter A. When M1 is high, both SDOA and SDOB are active. Data are valid on
the falling edge of CLOCK.
24
16
BVDD
Buffer I/O supply, 1.65V to 5.5V. Decouple to BGND with a 1μF ceramic capacitor.
Reference voltage output. The programmable internal voltage reference output is available on this pin.
External clock input
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SBAS383 – JUNE 2007
Equivalent Input Circuit
RSER = 200W
RSW = 50W
CHXX+
CPAR = 5pF
CS = 2pF
CPAR = 5pF
CS = 2pF
CHXXRSER = 200W
RSW = 50W
TIMING CHARACTERISTICS
Conversion 1
Conversion 2
tCKH
CLOCK
0
1
2
3
4
5
6
7
8
tCKL
9
10
11
12
13
14
15
t1
16
1
2
3
C1
C0
P1
4
t6
t11
t12
tCONV
BUSY
t4
PRODUCT PREVIEW
CONVST
tACQ
t5
t7
RD
t3
C1
C0
P1
P0
SERIAL
DATA A
0
0
D11
D10
SERIAL
DATA B
0
0
D11
D10
SDI
DP
t2
A1
A0
D4
D3
D2
D1
D0
0
0
0
0
D11
D4
D3
D2
D1
D0
0
0
0
0
D11
N
AN
RP
S4
A2
D9
D8
D7
D6
D5
D9
D8
D7
D6
D5
t13
CS
t8
t9
t10
Figure 1. Detailed Timing Diagram (Mode I)
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TIMING CHARACTERISTICS (continued)
CLOCK
Cycle 1
Cycle 2
12ns
12ns
TBD
CONVST
A
TBD
B
C
NOTE: All CONVST commands that occur more than 12ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur TBDns after the
rising edge of cycle ‘1’ or 12ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge
of cycle ‘2’. All CONVST commands that occur TBDns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a
conversion on the rising edge of the next clock period.
The CONVST pin should never be switched from LOW to HIGH in the region 12ns prior to the rising edge of the
CLOCK and TBDns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could
begin on either the same rising edge of the CLOCK or the following edge.
Figure 2. CONVST Timing
TIMING REQUIREMENTS (1)
PRODUCT PREVIEW
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5V, unless
otherwise noted.
ADS7863
SYMBOL
(1)
8
PARAMETER
COMMENTS
MIN
tCONV
Conversion time
fCLOCK = 24MHz
541.67
tACQ
125
MAX
UNIT
ns
Acquisition time
fCLOCK = 24MHz
fCLOCK
CLOCK frequency
See Figure 1
1
24
ns
TCLOCK
CLOCK period
See Figure 1
41.67
1000
tCKL
CLOCK low time
See Figure 1
5
ns
tCKH
CLOCK high time
See Figure 1
5
ns
t1
CONVST high time
See Figure 1
15
ns
t2
SDI setup time to CLOCK falling edge
See Figure 1
10
ns
t3
SDI hold time to CLOCK falling edge
See Figure 1
5
ns
t4
RD high setup time to CLOCK falling edge
See Figure 1
10
ns
t5
RD high hold time to CLOCK falling edge
See Figure 1
5
ns
t6
CONVST low time
See Figure 1
15
ns
t7
RD low time relative to CLOCK falling edge
See Figure 1
15
ns
t8
CS low to SDOx valid
See Figure 1
20
ns
t9
SDOx data setup time to CLOCK falling
edge
See Figure 1
t10
SDOx data hold time to CLOCK falling edge
See Figure 1
5
ns
t11
CONVST setup time to rising edge of
CLOCK
See Figure 1
12
ns
t12
CLOCK rising edge to BUSY low delay
See Figure 1
3
ns
t13
CS low to RD high delay
See Figure 1
10
ns
25
All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
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ns
ns
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SBAS383 – JUNE 2007
TYPICAL CHARACTERISTICS
NEED TITLE vs
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Figure 3.
Figure 4.
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NEED TITLE vs
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Figure 5.
Figure 6.
NEED TITLE vs
NEED TITLE
NEED TITLE vs
NEED TITLE
Figure 7.
Figure 8.
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PRODUCT PREVIEW
At TA = +25°C, +VA + VD = +5V, and VREF = 2.5V (internal), fCLK = 8MHz, and fSAMPLE = 2MHz, unless otherwise noted.
9
ADS7863
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SBAS383 – JUNE 2007
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VA + VD = +5V, and VREF = 2.5V (internal), fCLK = 8MHz, and fSAMPLE = 2MHz, unless otherwise noted.
PRODUCT PREVIEW
10
NEED TITLE vs
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NEED TITLE vs
NEED TITLE
Figure 9.
Figure 10.
NEED TITLE vs
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NEED TITLE vs
NEED TITLE
Figure 11.
Figure 12.
NEED TITLE vs
NEED TITLE
NEED TITLE vs
NEED TITLE
Figure 13.
Figure 14.
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SBAS383 – JUNE 2007
APPLICATIONS INFORMATION
GENERAL DESCRIPTION
CHx1+
Each ADC has a fully differential, 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage
(for example, 2.5V). In this type of application, the
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common pin and
the remaining three inputs (CHx0+, CHx1–, and
CHx1+) operate as separate inputs referred to the
common pin.
The ADS7863 also includes a 2.5V internal
reference.
The
reference
drives
a
10-bit
digital-to-analog converter (DAC), allowing the
voltage at the REFOUT pin to be adjusted via the
serial interface in 2.44mV steps. A low-noise
operational amplifier with unity gain buffers the DAC
output voltage and drives the REFOUT pin.
The ADS7863 offers a serial interface that is
compatible with the ADS7861. However, instead of
the A0 pin of the ADS7861 that controls the channel
selection, the ADS7863 offers a serial data input
(SDI) pin that supports additional functions described
in the Digital section of this data sheet.
ANALOG
This section addresses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
Each ADC is fed by an input multiplexer; see
Figure 15. Each multiplexer is either used in a
fully-differential 2:1 configuration (as described in
Table 1) or a pseudo-differential 3:1 configuration (as
shown in Table 2). The channel selection is
performed using bits C1 and C0 in the SDI Register
(see also the Serial Data Input section).
The input path for the converter is fully differential
and provides a common-mode rejection of 80dB at
50kHz. The high CMRR also helps suppress noise in
harsh industrial environments.
CHx1-
Input
MUX
CHx0+
ADC+
ADC-
CHx0-
Figure 15. Input Multiplexer Configuration
Table 1. Fully Differential 2:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
1
1
CHx1+
CHx1–
Table 2. Pseudo-Differential 3:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
0
1
CHx1–
CHx0–
1
1
CHx1+
CHx0–
Each of the of 2pF sample-and-hold capacitors
(shown as CS in the Equivalent Input Circuit) is
connected via switches to the multiplexer output.
Opening the switches holds the sampled data during
the conversion process. After finishing the
conversion, both capacitors are pre-charged for the
duration of one clock cycle to the voltage present at
the REFIN pin. After the pre-charging, the multiplexer
outputs are connected to the sampling capacitors
again. The voltage at the analog input pin is usually
different from the reference voltage; therefore, the
sample capacitors must be charged to within
one-half LSB for 12-bit accuracy during the
acquisition
time
tACQ
(see
the
Timing
Characteristics).
Acquisition time is indicated with the BUSY signal
being held low. It starts by closing the input switches
(after finishing the previous conversion and
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7863 operates at full
speed, the acquisition time is typically 125ns.
The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
Equation 1, with n = 12 being the resolution of the
ADS7863:
ln(2) ´ (n + 1)
f-3dB =
2p ´ tACQ
(1)
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11
PRODUCT PREVIEW
The ADS7863 includes two 12-bit analog-to-digital
converters (ADCs) that operate based on the
successive-approximation register (SAR) principle.
The ADCs sample and convert simultaneously.
Conversion time can be as low as 541.67ns. Adding
the acquisition time of 125ns results in a maximum
conversion rate of 1.5MSPS.
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With tACQ = 125ns, the minimum bandwidth of the
driving amplifier is 11.5MHz. The required bandwidth
can be lower if the application allows a longer
acquisition time.
A gain error occurs if a given application does not
fulfill the settling requirement shown in Equation 1.
As a result of precharging the capacitors, linearity
and THD are not directly affected.
The
OPA365
from
Texas
Instruments
is
recommended; in addition to offering the required
bandwidth, it provides a low offset and also offers
excellent THD performance.
The phase margin of the driving operational amplifier
is usually reduced by the ADC sampling capacitor. A
resistor placed between the capacitor and the
amplifier limits this effect; therefore, an internal 200Ω
resistor (RSER) is placed in series with the switch.
The switch resistance (RSW) is typically 50Ω (see
Equivalent Input Circuit).
PRODUCT PREVIEW
The differential input voltage range of the ADC is
±VREF, the voltage at the REFIN pin.
It is important to keep the voltage to all inputs within
the 0.3V limit below AGND and above AVDD while
not allowing dc current to flow through the inputs.
Current is only necessary to recharge the
sample-and-hold capacitors.
CLOCK
The ADC uses an external clock in the range of
1MHz to 24MHz. 12 clock cycles are needed for a
complete conversion; one additional clock cycle is
used for pre-charging the sample capacitors. With a
minimum of 16 clocks required per conversion, three
clock cycles are used for sampling.
The CLOCK duty cycle should be 50%. However, the
ADS7863 functions properly with a duty cycle
between 30% and 70%.
RESET
The ADS7863 features an internal power-on reset
(POR) function. However, an external reset can also
be issued using SDI Register bits A[2:0] (see the
Digital section).
REFIN
The reference input is not buffered and is directly
connected to the ADC. The converter generates
spikes on the reference input voltage because of
internal switching. Therefore, an external capacitor to
the analog ground (AGND) should be used to
stabilize the reference input voltage. This capacitor
should be at least 470nF. Ceramic capacitors (X5R
type) with values up to 1μF are commonly available
as SMD in 0402 size.
Analog-to-Digital Converter (ADC)
REFOUT
The ADS7863 includes two SAR-type, 1.5MSPS,
12-bit ADCs (shown in the Functional Block Diagram
on the front page of this data sheet).
The ADS7863 includes a low-drift, 2.5V internal
reference source. This source feeds a 10-bit string
DAC that is controlled via the serial interface. As a
result of this architecture, the voltage at the REFOUT
pin is programmable in 2.44mV steps and can be
adjusted to specific application requirements without
the use of additional external components.
CONVST
The analog inputs are held with the rising edge of the
CONVST (conversion start) signal. The setup time of
CONVST referred to the next rising edge of CLOCK
(system clock) is 12ns (minimum). The conversion
automatically starts with the rising CLOCK edge.
CONVST should not be issued during a conversion,
that is, when BUSY is high.
RD (read data) and CONVST can be shorted to
minimize necessary software and wiring. The RD
signal is triggered by the ADS7863 on the falling
edge of CLOCK. Therefore, the combined signals
must be activated with the rising CLOCK edge. The
conversion then starts with the subsequent rising
CLOCK edge.
12
However, the DAC output voltage should not be
programmed below 0.5V to ensure the correct
functionality of the reference output buffer. This
buffer is connected between the DAC and the
REFOUT pin, and is capable of driving the capacitor
at the REFIN pin. A minimum of 470nF is required to
keep the reference stable (see the previous
discussion of REFIN above). For applications that use
an external reference source, the internal reference
can be disabled using bit RP in the SDI Register
(see the Digital section). The settling time of the
REFOUT pin is 100μs. The default value of the
REFOUT pin after power-up is 2.5V.
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As a result of this poor performance, the ADS7863
buffer has a fixed transition at DAC code 496
(0x1F0). At this code, the DAC may show a jump of
up to 10mV in its transfer function.
AN: AutoNap power-down enable ('1' = device in
AutoNap power-down mode)
RP: Reference power-down ('1' = reference
turned off)
S4: Special read mode for Modes II and IV
('1' = special mode enabled)
Table 6. A2, A1, and A0: DAC Control and Device
Reset
A2
A1
A0
0
0
0
No action
0
0
1
DAC write with next access
0
1
0
No action
0
1
1
DAC read with next access
1
0
0
No action
1
0
1
Device reset
Serial Data Input (SDI)
1
1
0
No action
The serial data input or SDI pin (corresponding to pin
A0 on the ADS7861) is coupled to RD and clocked
into the ADS7863 on each falling edge of CLOCK.
The data word length of the SDI Register is 12 bits.
Table 3 shows the register structure. The data must
be transferred MSB-first. Table 4 through Table 6
describe specific bits of this register. The default
value of this register after power-up is 0x000.
1
1
1
No action
DIGITAL
This section addresses the timing and control of the
ADS7863 serial interface.
Table 3. SDI Register Contents
SDI REGISTER BIT
11
10
9
8
7
6
5
4
3
2
1
0
C1
C0
P1
P0
DP
N
AN
RP
S4
A2
A1
A0
Table 4. C1 and C0: Channel Selection
ADC A/B
C1
C0
POSITIVE INPUT
NEGATIVE INPUT
0
0
CHA0+ / CHB0+
CHA0– / CHB0–
0
1
CHA1– / CHB1–
CHA0– / CHB0–
1
0
CHA1+ / CHB1+
CHA0– / CHB0–
1
1
CHA1+ / CHB1+
CHA1– / CHB1–
Table 5. P1 and P0: Additional Features Enable
P1
P0
0
0
Convert both CHx0 channels
FUNCTION
0
1
Activate additional features
1
0
Reserved for factory test (do not
use)
1
1
Convert both CHx1 channels
DP: Deep power-down enable ('1' = device in
deep power-down mode)
N: Nap power-down enable ('1' = device in Nap
power-down mode)
FUNCTION
All additional features become active with the rising
edge of the 12th CLOCK signal after issuing the RD
pulse.
Timing and Control
IMPORTANT:
Consider the Detailed Timing Diagram (Figure 1)
and CONVST timing diagram (Figure 2) shown in
the Timing Characteristics section. For maximum
data throughput, the descriptions and diagrams
given in this data sheet assume that the
CONVST and RD pins are tied together. Note
that they can also be controlled independently.
The operation of the ADS7863 can be configured in
four different modes by using the mode pins M0 and
M1, as shown in Table 7.
Pin M0 sets either manual or automatic channel
selection. In manual mode, the SDI pin is used to
select between channels CHx0 and CHx1; in
automatic operation, the SDI pin is ignored and
channel selection is controlled by the device after
each conversion. Pin M1 selects between serial data
being transmitted simultaneously on both outputs
SDOA and SDOB for each channel respectively, or
using only the SDOA output for transmitting data
from both channels (see Figure 16 through Figure 23
and the associated text for more information).
Table 7. M1/M0 Truth Table
CHANNEL
SELECTION
M0
M1
0
0
Manual (via SDI)
SDOA and SDOB
0
1
Manual (via SDI)
SDOA only
1
0
Automatic
SDOA and SDOB
1
1
Automatic
SDOA only
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SDOx USED
13
PRODUCT PREVIEW
For operation with a 2.7V analog supply and a 2.5V
reference, the internal reference buffer requires a
rail-to-rail input and output. Such buffers typically
contain two input stages; when the input voltage
passes the mid-range area, a transition occurs at the
output because of switching between the two input
stages. In this voltage range, rail-to-rail amplifiers
generally show a very poor power-supply rejection.
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Additionally, the SDI pin is used for controlling device
functionality; see the Serial Data Input section for
details.
Converted data on the SDOx pins becomes valid
with the third falling CLOCK edge after generating an
RD pulse. The following sections explain the four
different modes of operation in detail.
MODE I
With the M0 and M1 pins both set to '0', the
ADS7863 enters manual channel control operation.
The SDI pin is used to switch between the channels.
A conversion is initiated by bringing CONVST high.
1
16 clock cycles are required to perform a single
conversion. With the rising edge of CONVST, the
ADS7863 switches asynchronously to the external
CLOCK from sample to hold mode.
After some delay (t12), the BUSY output pin goes
high and remains high for the duration of the
conversion cycle. On the falling edge of the second
CLOCK cycle, the ADS7863 latches in the channel
for the next conversion cycle, depending on the
status of the SDI pin. CS must be brought low to
enable both serial outputs. Data are valid on the
falling edge of every 16 clock cycles per conversion.
The first two bits are set to '0'. The subsequent data
contain the 12-bit conversion result (the most
significant bit is transferred first), followed by two '0's
(see Figure 1 and Figure 16).
16 1
16
CLOCK
PRODUCT PREVIEW
CONVST
SDI
C[1:0] = '11' ® Convert CHx1 Next
P[1:0] = '11' ® SDI Features Not Used
C[1:0] = '00' ® Convert CHx0 Next
P[1:0] = '00' ® SDI Features Not Used
C[1:0] = '00' ® Convert CHx0 Next
P[1:0] = '00' ® SDI Features Not Used
M0
M1
RD
CS
High-Z
SDOA
0 0
Previous 12-Bit Data CHAx
0 0 0 0
12-Bit Data CHA1
0 0
SDOB
0 0
Previous 12-Bit Data CHBx
0 0 0 0
12-Bit Data CHB1
0 0
High-Z
BUSY
Previous Conversion of Both CHxx
0ms
Conversion of Both CHx1
0.5ms
Conversion of Both CHx0
1.0ms
Figure 16. Mode I Timing Diagram (M0 = 0; M1 = 0)
14
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MODE II
With M0 = 0 and M1 set to '1', the ADS7863 also
operates in manual channel control mode and
outputs data on the SDOA pin only while SDOB is
set to tri-state. All other pins function in the same
manner as they do in Mode I. Because it takes 32
clock cycles to output the results from both ADCs
16
1
1
16
1
(instead of 16 cycles, if M1 = 0), the ADS7863
requires 1μs to perform a complete conversion/read
cycle. If the CONVST signal is issued every 0.5μs
(which is required for the RD signal) as in Mode I,
every second pulse is ignored; see Figure 17.
The output data consist of a '0' followed by an ADC
indicator ('0' for CHAx or '1' for CHBx), 12 bits of
conversion results, and another '00'.
16
1
16
1
16
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
C[1:0] = '00' ® CHx0 Next
P[1:0] = '00' ® No Features
C[1:0] = '11' ® CHx1 Next
P[1:0] = '11' ® No Features
SDI Ignored
C[1:0] = '00' ® CHx0 Next
P[1:0] = '00' ® No Features
SDI Ignored
C[1:0] = '11' ® CHx1 Next
P[1:0] = '11' ® No Features
12-Bit
Data CHB1
A
PRODUCT PREVIEW
SDI
M0
M1
RD
CS
CHx
B
Previous 12-Bit
Data CHAx
SDOA
A
B
12-Bit
Data CHB0
12-Bit
Data CHA0
A
12-Bit
Data CHA1
12-Bit
Data CHA0
CHx
BUSY
High-Z
Previous 12-Bit
Data
DataCHBx
CHBx
SDOB
Previous Conversion
of Both CHxx
0ms
No Conversion,
Read Access Only
Conversion
of Both CHx0
0.5ms
1.0ms
No Conversion,
Read Access Only
Conversion
of Both CHx1
1.5ms
2.0ms
Conversion
of Both CHx0
2.5ms
3.0ms
Figure 17. Mode II Timing Diagram (M0 = 0; M1 = 1)
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MODE III
With M0 set to '1' and M1 = 0, the ADS7863
automatically cycles between the multiplexer inputs
(ignoring the SDI pin) while offering the conversion
result of CHAx on SDOA and the conversion result of
CHBx on SDOB (see Figure 18).
1
Output data consist of a channel indicator ('0' for
CHx0 or '1' for CHx1), followed by a '0', 12 bits of
conversion results, and another '00'.
16 1
16
CLOCK
CONVST
SDI
C[1:0] is ignored
P[1:0] = ‘00’ ® SDI features are not used
M0
C[1:0] is ignored
P[1:0] = ‘11’ ® SDI features are not used
C[1:0] is ignored
P[1:0] = ‘11’ ® SDI features are not used
Both channel 0s are converted first,
followed by conversion of both channel 1s.
PRODUCT PREVIEW
M1
RD
CS
CH1
Previous 12-Bit Data CHAx
SDOA
CH0
12-Bit Data CHA1
12-Bit Data CHA0
CH1
Previous 12-Bit Data CHBx
SDOB
BUSY
CH0
Previous Conversion of Both CHxx
0ms
Previous 12-Bit Data CHB1
Previous 12-Bit Data CHB0
Conversion of Both CHx0
0.5ms
Conversion of Both CHx1
1.0ms
Figure 18. Mode III Timing Diagram (M0 = 1; M1 = 0)
16
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MODE IV
In the same way as Mode II, Mode IV uses the
SDOA output line exclusively to transmit data while
the multiplexer channels are switched automatically.
Following the first conversion after M1 goes high, the
SDOB output tri-states (see Figure 19).
16
1
1
Output data consist of a channel indicator ('0' for
CHx0 or '1' for CHx1), followed by the ADC indicator
('0' for CHAx or '1' for CHBx), 12 bits of conversion
results, and ends with '00'.
16
1
16
1
16
16
1
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
C[1:0] is Ignored
P[1:0] = '00'
Every 2nd
CONVST
Is Ignored
C[1:0] is Ignored
P[1:0] = '11'
Every 2nd
CONVST
Is Ignored
SDI Ignored
SDI Ignored
SDI
M0
Both channel 0s are converted first,
followed by conversion of both channel 1s.
PRODUCT PREVIEW
M1
RD
CS
CHx
0A
Previous 12-Bit
Data CHAx
SDOA
0B
1A
12-Bit
Data CHB0
12-Bit
Data CHA0
1B
12-Bit
Data CHA1
0A
12-Bit
Data CHA0
12-Bit
Data CHB1
CHx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0m s
High-Z
Conversion
of Both CHx0
0.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0ms
1.5ms
Conversion
of Both CHx0
No Conversion,
Read Access Only
2.0ms
2.5ms
3.0ms
Figure 19. Mode IV Timing Diagram (M0 = 1 ; M1 = 1)
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SPECIAL MODE II (Not ADS7861-Compatible)
For Mode II, a special read mode is available in the
ADS7863 where both data results can be read out,
triggered by a single RD pulse. To activate this
mode, bit S4 in the SDI Register must be set to '1'
(see also the Serial Data Input section).
16
1
1
16
1
The CONVST and RD pins can still be tied together,
but do not need to be issued every 16 CLOCK
cycles. Output data are presented on both terminals,
SDOA and SDOB.
The special read mode is not available in Mode I or
Mode III. Figure 20 illustrates the special read mode.
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] = '00' ® CHx0
P[1:0] = '01' ® Features ON
P[1:0] = '01' ® S4 = '1'
C[1:0] = '11' ® CHx1
P[1:0] = '11' ® No Updates
P[1:0] = '11' ® S4 Still = '1'
C[1:0] = '11' ® CHx1
P[1:0] = '11' ® No Updates
P[1:0] = '11' ® S4 Still = '1'
C[1:0] = '11' ® CHx1
P[1:0] = '11' ® No Updates
P[1:0] = '11' ® S4 Still = '1'
M0
PRODUCT PREVIEW
M1
RD
CS
B
B
SDOA
Previous 12-Bit
Data CHAx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0ms
A
12-Bit
Data CHB0
12-Bit
Data CHA0
A
12-Bit
Data CHA1
12-Bit
Data CHB1
A
High-Z
Conversion
of Both CHx0
0.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0ms
1.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
2.0ms
2.5ms
Figure 20. Special Mode II Timing Diagram (M0 = 0; M1 = 1; S4 = 1)
18
12-Bit
Data CHA1
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3.0ms
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SPECIAL MODE IV (Not ADS7861-Compatible)
Analogous to Special Mode II, the ADS7863 also
offers a special read mode for Mode IV in which both
data results of a conversion can be read, triggered
by a single RD pulse. In this case as well, bit S4 in
the SDI Register must be set to '1' while the
CONVST and RD pins can still be tied together .
16
1
1
16
1
As with Special Mode II, these two pins do not need
to be issued every 16 CLOCK cycles. Data are
available on the SDOA pin.
This special read mode (shown in Figure 21) is not
available in Mode I or Mode III.
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] is Ignored
P[1:0] = '01' ® Features ON
P[1:0] = '01' ® S4 = '1'
C[1:0] is Ignored
P[1:0] = '11' ® No Updates
P[1:0] = '11' ® S4 Still = '1'
C[1:0] is Ignored
P[1:0] = '11' ® No Updates
P[1:0] = '11' ® S4 Still = '1'
C[1:0] is Ignored
P[1:0] = '11' ® No Updates
P[1:0] = '11' ® S4 Still = '1'
M1
PRODUCT PREVIEW
M0
Both channel 0s are converted first,
followed by conversion of both channel 1s.
RD
CS
CHX
0A
Previous 12-Bit
Data CHAx
SDOA
0B
1A
12-Bit
Data CHB0
12-Bit
Data CHA0
1B
12-Bit
Data CHA1
0A
12-Bit
Data CHA0
12-Bit
Data CHB1
CHX
BUSY
High-Z
Previous 12-Bit
Data CHBx
SDOB
Conversion
of Both CHx0
Previous Conversion
of Both CHxx
0ms
0.5ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0ms
1.5ms
Conversion
of Both CHx0
No Conversion,
Read Access Only
2.0ms
2.5ms
3.0ms
Figure 21. Special Mode IV Timing Diagram (M0 = 1; M1 = 1; S4 = 1)
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PSEUDO-DIFFERENTIAL MODE I
(Not ADS7861-Compatible)
In Mode I, the ADS7863 input multiplexers can also
operate in a pseudo-differential manner. In this case,
SDI bits C[1:0] are used to choose the channels
accordingly.
16
1
1
16
1
For more details, see the Serial Data Input section.
Data are available on both output terminals, SDOA
and SDOB.
The input multiplexer cannot be used for
pseudo-differential signals in Mode III or Mode IV.
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] = '00' ® CHx0+/CHx0P[1:0] = '00' ® Features OFF
C[1:0] = '01' ® CHx1-/CHx0P[1:0] = '11' ® Features OFF
C[1:0] = '10' ® CHx1+/CHx0P[1:0] = '00' ® Features OFF
C[1:0] = '00' ® CHx0+/CHx0P[1:0] = '00' ® Features OFF
C[1:0] = '01' ® CHx1-/CHx0P[1:0] = '11' ® Features OFF
C[1:0] = '10' ® CHx1+/CHx0P[1:0] = '00' ® Features OFF
SDOA
Previous 12-Bit
Data CHAx
12-Bit Data
CHA0+/CHA0-
12-Bit Data
CHA1-/CHA0-
12-Bit Data
CHA1+/CHA0+
12-Bit Data
CHA0+/CHA0-
12-Bit Data
CHA1-/CHA0-
SDOB
Previous 12-Bit
Data CHBx
12-Bit Data
CHB0+/CHB0-
12-Bit Data
CHB1-/CHB0-
12-Bit Data
CHB1+/CHB0+
12-Bit Data
CHB0+/CHB0-
12-Bit Data
CHB1-/CHB0-
BUSY
Previous Conversion
of Both CHxx
Conversion of Both
CHx0+/CHx0-
Conversion of Both
CHx1-/CHx0-
Conversion of Both
CHx1+/CHx0-
M0
M1
PRODUCT PREVIEW
RD
CS
0ms
0.5ms
1.0ms
1.5ms
Conversion of Both
CHx0+/CHx02.0ms
Figure 22. Pseudo-Differential Mode I (M0 = 0; M1 = 0)
20
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Conversion of Both
CHx1-/CHx02.5ms
3.0ms
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PSEUDO-DIFFERENTIAL MODE II
(Not ADS7861-Compatible)
Channel switching is performed by setting the C[1:0]
bits in the SDI Register accordingly (see also the
Serial Data Input section).
In Mode II, the ADS7863 input multiplexers can also
operate in a pseudo-differential configuration. In this
case, output data are available on terminal SDOA
only, while SDOB is held in tri-state.
16
1
1
16
1
The input multiplexer cannot be used for
pseudo-differential signals in Mode III or Mode IV.
16
1
16
1
16
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
SDI
C[1:0] = '00' ® CHx0+/CHx0-
C[1:0] = '01' ® CHx1-/CHx0-
C[1:0] = '10' ® CHx1+/CHx0-
P[1:0] = '00' ® Features OFF
P[1:0] = '11' ® Features OFF
P[1:0] = '00' ® Features OFF
M1
RD
CS
SDOA
Previous 12-Bit
Data CHAx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0 ms
12-Bit Data
CHB0+/CHA0-
12-Bit Data
CHA0+/CHA0-
12-Bit Data
CHA1-/CHA0-
12-Bit Data
CHA1+/CHA0-
12-Bit Data
CHB1-/CHB0-
High-Z
Conversion of Both
CHx0+/CHx00.5ms
No Conversion,
Read Data Only
1.0ms
Conversion of Both
CHx1+/CHx01.5ms
No Conversion,
Read Data Only
2.0ms
Conversion of Both
CHx1+/CHx02.5ms
3.0ms
Figure 23. Pseudo-Differential Mode II (M0 = 0; M1 = 1)
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PRODUCT PREVIEW
M0
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Programming the Reference
(Not ADS7861-Compatible)
DAC
The internal reference DAC can be set by issuing an
RD pulse while providing an SDI word with P[1:0] =
'01' and A[2:0] = '001'. Thereafter, a second RD
pulse must be generated with an SDI word starting
with '00' followed by the actual 10-bit DAC value (see
Figure 24). During the second access, the first two
'00' bits are not interpreted as channel selection bits.
read access. Triggering the RD line again causes the
SDOA output to send '0000' followed by the 10-bit
DAC value and another '00'. During the second RD
access, data present on SDI are ignored, while in
Mode I and Mode III valid conversion data for
channel B are present on SDOB. The default value
of the DAC register after power-up is 0x3FF,
corresponding to a reference voltage of 2.5V on the
REFOUT pin.
To verify the DAC setting, an RD pulse must be
generated while providing an SDI word containing
P[1:0] = '01' and A[2:0] = '011' to initialize the DAC
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
CONVST
PRODUCT PREVIEW
10-Bit
DAC Value
SDI
C[1:0] = '00' ® CHx0 is Next
P[1:0] = '01' ® Features ON
A[2:0] = '001' ® Write DAC
Data Interpreted as
DAC Value Only
C[1:0] = '11' ® CHx1 is Next
P[1:0] = '01' ® Features ON
A[2:0] = '011' ® Read DAC
SDOA
Previous 12-Bit
Data CHAx
12-Bit
Data CHA0
12-Bit
Data CHA0
SDOB
Previous 12-Bit
Data CHBx
12-Bi
Data CHB0
12-Bit
Data CHB0
BUSY
Previous Conversion
of Both CHxx
SDI Data Ignored
C[1:0] = '00' ® CHx0 is Next C[1:0] = '00' ® CHx0 is Next
P[1:0] = '11' ® No Features P[1:0] = '11' ® No Features
M0
M1
RD
CS
0ms
Conversion of
Both CHx0
0.5ms
10-Bit
DAC Value
12-Bit
Data CHB1
Conversion of
Both CHx0
1.0ms
12-Bit
Data CHA0
12-Bit
Data CHB1
12-Bit
Data CHB0
Conversion of
Both CHx1
Conversion of
Both CHx1
1.5ms
12-Bit
Data CHA1
2.0ms
Figure 24. DAC Write and Read Access Timing Diagram
22
Submit Documentation Feedback
Conversion of
Both CHx0
2.5ms
3.0ms
ADS7863
www.ti.com
SBAS383 – JUNE 2007
Reset
The ADS7863 has a comprehensive built-in
power-down feature. There are three power-down
modes: deep power-down, nap power-down, and
auto-nap power-down. All three power-down modes
are activated with the 12th falling CLOCK edge of
the SDI access, during which the related bit asserts
(DP = '1', N = '1', or AN = '1'). All modes are
deactivated by de-asserting the respective bit in the
SDI Register. Contents of the SDI Register are not
affected by any of the power-down modes. Any
ongoing conversion aborts when deep or nap
power-down is initiated. Table 8 lists the differences
among the three power-down modes.
In deep power-down mode, all functional blocks
except the digital interface are disabled. The analog
block has its bias currents and the internal oscillator
turned off. In this mode, the power dissipation
reduces to 1μA within 2μs. The wake-up time from
deep power-down mode is 1μs.
In nap power-down mode, the ADS7863 turns off
the biasing of the comparator and the mid-voltage
buffer. In this mode, power dissipation reduces to
approximately 0.3mA within 200ns. The device goes
into nap power-down mode regardless of the
conversion state.
The auto-nap power-down mode is almost identical
to the nap mode. The only difference is the time
required to power down and the method of waking
up the device. The SDI Register bit AN is only used
to enable/disable this feature. If the auto-nap mode
is enabled, the ADS7863 turns off the biasing
automatically after finishing a conversion; thus, the
end of conversion actually activates the auto-nap
power-down. Device power dissipation reduces to
about 0.3mA within 200ns in this mode, as well.
Triggering a new conversion by applying a CONVST
pulse puts the device back into normal operation.
To issue a device reset, an RD pulse must be
generated along with an SDI word containing A[2:0]
= '101'. With the 12th falling edge after generating
the RD pulse, the entire device—including the serial
interface—is forced into reset. After approximately
20ns, the serial interface becomes active again.
Table 8. Power-Down Modes
POWERDOWN TYPE
POWER
DISSIPATION
ENABLED
BY
Deep
1μA
DP = ‘1’
Nap
300μA
N = ‘1’
Auto-nap
300μA
AN = ‘1’
ACTIVATED
BY
ACTIVATION
TIME
RESUMED
BY
REACTIVATION
TIME
DISABLED
BY
12th clock
2μs
12th clock
200ns
DP = ‘0’
1μs
DP = ‘0’
N = ‘0’
3 clocks
Each end of
conversion
N = ‘0’
200ns
CONVST pulse
3 clocks
AN = ‘0’
Submit Documentation Feedback
23
PRODUCT PREVIEW
Power-Down
Modes and
(Not ADS7861-Compatible)
ADS7863
www.ti.com
SBAS383 – JUNE 2007
LAYOUT
For optimum performance, care should be taken with
the physical layout of the ADS7863 circuitry. This
condition is particularly true if the CLOCK input is
approaching the maximum throughput rate. The
basic SAR architecture is quite sensitive to glitches
or sudden changes on the power supply, reference,
ground connections, and digital inputs that occur just
prior to latching the output of the analog comparator.
Therefore, driving any single conversion for an n-bit
SAR converter, there are n windows in which large
external transient voltages can affect the conversion
result. Such glitches might originate from switching
power supplies, nearby digital logic, or high-power
devices. The degree of error in the digital output
depends on the reference voltage, layout, and the
exact timing of the external event. These errors can
change if the external event also changes in time
with respect to the CLOCK input.
PRODUCT PREVIEW
With this possibility in mind, power to the ADS7863
should be clean and well-bypassed. A 0.1μF ceramic
bypass capacitor should be placed as close to the
device as possible. In addition, a 1μF to 10μF
capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
If the reference voltage is external and originates
from an operational amplifier, be sure that it can
drive the bypass capacitor or capacitors without
oscillation.
Grounding
The xGND pins should be connected to a clean
ground reference. These connections should be kept
as short as possible to minimize the inductance of its
path. It is recommended to use vias connecting the
pads directly to the ground plane. In designs without
ground planes, the ground trace should be kept as
wide as possible. Avoid connections that are too
near the grounding point of a microcontroller or
digital signal processor.
Depending on the circuit density on the board,
placement of the analog and digital components, and
the related current loops, a single solid ground plane
for the entire printed circuit board (PCB) or a
dedicated analog ground area may be used. In an
instance of a separated analog ground area, ensure
a low-impedance connection between the analog
and digital ground of the ADC by placing a bridge
24
underneath (or next) to the ADC. Otherwise, even
short undershoots on the digital interface with a
value lower than –300mV will lead to conduction of
ESD diodes, causing current flow through the
substrate and degrading the analog performance.
During the PCB layout, care
avoid any return currents
analog areas or signals. No
limit of –300mV with respect
plane.
should also be taken to
crossing any sensitive
signal must exceed the
to the according ground
Supply
The ADS7863 has two separate supplies, the BVDD
pin for the digital interface and the AVDD pin for all
remaining (analog) circuits.
BVDD can range from 1.65V to 5.5V, allowing the
ADS7863 to interface with all state-of-the-art
processors and controllers. To limit the injection of
noise energy from external digital circuitry, BVDD
should be filtered properly. Bypass capacitors of
0.1μF and 10μF should be placed between the BVDD
pin and the ground plane.
AVDD is used to supply the internal analog circuitry.
For optimum performance, a linear regulator (for
example, the UA7805 family) is recommended to
generate the analog supply voltage in the range of
2.7V to 5.5V for the ADS7863 and the necessary
analog front-end circuitry.
Bypass capacitors should be connected to
ground plane such that the current is allowed to
through the pad of the capacitor (that is, the
should be placed on the opposite side of
connection between the capacitor and
power-supply pin of the ADC).
the
flow
vias
the
the
Digital Interface
To further optimize device performance, a resistor of
10Ω to 100Ω can be used on each digital pin of the
ADS7863. In this way, the slew rate of the input and
output signals is reduced, limiting the noise injection
from the digital interface.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS7863IDBQ
PREVIEW
SSOP/
QSOP
DBQ
24
56
TBD
Call TI
Call TI
ADS7863IDBQR
PREVIEW
SSOP/
QSOP
DBQ
24
2500
TBD
Call TI
Call TI
ADS7863IRGER
PREVIEW
QFN
RGE
24
3000
TBD
Call TI
Call TI
ADS7863IRGET
PREVIEW
QFN
RGE
24
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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