TI ADS8363SRHBT

ADS8363
ADS7263
ADS7223
www.ti.com
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
Dual, 1MSPS, 16-/14-/12-Bit, 4×2 or 2×2 Channel, Simultaneous Sampling
Analog-to-Digital Converter
Check for Samples: ADS8363, ADS7263, ADS7223
FEATURES
DESCRIPTION
•
•
•
The ADS8363 is a dual, 16-bit, 1MSPS
analog-to-digital converter (ADC) with eight pseudoor four fully-differential input channels grouped into
two pairs for simultaneous signal acquisition. The
analog inputs are maintained differentially to the input
of the ADC. The input multiplexer can be used in
either pseudo-differential mode, supporting up to four
channels per ADC (4x2), or in fully-differential mode
that allows to convert up to two inputs per ADC (2x2).
The ADS7263 is a 14-bit version while the ADS7223
is a 12-bit version of the ADS8363.
1
2
•
•
•
•
•
Eight Pseudo- or Four Fully-Differential Inputs
Simultaneous Sampling of Two Channels
Excellent AC Performance:
– SNR:
93dB (ADS8363)
85dB (ADS7263)
73dB (ADS7223)
– THD:
–98dB (ADS8363)
–92dB (ADS7263)
–86dB (ADS7223)
Dual Programmable and Buffered 2.5V
Reference Allows:
– Two Different Input Voltage Range Settings
– Two-Level PGA Implementation
Programmable Auto-Sequencer
Integrated Data Storage (up to 4 per channel)
for Oversampling Applications
2-Bit Counter for Safety Applications
Fully Specified over the Extended Industrial
Temperature Range
APPLICATIONS
•
•
•
•
•
•
Motor Control: Current and Position
Measurement including Safety Applications
Power Quality Measurement
Three-Phase Power Control
Programmable Logic Controllers
Industrial Automation
Protection Relays
The ADS8363/7263/7223 offer two programmable
reference outputs, flexible supply voltage ranges, a
programmable auto-sequencer, data storage of up to
four conversion results per channel, and several
power-down features.
All devices are offered in a 5x5mm QFN-32 package.
Functional Block Diagram
AVDD
CHA1P/CHA3
CHA1N/CHA2
CHA0P/CHA1
CHA0N/CHA0
CMA
Input
Mux
DVDD
CLOCK
Serial
Interface
and
FIFO
REF1
REF2
CHB1P/CHB3
CHB1N/CHB2
CHB0P/CHB1
CHB0N/CHB0
CMB
CS
SAR ADC
BUSY
SDI
RD
SDOA
Input
Mux
SAR ADC
SDOB
REF1
String
DAC
REFIO1
2.5V
REF
Control
Logic
M1
CONVST
REF2
REFIO2
M0
String
DAC
RGND
AGND
DGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
FAMILY OVERVIEW
(1)
PRODUCT
RESOLUTION
NMC
INL
SNR
THD
ADS8363
16 bits
16 or 15 bits (1)
±3 or ±4 LSB (1)
93dB (typ)
–98dB (typ)
ADS7263
14 bits
14 bits
±1 LSB
85dB (typ)
–92dB (typ)
ADS7223
12 bits
12 bits
±0.5 LSB
73dB (typ)
–86dB (typ)
See Electrical Characteristics.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
ADS8363, ADS7263, ADS7223
UNIT
–0.3 to +6
V
1.2 × AVDD (2)
V
Analog and reference input voltage with respect to AGND
AGND – 0.3 to AVDD + 0.3
V
Digital input voltage with respect to DGND
DGND – 0.3 to DVDD + 0.3
V
Ground voltage difference |AGND-DGND|
0.3
V
Input current to any pin except supply pins
–10 to +10
mA
Supply voltage, AVDD to AGND or DVDD to DGND
Supply voltage, DVDD to AVDD
Maximum virtual junction temperature, TJ
Electrostatic
discharge (ESD)
ratings, all pins
(1)
(2)
+150
°C
Human body model (HBM),
JEDEC standard 22, test method A114-C.01
±2000
V
Charged device model (CDM),
JEDEC standard 22, test method C101
±500
V
Stresses above these ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied. Exposure to absolute maximum conditions for extended
periods may affect device reliability.
Exceeding the specified limit causes an increase of the DVDD leakage current and leads to malfunction of the device.
THERMAL INFORMATION
ADS8363,
ADS7263,
ADS7223
THERMAL METRIC (1)
UNITS
RHB
32 PINS
qJA
Junction-to-ambient thermal resistance
33.3
qJCtop
Junction-to-case (top) thermal resistance
29.5
qJB
Junction-to-board thermal resistance
7.3
yJT
Junction-to-top characterization parameter
0.2
yJB
Junction-to-board characterization parameter
7.4
qJCbot
Junction-to-case (bottom) thermal resistance
0.9
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
ADS8363
ADS7263
ADS7223
www.ti.com
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS: ADS8363
All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA =
1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS8363
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
UNIT
16
Bits
DC ACCURACY
INL
Integral nonlinearity
DNL
Differential nonlinearity
VOS
Input offset error
VOS match
dVOS/dT
Half-clock mode
–3
±1.2
+3
LSB
Full-clock mode
–4
±1.5
+4
LSB
Half-clock mode
–0.99
±0.6
+2
LSB
Full-clock mode
–1.5
±0.8
+3
LSB
–2
±0.2
+2
mV
–1
±0.1
+1
mV
ADC to ADC
Input offset thermal drift
1
mV/°C
Gain error
Referenced to the voltage at
REFIOx
–0.1
±0.01
+0.1
%
GERR match
ADC to ADC
–0.1
±0.005
+0.1
%
GERR/dT
Gain error thermal drift
Referenced to the voltage at
REFIOx
CMRR
Common-mode rejection ratio
Both ADCs, dc to 100kHz
GERR
1
ppm/°C
92
dB
AC ACCURACY
SINAD
Signal-to-noise + distortion
VIN = 5VPP at 10kHz
89
92
dB
SNR
Signal-to-noise ratio
VIN = 5VPP at 10kHz
90
93
dB
THD
Total harmonic distortion
VIN = 5VPP at 10kHz
SFDR
Spurious-free dynamic range
VIN = 5VPP at 10kHz
–98
90
–90
dB
100
dB
ELECTRICAL CHARACTERISTICS: ADS7263
All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA =
1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS7263
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
UNIT
14
Bits
DC ACCURACY
INL
Integral nonlinearity
DNL
Differential nonlinearity
VOS
Input offset error
VOS match
–1
±0.4
+1
LSB
–0.5
±0.2
+1
LSB
–2
±0.2
+2
mV
–1
±0.1
+1
ADC to ADC
1
mV
dVOS/dT
Input offset thermal drift
GERR
Gain error
Referenced to the voltage at
REFIOx
–0.1
±0.01
+0.1
%
GERR match
ADC to ADC
–0.1
±0.005
+0.1
%
GERR/dT
Gain error thermal drift
Referenced to the voltage at
REFIOx
CMRR
Common-mode rejection ratio
Both ADCs, dc to 100kHz
mV/°C
1
ppm/°C
92
dB
dB
AC ACCURACY
SINAD
Signal-to-noise + distortion
VIN = 5VPP at 10kHz
82
84
SNR
Signal-to-noise ratio
VIN = 5VPP at 10kHz
84
85
THD
Total harmonic distortion
VIN = 5VPP at 10kHz
SFDR
Spurious-free dynamic range
VIN = 5VPP at 10kHz
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
–92
88
dB
–88
92
Submit Documentation Feedback
dB
dB
3
ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS7223
All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA =
1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS7223
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
12
UNIT
Bits
DC ACCURACY
INL
Integral nonlinearity
–0.5
±0.2
+0.5
LSB
DNL
Differential nonlinearity
–0.5
±0.1
+0.5
LSB
VOS
Input offset error
–2
±0.2
+2
mV
–1
±0.1
+1
VOS match
ADC to ADC
1
mV
dVOS/dT
Input offset thermal drift
GERR
Gain error
Referenced to the voltage at
REFIOx
–0.1
±0.01
+0.1
%
GERR match
ADC to ADC
–0.1
±0.005
+0.1
%
GERR/dT
Gain error thermal drift
Referenced to the voltage at
REFIOx
CMRR
Common-mode rejection ratio
Both ADCs, dc to 100kHz
mV/°C
1
ppm/°C
92
dB
72
dB
AC ACCURACY
SINAD
Signal-to-noise + distortion
VIN = 5VPP at 10kHz
71
SNR
Signal-to-noise ratio
VIN = 5VPP at 10kHz
72
THD
Total harmonic distortion
VIN = 5VPP at 10kHz
SFDR
Spurious-free dynamic range
VIN = 5VPP at 10kHz
73
–86
84
dB
–84
86
dB
dB
ELECTRICAL CHARACTERISTICS: GENERAL
All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA =
1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS8363, ADS7263, ADS7223
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
+VREF
V
ANALOG INPUT
FSR
Full-scale input range
(CHxxP – CHxxN) or CHxx to
CMx
VIN
Absolute input voltage
CHxxx to AGND
CIN
Input capacitance
CHxxx to AGND
CID
Differential input capacitance
IIL
Input leakage current
PSRR
Power-supply rejection ratio
–VREF
–0.1
AVDD + 0.1
pF
22.5
pF
–16
AVDD = 5.5V
V
45
16
75
nA
dB
SAMPLING DYNAMICS
tCONV
Conversion time per ADC
tACQ
Acquisition time
fDATA
Data rate
tA
Aperture delay
tA match
tAJIT
17.5
tCLK
Full-clock mode
35
tCLK
Half-clock mode
2
tCLK
Full-clock Mode
4
tCLK
25
Clock frequency
tCLK
Clock period
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1000
6
ADC to ADC
50
Aperture jitter
fCLK
4
Half-clock mode
kSPS
ns
ps
50
ps
Half-clock mode
0.5
20
MHz
Full-clock mode
1
40
MHz
Half-clock mode
50
2000
ns
Full-clock mode
25
1000
ns
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
ADS8363
ADS7263
ADS7223
www.ti.com
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS: GENERAL (continued)
All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA =
1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS8363, ADS7263, ADS7223
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REFERENCE
Resolution
Reference output DAC resolution
10
Over 20% to 100% DAC range
VREFOUT
Reference output voltage
Bits
0.2VREFOUT
VREFOUT
V
REFIO1, DAC = 3FFh,
2.485
2.500
2.515
V
REFIO2, DAC = 3FFh
2.480
2.500
2.520
V
dVREFOUT/dT
Reference voltage drift
DNLDAC
DAC differential linearity error
–4
±10
±1
4
LSB
INLDAC
DAC integral linearity error
–4
±0.5
4
LSB
VOSDAC
DAC offset error
–4
±1
4
LSB
PSRR
Power-supply rejection ratio
IREFOUT
Reference output dc current
+2
mA
IREFSC
Reference output short-circuit
current (1)
tREFON
Reference output settling time
VREFOUT = 0.5V
ppm/°C
73
dB
–2
50
mA
8
ms
CREF= 22mF
VOLTAGE REFERENCE INPUT
VREF
Reference input voltage range
IREF
Reference input current
0.5
2.5
50
2.525
mA
V
CREF
External ceramic reference
capacitance
22
mF
DIGITAL INPUTS (2)
IIN
Input current
CIN
Input capacitance
VIN = DVDD to DGND
–50
+50
5
Logic family
nA
pF
CMOS with Schmitt-Trigger
VIH
High-level input voltage
DVDD = 4.5V to 5.5V
0.7DVDD
DVDD + 0.3
V
VIL
Low-level input voltage
DVDD = 4.5V to 5.5V
–0.3
0.3DVDD
V
Logic family
LVCMOS
VIH
High-level input voltage
DVDD = 2.3V to 3.6V
2
DVDD + 0.3
V
VIL
Low-level input voltage
DVDD = 2.3V to 3.6V
–0.3
0.8
V
DIGITAL OUTPUTS
(2)
V
COUT
Output capacitance
CLOAD
Load capacitance
5
Logic family
pF
CMOS
VOH
High-level output voltage
DVDD = 4.5V, IOH = –100µA
VOL
Low-level output voltage
DVDD = 4.5V, IOH = +100µA
4.44
V
0.5
Logic family
V
LVCMOS
VOH
High-level output voltage
DVDD = 2.3V, IOH = –100µA
VOL
Low-level output voltage
DVDD = 2.3V, IOH = +100µA
(1)
(2)
pF
30
DVDD – 0.2
V
0.2
V
Reference output current is not internally limited.
Specified by design; not production tested.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
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5
ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: GENERAL (continued)
All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA =
1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS8363, ADS7263, ADS7223
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD to AGND, half-clock mode
2.7
5.0
5.5
V
AVDD to AGND, full-clock mode
4.5
5.0
5.5
V
3V and 3.3V levels
2.3
2.5
3.6
V
5V levels, half-clock mode only
4.5
5.0
5.5
V
AVDD = 3.6V
12.0
16.0
mA
AVDD = 5.5V
15.0
20.0
mA
AVDD = 3.6V, sleep/auto-sleep
modes
0.8
1.2
mA
AVDD = 5.5V, sleep/auto-sleep
modes
0.9
1.4
mA
0.005
mA
mA
POWER SUPPLY
AVDD
DVDD
AIDD
Analog supply voltage
Digital supply voltage
Analog supply current
Power-down mode
DIDD
PD
6
Digital supply current
Power dissipation (normal
operation)
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DVDD = 3.6V, CLOAD = 10pF
1.1
2.5
DVDD = 5.5V, CLOAD = 10pF
3
6
mA
AVDD = DVDD = 3.6V
47.2
66.6
mW
AVDD = 5.5V, DVDD = 3.6V
86.5
117.0
mW
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
ADS8363
ADS7263
ADS7223
www.ti.com
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
PIN CONFIGURATION
CMB
CMA
AGND
AVDD
DGND
DVDD
NC
SDOA
RHB PACKAGE
QFN-32
(TOP VIEW)
32
31
30
29
28
27
26
25
CHB1P/CHB3
1
24
SDOB
CHB1N/CHB2
2
23
BUSY
CHB0P/CHB1
3
22
CLOCK
21
CS
20
RD
19
CONVST
18
SDI
17
M0
CHB0N/CHB0
4
CHA1P/CHA3
5
CHA1N/CHA2
6
CHA0P/CHA1
7
ADS8363
ADS7263
ADS7223
(Thermal Pad)
12
13
14
AVDD
NC
15
16
M1
11
NC
10
AGND
REFIO1
9
RGND
8
REFIO2
CHA0N/CHA0
Pin Descriptions
PIN
NAME
NO.
TYPE (1)
CHB1P/CHB3
1
AI
Fully-differential noninverting analog input channel B1 or pseudo-differential input B3
CHB1N/CHB2
2
AI
Fully-differential inverting analog input channel B1 or pseudo-differential input B2
DESCRIPTION
CHB0P/CHB1
3
AI
Fully-differential noninverting analog input channel B0 or pseudo-differential input B1
CHB0N/CHB0
4
AI
Fully-differential inverting analog input channel B0 or pseudo-differential input B0
CHA1P/CHA3
5
AI
Fully-differential noninverting analog input channel A1 or pseudo-differential input A3
CHA1N/CHA2
6
AI
Fully-differential inverting analog input channel A1 or pseudo-differential input A2
CHA0P/CHA1
7
AI
Fully-differential nonInverting analog input channel A1 or pseudo-differential input A1
CHA0N/CHA0
8
AI
Fully-differential inverting analog input channel A1 or pseudo-differential input A0
REFIO1
9
AIO
Reference voltage input/output 1. A ceramic capacitor of 22µF connected to RGND is required.
REFIO2
10
AIO
Reference voltage input/output 2. A ceramic capacitor of 22µF connected to RGND is required.
RGND
11
P
Reference ground. Connect to analog ground plane with a dedicated via.
AGND
12, 30
P
Analog ground. Connect to analog ground plane.
AVDD
13, 29
P
Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1mF ceramic capacitor.
NC
14,
15, 26
NC
This pin is not internally connected.
M1
16
DI
Mode pin 1. Selects the digital output mode (see Table 4).
M0
17
DI
Mode pin 0. Selects analog input channel mode (see Table 4).
SDI
18
DI
Serial data input. This pin is used to set up of the internal registers, and can also be used in
ADS8361-compatible manner. The data on SDI are ignored when CS is high.
CONVST
19
DI
Conversion start. The ADC switches from sample into hold mode on the rising edge of CONVST.
Thereafter, the conversion starts with the next rising edge of the CLOCK pin.
RD
20
DI
Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is
low.
(1)
AI = analog input, AIO = analog input/output, DI = digital input, DO = digital output, DIO = digital input/output, P = power supply, NC =
not connected.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
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7
ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
www.ti.com
Pin Descriptions (continued)
PIN
8
NAME
NO.
TYPE (1)
CS
21
DI
Chip select. When this pin is low, the SDOx, SDI, and RD pins are active; when this pin is high, the
SDOx outputs are 3-stated, while the SDI and RD inputs are ignored.
CLOCK
22
DI
External clock input. The range is 0.5MHz to 20MHz in half-clock mode, or 1MHz to 40MHz in
full-clock mode.
BUSY
23
DO
Converter busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after
the conversion is complete.
SDOB
24
DO
Serial data output for converter B. Active only if M1 is low. 3-state when CS is high.
SDOA
25
DO
Serial data output for converter A. 3-state when CS is high.
DVDD
27
P
Digital supply, 2.3V to 5.5V. Decouple to DGND with a 1mF ceramic capacitor.
DGND
28
P
Digital ground. Connect to digital ground plane.
CMA
31
AI
Common-mode voltage input for channels Ax (in pseudo-differential mode only).
CMB
32
AI
Common-mode voltage input for channels Bx (in pseudo-differential mode only).
DESCRIPTION
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
ADS8363
ADS7263
ADS7223
www.ti.com
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
TIMING DIAGRAMS
tCLK
tCLKL
1
tCLKH
18
21
CLOCK
tCONV
tACQ
CS
t1
t2
CONVST
tDATA
tD2
tD1
BUSY
conversion n
tH1
tS1
t3
RD
tD5
SDOx(1)
(CID = ‘0’)
tH3
data n-1
CH
AD
0/1
A/B
MSB
D14
D13
D12
D11
D10
D9
tD6
tD3
D8
D7
D6
D5
D4
D3
D2
D6
D5
D4
D3
D2
D1
D0
D1
D0
CH
0/1
data n-1
SDOx(1)
(CID = ‘1’)
MSB
D14
D13
D12
D11
tS2
SDI
(1)
D15
D14
D13
D10
D9
D8
D7
MSB
tH2
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
The ADS7263/7223 output data with the MSB located as ADS8363 and last 2/4 bits being '0'.
Figure 1. Detailed Timing Diagram: Half-Clock Mode (ADS8361-Compatible)
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TIMING DIAGRAMS (continued)
tCLK
1
tCLKL
tCLKH
23
25
36
41
CLOCK
tCONV
tACQ
CS
tDATA
t1
t2
CONVST
tD2
tD1
BUSY
conversion n
tH1
tS1
RD
tD5
(CID = ‘0’)
SDOx
(1)
tH4
data n
CH AD
0/1 A/B
M
S
B
D
14
D
13
D
12
D
15
D
13
D
12
D
11
D
10
D
11
D
10
tD4
D9 D8 D7 D6 D5 D4 D3 D0 D1 D0
tS2
SDI
D
14
tD6
tH2
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RD
tD5
(CID = ‘1’)
data n
tH4
SDOx(1)
M
S
B
D
14
D
13
D
12
SDI
D
15
D
14
D
13
D
12
D
11
D
10
D
11
D
10
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tS2
(2)
tD4
tH2
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
The ADS7263/7223 output data with the MSB located as ADS8363 and last 2/4 bits being '0'.
Figure 2. Detailed Timing Diagram: Full-Clock Mode
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TIMING CHARACTERISTICS (1)
Over the recommended operating free-air temperature range of –40°C to +125°C, and DVDD = 2.3V to 5.5V, unless
otherwise noted.
ADS8363, 7263, 7223
PARAMETER
tDATA
Data throughput
tCONV
Conversion time
tACQ
Acquisition time
fCLK
TEST CONDITIONS
fCLK = max
MIN
MAX
1
ms
Half-clock mode
17.5
tCLK
Full-clock mode
35
tCLK
100
Half-clock mode
CLOCK frequency
UNIT
0.5
ns
20
MHz
MHz
Full-clock mode
1
40
Half-clock mode
50
2000
ns
Full-clock mode
25
1000
ns
tCLK
CLOCK period
tCLKL
CLOCK low time
11.25
ns
tCLKH
CLOCK high time
11.25
ns
t1
CONVST rising edge to first CLOCK rising edge
12
ns
10
ns
t2
CONVST high time
t3
RD high time
tS1
RD high to CLOCK falling edge setup time
5
ns
tH1
RD high to CLOCK falling edge hold time
5
ns
tS2
Input data to CLOCK falling edge setup time
5
ns
tH2
Input data to CLOCK falling edge hold time
4
tD1
CONVST rising edge to BUSY high delay (2)
tD2
CLOCK 18th falling edge (half-clock mode) or
24th rising edge (full-clock mode) to BUSY low
delay
tD3
CLOCK rising edge to next data valid delay
Half-clock mode: timing
modes II and IV only
1
tCLK
Half-clock mode: timing
modes II, IV, SII, and SIV
only
1
tCLK
19
ns
4.5V < DVDD < 5.5V
16
ns
2.3V < DVDD < 3.6V
25
ns
4.5V < DVDD < 5.5V
20
ns
Half-clock mode, 2.3V <
DVDD < 3.6V
14
ns
Half-clock mode, 4.5V <
DVDD < 5.5V
12
ns
tH3
Output data to CLOCK rising edge hold time
Half-clock mode
tD4
CLOCK falling edge to next data valid delay
Full-clock mode
tH4
Output data to CLOCK falling edge hold time
Full-clock mode
tD5
RD falling edge to first data valid
tD6
CS rising edge to SDOx 3-state
(1)
(2)
ns
2.3V < DVDD < 3.6V
3
ns
19
7
ns
ns
2.3V < DVDD < 3.6V
16
ns
4.5V < DVDD < 5.5V
12
ns
6
ns
All input signals are specified with tR = tF = 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
Not applicable in auto-sleep power-down mode.
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted.
INTEGRAL NONLINEARITY vs
DATA RATE
DIFFERENTIAL NONLINEARITY vs
DATA RATE
3.0
3.0
ADS8363 Positive
ADS7263 Positive
ADS7223 Positive
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0
-0.5
-1.0
-1.5
200
300
400 500 600 700
Data Rate (kSPS)
800
900
0
-0.5
-1.0
ADS8363 Negative
ADS7263 Negative
ADS7223 Negative
-2.5
-3.0
-3.0
100
0.5
-1.5
-2.0
ADS8363 Negative
ADS7263 Negative
ADS7223 Negative
-2.0
-2.5
ADS8363 Positive
ADS7263 Positive
ADS7223 Positive
2.5
DNL (LSB)
INL (LSB)
2.0
1000
100
200
300
400 500 600 700
Data Rate (kSPS)
Figure 3.
INTEGRAL NONLINEARITY vs CODE
1.5
1.5
1.0
1.0
DNL (LSB)
INL (LSB)
2.0
0.5
0
-0.5
-1.0
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-2.5
-3.0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
Figure 6.
INTEGRAL NONLINEARITY vs
TEMPERATURE
DIFFERENTIAL NONLINEARITY vs
TEMPERATURE
3.0
ADS8363
AVDD = 5V, Positive
AVDD = 3V, Positive
2.5
2.0
1.5
1.0
1.0
DNL (LSB)
1.5
0.5
0
-0.5
-1.0
-2.5
-3.0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Figure 5.
3.0
INL (LSB)
0.5
-1.5
-2.0
-1.5
-2.0
ADS8363
2.5
2.0
2.0
5
-0.5
-1.0
-2.5
-3.0
20 35 50 65
Temperature (°C)
80
95
110 125
AVDD = 5V, Negative
AVDD = 3V, Negative
-40 -25 -10
5
Figure 7.
12
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ADS8363
AVDD = 5V, Positive
AVDD = 3V, Positive
0.5
0
-1.5
-2.0
AVDD = 5V, Negative
AVDD = 3V, Negative
-40 -25 -10
1000
DIFFERENTIAL NONLINEARITY vs CODE
3.0
ADS8363
2.5
2.5
900
Figure 4.
3.0
0
800
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 8.
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ADS7223
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted.
OFFSET ERROR AND OFFSET MATCH vs
ANALOG SUPPLY VOLTAGE
OFFSET ERROR AND OFFSET MATCH vs
TEMPERATURE
2.0
2.0
All Devices
Offset Error
Offset Match
1.5
Offset Error and Match (mV)
Offset Error and Match (mV)
All Devices
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
-2.0
-2.0
2.7
3.1
3.5
3.9
4.3
AVDD (V)
4.7
5.1
5.5
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
Figure 9.
Figure 10.
GAIN ERROR AND GAIN MATCH vs
ANALOG SUPPLY VOLTAGE
GAIN ERROR AND GAIN MATCH vs
TEMPERATURE
0.10
110 125
0.10
All Devices
0.08
Gain Error
Gain Match
0.06
0.08
Gain Error and Match (%)
Gain Error and Match (%)
1.0
-1.5
-1.5
0.04
0.02
0
-0.02
-0.04
-0.06
All Devices
Gain Error
Gain Match
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.08
-0.10
-0.10
2.7
3.1
3.5
3.9
4.3
AVDD (V)
4.7
5.1
5.5
5
-40 -25 -10
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 11.
Figure 12.
COMMON-MODE REJECTION RATIO vs
ANALOG SUPPLY VOLTAGE
COMMON-MODE REJECTION RATIO vs
TEMPERATURE
100
100
95
95
90
90
CMRR (dB)
CMRR (dB)
Offset Error
Offset Match
1.5
85
80
85
80
75
75
All devices
f = 100kHz
70
2.7
3.1
3.5
3.9
4.3
AVDD (V)
4.7
5.1
5.5
All devices
f = 100kHz
70
-40 -25 -10
5
Figure 13.
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10kHz)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10kHz, fSAMPLE = 0.5MSPS)
0
0
All Devices
-20
-20
-40
-40
-60
-60
Amplitude (dB)
Amplitude (dB)
All Devices
-80
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
50
100 150 200 250 300 350 400 450 500
Frequency (kHz)
0
100
150
Frequency (kHz)
250
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE +
DISTORTION
vs INPUT SIGNAL FREQUENCY
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE +
DISTORTION
vs TEMPERATURE
100
100
95
95
90
90
85
80
75
70
65
85
80
75
70
65
60
ADS8363 SINAD
ADS7263 SINAD
ADS7223 SINAD
ADS8363 SNR
ADS7263 SNR
ADS7223 SNR
55
ADS8363 SNR
ADS7263 SNR
ADS7223 SNR
55
ADS8363 SINAD
ADS7263 SINAD
ADS7223 SINAD
50
50
10
20
30
fIN (kHz)
40
-40 -25 -10
50
5
20 35 50 65
Temperature (°C)
80
95
Figure 17.
Figure 18.
TOTAL HARMONIC DISTORTION
vs INPUT SIGNAL FREQUENCY
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
-80
110 125
-80
ADS8363
ADS7263
ADS7223
-84
ADS8363
ADS7263
ADS7223
-84
-88
THD (dB)
-88
-92
-92
-96
-96
-100
-100
-104
-104
10
20
30
fIN (kHz)
40
50
fIN = 10kHz
-40 -25 -10
5
Figure 19.
14
200
Figure 16.
60
THD (dB)
50
Figure 15.
SNR and SINAD (dB)
SNR and SINAD (dB)
0
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Temperature (°C)
80
95
110 125
Figure 20.
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SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT SIGNAL FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
105
104
ADS8363
ADS7263
ADS7223
100
ADS8363
ADS7263
ADS7223
101
99
SFDR (dB)
96
SFDR (dB)
fIN = 10kHz
103
92
88
97
95
93
91
89
84
87
85
80
10
20
20
30
fIN (kHz)
40
20 35 50 65
Temperature (°C)
80
95
Figure 22.
ANALOG SUPPLY CURRENT
vs TEMPERATURE
DIGITAL SUPPLY CURRENT
vs TEMPERATURE
20
All Devices
AVDD = 5.5V
AVDD = 3.6V
16
14
14
IDVDD (mA)
16
12
10
8
All Devices
110 125
DVDD = 5.5V
DVDD = 3.6V
18
12
10
8
6
6
4
4
2
2
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 23.
Figure 24.
ANALOG SUPPLY CURRENT vs DATA RATE
ANALOG SUPPLY CURRENT vs DATA RATE
(Auto-Sleep Mode)
20
20
All Devices
18
External Reference
Internal Reference
16
16
14
14
12
10
8
All Devices in Auto-Sleep Mode
18
IAVDD (mA)
IAVDD (mA)
5
Figure 21.
18
IAVDD (mA)
-40 -25 -10
50
External Reference
Internal Reference
12
10
8
6
6
4
4
2
2
0
0
0
100 200 300 400 500 600 700 800 900 1000
fSAMPLE (kSPS)
0
100
200
Figure 25.
300
400
500
fSAMPLE (kSPS)
600
700
800
Figure 26.
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ADS7223
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THEORY OF OPERATION
GENERAL DESCRIPTION
The ADS8363/7263/7223 contain two 16-/14-/12-bit
analog-to-digital converters (ADCs), respectively, that
operate based on the successive approximation
register (SAR) principle. These ADCs sample and
convert simultaneously. Conversion time can be as
low as 875ns. Adding an acquisition time of 100ns,
and a margin of 25ns for propagation delay and
CONVST pulse generation, results in a maximum
conversion rate of 1MSPS.
Each ADC has a fully-differential 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage (for
example, 2.5V). For these applications, the
multiplexer can be used in a pseudo-differential 4:1
mode, where the CMx pins function as
common-mode pins and all four analog inputs are
referred to the corresponding CMx pin.
The ADS8363/7263/7223 also include a 2.5V internal
reference.
This
reference
drives
two
independently-programmable, 10-bit digital-to-analog
converters (DACs), allowing the voltage at each of
the REFIOx pins to be adjusted through the internal
REFDACx registers in 2.44mV steps. A low-noise,
unity-gain operational amplifier buffers each of the
DAC outputs and drives the REFIOx pin.
The ADS8363/7263/7223 provide a serial interface
that is compatible with the ADS8361. However,
instead of the ADS8361 A0 pin that controls the
channel selection, the ADS8363/7263/7223 offers a
serial data input (SDI) pin that supports additional
functions described in the Digital section of this data
sheet (also see the ADS8361 Compatibility section).
ANALOG
This section discusses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
Each ADC is fed by an input multiplexer, as shown in
Figure 27. Each multiplexer is used in either a
fully-differential 2:1 configuration (as shown in
Table 1) or a pseudo-differential 4:1 configuration (as
shown in Table 2).
Channel selection is performed using either the
external M0 pin or the C[1:0] bits in the Configuration
(CONFIG) register in fully-differential mode, or using
the SEQFIFO register in pseudo-differential mode. In
either case, changing the multiplexer settings impacts
the conversion started with the next CONVST pulse.
Table 1. Fully-Differential 2:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
x
CHx0P
CHx0N
1
x
CHx1P
CHx1N
Table 2. Pseudo-Differential 4:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0
CMx/REFIOx
0
1
CHx1
CMx/REFIOx
1
0
CHx2
CMx/REFIOx
1
1
CHx3
CMx/REFIOx
The input path for the converter is fully differential
and provides a good common-mode rejection of 92dB
at 100kHz (for the ADS8363). The high CMRR also
helps
suppress
noise
in
harsh
industrial
environments.
Each of the 40pF sample-and-hold capacitors (shown
as CS in Figure 28) is connected through switches to
the multiplexer output. Opening the switches holds
the sampled data during the conversion process.
After the conversion completes, both capacitors are
precharged for the duration of one clock cycle to the
voltage present at the REFIOx pin. After precharging,
the multiplexer outputs are connected to the sampling
capacitors again. The voltage at the analog input pin
is usually different from the reference voltage;
therefore, the sample capacitors must be charged to
within one-half LSB for 16-, 14-, or 12-bit accuracy
during the acquisition time tACQ (see the Timing
Diagrams).
AVDD
RSER
100W
CHxx+
CHx1N/CHx2
CHx0P/CHx1
CPAR
5pF AVDD
CS
40pF
RSER
AGND 100W
CPAR
5pF
CHx1P/CHx3
RSW
100W
RSW
100W
CS
40pF
CHxx-
Input
Mux
To
ADC
AGND
CHx0N/CHx0
Figure 28. Equivalent Analog Input Circuit
Figure 27. Input Multiplexer Configuration
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Acquisition is indicated with the BUSY signal being
low. It starts by closing the input switches (after
finishing the previous conversion and precharging)
and finishes with the rising edge of the CONVST
signal. If the device operates at full speed, the
acquisition time is typically 100ns.
The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
Equation 1, with n = 16 for the resolution of the
ADS8363, n = 14 for the ADS7263, or n = 12 for the
ADS7223:
ln(2)(n + 1)
f-3dB =
2ptACQ
(1)
With tACQ = 100ns, the minimum bandwidth of the
driving amplifier is 19MHz for the ADS8363, 17MHz
for the ADS7263, and 15MHz for the ADS7223. The
required bandwidth can be lower if the application
allows a longer acquisition time.
A gain error occurs if a given application does not
fulfill the settling requirement shown in Equation 1.
However, linearity and THD are not directly affected
as a result of precharging the capacitors.
The
OPA365
from
Texas
Instruments
is
recommended as a driver; in addition to offering the
required bandwidth, it also provides a low offset and
excellent THD performance (see also Application
Information section).
It is important to keep the voltage to all inputs within
the 0.3V limit below AGND and above AVDD, while
not allowing dc current to flow through the inputs
(exceeding these limits causes the internal ESD
diodes to conduct, leading to increased leakage
current that may damage the device). Current is only
necessary to recharge the sample-and-hold
capacitors.
Unused inputs should be directly tied to AGND or
RGND without the need of a pull-down resistor.
Analog-to-Digital Converters (ADCs)
The ADS8363/7263/7223 include two SAR-type,
1MSPS,
16-/14-/12-bit
ADCs
that
include
sample-and-hold (S&H), respectively, as shown in the
Functional Block Diagram on the front page of this
data sheet.
CONVST
The analog inputs are held with the rising edge of the
CONVST (conversion start) signal. The setup time of
CONVST referred to the next rising edge of CLOCK
(system clock) is 12ns (minimum). The conversion
automatically starts with the rising CLOCK edge. A
rising edge of CONVST should not be issued during a
conversion (that is, when BUSY is high).
The phase margin of the driving operational amplifier
is usually reduced by the ADC sampling capacitor. A
resistor placed between the capacitor and the
amplifier limits this effect; therefore, an internal 100Ω
resistor (RSER) is placed in series with the switch. The
switch resistance (RSW) is typically 100Ω, as shown in
Figure 28).
RD (read data) and CONVST can be shorted to
minimize necessary software and wiring. The RD
signal is triggered by the device on the falling edge of
CLOCK. Therefore, the combined signals must be
activated with the rising CLOCK edge. The
conversion then starts with the subsequent rising
CLOCK edge. In modes with only SDOA active (that
is, in modes II, IV, SII, and SIV), the maximum length
of the combined RD and CONVST signal is one clock
cycle if the half-clock timing is used.
An input driver may not be required, if the impedance
of the signal source (RSOURCE) fulfills the requirement
of Equation 2:
tACQ
RSOURCE <
- (RSER + RSW)
CSln(2)(n + 1)
If CONVST and RD are combined, CS must be low
whenever a new conversion starts; however, this
condition is not required if RD and CONVST are
controlled separately. Note that if FIFO is used,
CONVST must be controlled separately from RD.
Where:
n = 16/14/12 for the resolution of the
ADS8363/7263/7223, respectively.
CS = 40pF sample capacitance.
RSER = 100Ω input resistor value.
RSW = 100Ω switch resistance value.
(2)
After completing a conversion, the sample capacitors
are automatically precharged to the value of the
reference voltage used to significantly reduce the
crosstalk among the multiplexed input channels.
With tACQ = 100ns, the maximum source impedance
should be less than 12Ω for the ADS8363, less than
40Ω for the ADS7263, and less than 77Ω for the
ADS7223. The source impedance can be higher if the
ADC is used at a lower data rate.
The differential input voltage range of the ADC is
±VREF, the voltage at the selected REFIOx pin.
CLOCK
The ADS8363/7263/7223 use an external clock with
an allowable frequency range that depends on the
mode being used. By default (after power-up), the
ADC operates in half-clock mode, which supports a
clock in the range of 0.5MHz to 20MHz. In full-clock
mode, the ADC requires a clock in the range of 1MHz
to 40MHz. For maximum data throughput, the clock
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signal should be continuously running. However, in
applications that use the device in burst mode, the
clock may be held static low or high upon completion
of the read access and before starting a new
conversion.
capacitor connected. Smaller reference capacitance
values reduce the DNL, INL, and ac performance of
the device. By default, both reference outputs are
disabled and the respective values are set to 2.5V
after power-up.
The CLOCK duty cycle should be 50%. However, the
device functions properly with a duty cycle between
30% and 70%.
For applications that use an external reference
source, the internal reference can be disabled
(default) using the RPD bit in the CONFIG register
(see the Digital section). The REFIOx pins are
directly connected to the ADC; therefore, the internal
switching generates spikes that can be observed at
this pin. Therefore, also in this case, an external
22µF capacitor to the analog ground (AGND) should
be used to stabilize the reference input voltage.
RESET
The ADS8363/7263/7223 feature an internal
power-on reset (POR) function. A user-controlled
reset can also be issued using SDI register bits A[3:0]
(see the Digital section).
Disabled REFIOx pins can be left floating or can be
directly tied to AGND or RGND.
REFIOx
The ADS8363/7263/7223 include a low-drift, 2.5V
internal reference source. This source feeds two,
10-bit string DACs that are controlled through
registers. As a result of this architecture, the
reference voltages at REFIOx are programmable in
2.44mV steps and can be adjusted to the application
requirements without the use of additional external
components. The actual output voltage can be
calculated using Equation 3, with code being the
decimal value of the REFDACx register content:
2.5V(code +1)
VREF =
1024
(3)
Each of the reference DAC outputs can be
individually selected as a source for each channel
input using the Rxx bits in the REFCM register.
Figure 29 illustrates a simplified block diagram of the
internal circuit.
ADC A
REFCM Bits[3:0]
REFCM Bits[7:4]
The reference DAC has a fixed transition at the code
508 (0x1FC). At this code, the DAC may show a jump
of up to 10mV in its transfer function. Table 3 lists
some examples of internal reference DAC settings.
However, to ensure proper performance, the
REFDACx output voltage should not be programmed
below 0.5V.
Table 3. REFDACx Setting Examples
VREFOUT
(NOM)
DECIMAL
CODE
BINARY
CODE
HEXADECIMAL
CODE
0.5000V
205
00 1100 1101
0CD
1.2429V
507
01 1111 1100
1FB
1.2427V
508
01 1111 1101
1FC
2.5000V
1023
11 1111 1111
3FF
A minimum of 22mF capacitance is required on each
REFIOx output to keep the references stable. The
settling time is 8ms (maximum) with the reference
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ADC B
REFDAC1 Bit 10
REFIO1
DAC 1
REFIO2
DAC 2
2.5V
Reference
REFDAC2 Bit 10
Figure 29. Reference Selection Circuit
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DIGITAL
This section reviews the timing and control of the
serial interface.
The ADS8363/7263/7223 offer a set of internal
registers (see the Register Map section for details),
which allows the control of several features and
modes of the device, as Table 5 shows.
Mode Selection Pin M0 and M1
The ADS8363/7263/7223 can be configured to four
different operating modes by using mode pins M0
and M1, as shown in Table 4.
Table 4. M0/M1 Truth Table
M0
M1
CHANNEL
SELECTION
0
0
Manual (through SDI)
SDOA and SDOB
0
1
Manual (through SDI)
SDOA only
1
0
Automatic
SDOA and SDOB
1
1
Automatic
SDOA only
SDOx USED
The M0 pin sets either manual or automatic channel
selection. In Manual mode, CONFIG register bits
C[1:0] are used to select between channels CHx0
and CHx1. In Automatic mode, CONFIG register bits
C[1:0] are ignored and channel selection is controlled
by the device after each conversion. The automatic
channel
selection
is
only
performed
on
fully-differential
inputs
in
this
case;
for
pseudo-differential inputs, the internal sequencer
controls the input multiplexer.
The M1 pin selects between serial data being
transmitted simultaneously on both SDOA and SDOB
outputs for each channel, respectively, or using only
the SDOA output for transmitting data from both
channels (see Figure 34 through Figure 39 and the
associated text for more information).
Additionally, the SDI pin is used for controlling device
functionality through the internal register; see the
Register Map section for details.
Half-Clock Mode (default mode after power-up
and reset)
The ADS8363/7263/7223 power up in half-clock
mode, in which the ADC requires at least 20 CLOCKs
for a complete conversion cycle, including the
acquisition phase. The conversion result can only be
read during the next conversion cycle. The first output
bit is available with the falling RD edge, while the
following output data bits are refreshed with the rising
edge of CLOCK.
Full-Clock Mode (allowing conversion and data
readout within 1µs, supported in dual output
modes)
The full-clock mode allows converting data and
reading the result within 1µs. The entire cycle
requires 40 CLOCKs. The first output bit is available
with the falling RD edge while the following output
data bits are refreshed with the falling edge of the
CLOCK in this mode.
The full-clock mode can only be used with analog
power supply AVDD in the range of 4.5V to 5.5V and
digital supply DVDD in the range of 2.3V to 3.6V. The
internal FIFO is disabled in full-clock mode.
2-Bit Counter
These devices offers a selectable 2-bit counter
(activated using the CE bit in the CONFIG register)
that is a useful feature in safety applications. The
counter value automatically increments whenever a
new conversion result is stored in the output register,
indicating a new value. The counter default value
after power-up is '01' (followed by '10', '11', '00', '01',
and so on), as shown in Figure 31. Because the
counter value increments only when a new
conversion results are transferred to the output
register, this counter is used to verify that the ADC
has performed a conversion and the data read is the
result of this new conversion (not a old result read
multiple times).
Table 5. Supported Operating Modes
INPUT SIGNAL TYPE
MANUAL CHANNEL SELECTION
AUTOMATIC CHANNEL SELECTION
Fully-differential
(PDE bit = '0')
Operating modes: I, II, and special mode II
Channel information selectable through CID bit
FIFO: not available
Operating modes: III, IV and special mode IV
Channel information selectable through CID bit
FIFO: available in mode III and special mode IV;
when used, a single read pulse allows reading of all data
Pseudo-differential
(PDE bit = '1')
Operating modes: I, II and special mode II
Channel information selectable through CID bit
FIFO: not available
Operating modes: III and special mode IV
Channel information not available (CID bit forced to '1')
FIFO: available in mode III and special mode IV;
when used, a single read pulse allows reading of all data
Pseudo-differential sequencer is enabled
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REGISTERS
Register Map
ADS8363/7263/7223 operation is controlled through a set of registers described in the following sections. Table 6
shows the register map. The contents of these 16-bit registers can be set using the serial data input (SDI) pin,
which is coupled to RD and clocked into the device on each falling edge of CLOCK. All data must be transferred
MSB first. All register updates become active with the rising edge of CLOCK after completing the 16-clock-cycle
write access operation.
Table 6. Register Map
REGISTER
CONFIG
REFDAC1
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
C1
C0
R1
R0
0
0
0
0
BIT
3
BIT
2
BIT
1
BIT
0
PD1
PD0
FE
SR
FC
PDE
CID
CE
A3
A2
A1
A0
0
RPD
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
REFDAC2
0
0
0
0
0
RPD
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SEQFIFO
S1
S0
SL1
SL0
C11
C10
C21
C20
C31
C30
C41
C40
SP1
SP0
FD1
FD0
CMB3
CMB2
CMB1
CMB0
CMA3
CMA2
CMA1
CMA0
RB3
RB2
RB1
RB0
RA3
RA2
RA1
RA0
REFCM
To update the CONFIG register, a single write access is required. To update the contents of all the other
registers, a write access to the control register with the appropriate register address (bits A[3:0]), followed by a
write access to the actual register is required (refer to Figure 30). It is possible to update the CONFIG register
contents while issuing a register read out access with a single register write access. For example, it is possible to
change the mode of the device to full-clock mode while activating the REFDAC1 register read access; because
full-clock mode is active upon the 16th clock cycle of the CONFIG register update, the REFDAC1 data are then
presented according to the full-clock mode timing.
To verify the register contents, a read access may be issued using CONFIG register bits A[3:0]. Such access is
described in the Programming the Reference DAC section, based on an example of verifying the reference DAC
register settings. The register contents are always available on SDOA with the next read command. For example,
if the FIFO is used, the register contents are presented after completion of the FIFO read access (see Table 10
for more details). In both cases, a complete read or write access requires a total of 40 clock cycles, during which
a new access to the CONFIG register is not allowed.
CID = ‘1’
20
1
20
1
1
20
1
20
1
20
1
CLOCK
Half-Clock Mode
SEQFIFO register
setting value
SDI
R[1:0]=’01’ → update enabled
A[3:0]=’1001’ → SEQFIFO update
CONVST
and RD
SDOx(1)
conversion n
conversion n + 1
conversion result
n-1
conversion result
n
R[1:0]=’01’ → update enabled
A[3:0]=’1011’ → read SEQFIFO
SDI ignored because a register
read access is ongoing
conversion n + 2
conversion n + 3
conversion result
n+1
SEQFIFO
register value
conversion n + 4
conversion result
n+3
Full-Clock Mode
SEQFIFO register
setting value
SDI
R[1:0]=’01’ → update enabled
A[3:0]=’1001’ → SEQFIFO update
CONVST
and RD
conversion n
conversion result
n
SDOx(1)
(1)
conversion n + 1
conversion result
n+1
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 30. Updating Internal Register Settings
(Example: Half-Clock Mode, CID = '1')
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Configuration (CONFIG) Register
The configuration register selects the input channel, the activation of power-down modes, and the access to the
sequencer/FIFO, reference selection, and reference DAC registers.
Table 7. CONFIG: Configuration Register (default = 0000h)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
C1
C0
Bits[15:14]
R1
R0
PD1
PD0
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FE
SR
FC
PDE
CID
CE
A3
A2
A1
A0
C[1:0]—Input Channel Selection (ADS8361-compatible).
These bits control the multiplexer input selection depending on the status of the PDE bit.
If PDE = '0' (default), the multiplexer is in fully-differential mode and bits C[1:0] control the input multiplexer in the
following manner:
0x = conversion of analog signals at inputs CHx0P/CHx0N (default).
1x = conversion of analog signals at inputs CHx1P/CHx1N.
If PDE = '1', the multiplexer is in pseudo-differential mode and bits C[1:0] control the input multiplexer in the following
manner:
00 = conversion of analog signal at input CHx0 versus the selected CMx or REFIOx (default).
01 = conversion of analog signal at input CHx1 versus the selected CMx or REFIOx.
10 = conversion of analog signal at input CHx2 versus the selected CMx or REFIOx.
11 = conversion of analog signal at input CHx3 versus the selected CMx or REFIOx.
Bits[13:12]
R[1:0]—Configuration register update control.
These bits control the access to the CONFIG register.
00
01
10
11
Bits[11:10]
PD[1:0]—Power-down control.
These bits control the different power-down modes of the device.
00
01
10
11
Bit 9
= If M0 = '0', update of input selection bits C[1:0] only (ADS8361-compatible behavior); if M0 = '1', no action (default).
= Update of the entire CONFIG register content enabled.
= Reserved for factory test; do not use. Changes may result in false behavior of the device.
= If M0 = '0', update of input selection bits C[1:0] only (ADS8361-compatible behavior); if M0 = '1', no action.
= Normal operation (default).
= Device is in power-down mode (see the Power-Down Modes and Reset section for details).
= Device is in sleep power-down mode (see the Power-Down Modes and Reset section for details).
= Device is in Auto-sleep power-down mode (see the Power-Down Modes and Reset section for details).
FE—FIFO enable control.
0 = The internal FIFO is disabled (default).
1 = The internal FIFO is enabled. The depth of the FIFO is controlled by SEQFIFO register bits FD[1:0].
Bit 8
SR—Special read mode control.
0 = Special read mode is disabled (default).
1 = Special read mode is enabled; see Figure 36 and Figure 39 for details.
Bit 7
FC—Full clock mode operation control.
0 = Full-clock mode operation is disabled (default); see Figure 1 for details.
1 = Full-clock mode operation is enabled; see Figure 2 for details.
Bit 6
PDE—Pseudo-differential mode operation enable.
0 = 2 x 2 fully-differential operation (default).
1 = 4 x 2 pseudo-differential operation.
Bit 5
CID—Channel information disable.
0 = The channel information followed by conversion results or register contents are present on SDOx (default).
1 = Conversion data or register content is present on SDOx immediately after the falling edge of RD.
Bit 4
CE—2-bit counter enable (see Figure 31).
0: The internal counter is disabled (default).
1: The counter value is available prior to the conversion result on SDOx (active only if CID = '0').
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Bits[3:0]
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A[3:0]—Register access control.
These bits allow reading of the CONFIG register contents and control the access to the remaining registers of the device.
x000 = Update CONFIG register contents only (default)
0001 = Read CONFIG register content on SDOA with next access (see Figure 30).
x010 = Write to REFDAC1 register with next access (see Figure 30).
0011 = Read REFDAC1 register content on SDOA with next access (see Figure 30).
0100 = Generate software reset of the device.
x101 = Write to REFDAC2 register with next access (see Figure 30).
0110 = Read REFDAC2 register content on SDOA with next access (see Figure 30).
x111 = Update CONFIG register contents only.
1001 = Write to SEQFIFO register with next access (see Figure 30).
1011 = Read SEQFIFO register content on SDOA with next access (see Figure 30).
1100 = Write to REFCM register with next access (see Figure 30).
1110 = Read REFCM register content on SDOA with next access (see Figure 30).
CS
20
1
1
20
1
20
1
20
1
20
1
CLOCK
CONVST
RD
SDI
R[1:0]=’01’ → register update
CE = ‘1’
conversion n
of both CHx0
BUSY
C
H
x
SDOx(1)
(1)
R[1:0]=’11’ → no update
conversion n+1
of both CHx1
16bit data n-1
CHxx
16bit data n
CHx0
R[1:0]=’00’ → no update
conversion n+2
of both CHx1
16bit data n+1
data CHx1
R[1:0]=’00’ → no update
conversion n+3
of both CHx0
16bit data n+2
CHx1
R[1:0]=’00’ → no update
conversion n+4
both CHx0
16bit data n+3
CHx0
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 31. 2-Bit Counter Feature
(Half-Clock Mode, Manual Channel Control, CID = '0')
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REFDAC1 and REFDAC2 Registers
Two reference DAC registers allow for enabling and setting up the appropriate value for each of the output string
DACs that are connected to the REFIO1 and REFIO2 pins.
Table 8. REFDAC1 Control Register (default = 07FFh)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
0
0
0
0
RPD
Bits[15:11]
Not used; always set to '0'.
Bit 10
RPD—DAC1 power down.
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0 = Internal reference path 1 is enabled and the reference voltage is available at the REFIO1 pin.
1 = The internal reference path is disabled (default).
Bits[9:0]
D[9:0]—DAC1 setting bits.
These bits correspond to the settings of the internal reference DACs (compare REFIO section). The D9 bit is the MSB
value of the DAC.
Default value is 1FFh (2.5V nom)
Table 9. REFDAC2 Control Register (default = 07FFh)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
0
0
0
0
RPD
Bits[15:11]
Not used; always set to '0'.
Bit 10
RPD—DAC2 power down.
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0 = Internal reference path 2 is enabled and the reference voltage is available at the REFIO2 pin.
1 = The internal reference path is disabled (default).
Bits[9:0]
D[9:0]—DAC2 setting bits.
These bits correspond to the settings of the internal reference DACs (compare REFIO section). The D9 bit is the MSB
value of the DAC.
Default value is 1FFh (2.5V nom)
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Sequencer/FIFO (SEQFIFO) Register
The ADS8363/7363/7223 feature a programmable sequencer that controls the switching of the ADC input
multiplexer in pseudo-differential, automatic channel-selection mode only. When used, a single read pulse allows
reading of all stored conversion data. A single CONVST is required to control the conversion of the entire
sequence. If the sequencer is used, CONVST and RD must be controlled independently (see Figure 32 and
Figure 33).
Additionally, a programmable FIFO is available on each channel that allows for storing up to four conversion
results. Both features are controlled using this register. If FIFO is used, CONVST and RD must be controlled
independently. Note that after activation of this feature, the FIFO should be full before being read for the first
time.
If the FIFO is full and a new conversion starts, the contents are shifted by one while the oldest result is lost. Only
when the sequencer is used are the entire FIFO contents lost (that is, all bits are automatically set to '0'). The
FIFO can be used independently from the sequencer. When both are used, the complete sequence must be
finished before reading the data out of the FIFO; otherwise, the data may be corrupted.
Table 10 contains details of the data readout requirements depending on the FIFO settings in automatic channel
selection mode.
Table 10. Conversion Result Read Out in FIFO Mode
AUTOMATIC CHANNEL SELECTION
INPUT SIGNAL TYPE
FE = '0'
FE = '1'
Fully-differential input
mode
Read cycle length = 1 word
One RD pulse required after each conversion
Read cycle length = 2 · FIFO length
One RD pulse required for the entire FIFO content
Pseudo-differential input
mode
Read cycle length = 1 word
One RD pulse required after each conversion or after
completing the sequence if S1 = '1' and S0 = '1'
Read cycle length = 2 · sequencer length · FIFO
length
One RD pulse required for the entire FIFO content
Table 11. SEQFIFO: Sequencer and FIFO Register (default = 0000h) (1)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
S1
(1)
S0
SL1
SL0
C11
C10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
C21
C20
C31
C30
C41
C40
SP1
SP0
FD1
FD0
The sequencer is used in pseudo-differential mode only; this register should be set before setting the REFCM register.
Bits[15:14]
S[1:0]—Sequencer mode selection (see Figure 32) in pseudo-differential mode only.
These bits allow for the control of the number of CONVSTs required, and the behavior of the BUSY pin in Sequencer
mode.
0x = An individual CONVST is required with BUSY indicating each conversion (default).
10 = A single CONVST is required for the entire sequence with BUSY indicating each conversion (half-clock mode only).
11 = A single CONVST is required for the entire sequence with BUSY remaining high throughout the sequence
(half-clock mode only)
Bits[13:12]
SL[1:0] Sequencer length control.
These bits control the length of a sequence. Bits [11:6] are only active if SL > '00'.
00 = Do not use; use Mode I or II instead, where M0 = '0' (default).
01 = Sequencer length = 2; C1x (bits[11:10]) and C2x (bits[9:8]) define the actual channel selection.
10 = Sequencer length = 3; C1x (bits[11:10]), C2x (bits[9:8]) and C3x (bits[7:6]) define the actual channel selection.
11 = Sequencer length = 4; C1x (bits[11:10]), C2x (bits[9:8]), C3x (bits[7:6]), and C4x (bits[5:4]) define the actual channel
selection.
Bits[11:10]
C1[1:0]—First channel in sequence selection bits.
Bits[9:8]
C2[1:0]—Second channel in sequence selection bits.
Bits[7:6]
C3[1:0]—Third channel in sequence selection bits.
Bits[5:4]
C4[1:0]—Fourth channel in sequence selection bits.
Bits [11:4] control the pseudo-differential input multiplexer channel selection in sequencer mode.
00
01
10
11
24
= CHA0
= CHA1
= CHA2
= CHA3
and CHB0
and CHB1
and CHB2
and CHB3
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are
are
are
are
selected for
selected for
selected for
selected for
the
the
the
the
next
next
next
next
conversion (default).
conversion.
conversion.
conversion.
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Bits[3:2]
SP[1:0]—Sequence position bits (read only).
These bits indicate the setting of the pseudo-differential input multiplexer in sequencer mode.
00
01
10
11
Bits [1:0]
= Inputs selected using bits
= Inputs selected using bits
= Inputs selected using bits
= Inputs selected using bits
C1[1:0] are
C2[1:0] are
C3[1:0] are
C4[1:0] are
converted
converted
converted
converted
with next
with next
with next
with next
rising edge of CONVST (default).
rising edge of CONVST.
rising edge of CONVST.
rising edge of CONVST.
FD[1:0]—FIFO depth control (see Figure 33).
These bits control the depth of the internal FIFO if CONFIG register bit FE = '1'.
00
01
10
11
= One conversion result per channel is stored in the FIFO for burst read access (default).
= Two conversion results per channel are stored in the FIFO for burst read access.
= Three conversion results per channel are stored in the FIFO for burst read access.
= Four conversion results per channel are stored in the FIFO for burst read access .
S1 = ‘0’
CONVST
BUSY
CONVERSION 1
CONVERSION 2
CONVERSION 3
CONVERSION 2
CONVERSION 3
CONVERSION 2
CONVERSION 3
S1 = ‘1’, S0 = ‘0’ (half-clock mode only)
CONVST
BUSY
CONVERSION 1
S1 = ‘1’, S0 = ‘1’ (half-clock mode only)
CONVST
BUSY
CONVERSION 1
Figure 32. Sequencer Modes
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FD[1:0] = ‘01’, SL[1:0] = ‘00’
…
CONVST
BUSY
Conversion 1
…
Conversion 2
…
RD
…
CONV1 CONV2
SDOx
(2x16 clock cycles)
FD[1:0] = ‘01’, SL[1:0] = ‘10’
…
CONVST
BUSY
1.CHx2
1.CHx1
1.CHx0
2.CHx2
2.CHx1
2.CHx0
CHx1+
…
…
RD
1.CHx2 1.CHx1 1.CHx0 2.CHx2 2.CHx1 2.CHx0
SDOx
…
(6x16 clock cycles)
Figure 33. FIFO and Sequencer Operation Example
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Reference and Common-Mode Selection (REFCM) Register
To allow flexible adjustment of the common-mode voltage in pseudo-differential mode while simplifying the circuit
layout, the ADS8363/7263/7223 provide this register to assign one of the CMx inputs as a reference for each of
the input signals. According to the register settings, the CMx signals are internally connected to the appropriate
negative input of each ADC.
Additionally, this register also allows for the flexible assignment of one of the internal reference DAC outputs as a
reference for each channel in both fully- and pseudo-differential modes.
Table 12. REFCM: Reference and Common-Mode Selection Register (default = 0000h) (1)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
CMB3
CMA1
CMA0
RB3
RB2
RB1
RB0
RA3
RA2
RA1
RA0
(1)
CMB2
CMB1
CMB0
CMA3
CMA2
This register should be set after setting the SEQFIFO register.
Bits[15:8]
CMxx—Common-mode source selection bits (per input channel).
These bits allow selection of the CMx input pins or the internal reference source as common-mode for pseudo-differential
inputs B[3:0] and A[3:0]. The selected signal is connected to the negative input of the corresponding ADC.
0 = external common-mode source through CMx (default).
1 = internal common-mode source = REFIOx, depending on settings of bits Rx[3 :0].
Bit 7
RB3—Internal reference DAC output selection for CHB3 in pseudo-differential mode, or channel CHB1P/N in
fully-differential mode.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
Bit 6
RB2—Internal reference DAC output selection for CHB2 in pseudo-differential mode only.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
Bit 5
RB1—Internal reference DAC output selection for CHB1 in pseudo-differential mode only.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
Bit 4
RB0—Internal reference DAC output selection for CHB0 in pseudo-differential mode, or channel CHB0P/N in
fully-differential mode.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
Bit 3
RA3—Internal reference DAC output selection for CHA3 in pseudo-differential mode, or channel CHA1P/N in
fully-differential mode.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
Bit 2
RA2—Internal reference DAC output selection for CHA2 in pseudo-differential mode only.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
Bit 1
RA1—Internal reference DAC output selection for CHA1 in pseudo-differential mode only.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
Bit 0
RA0—Internal reference DAC output selection for CHA0 in pseudo-differential mode, or channel CHA0P/N in
fully-differential mode.
0 = internal reference source REFIO1 selected (default).
1 = internal reference source REFIO2 selected.
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READ DATA INPUT (RD)
The RD input is used to control serial data outputs
SDOx. The falling edge of the RD pulse triggers the
output of the first bit of the output data. When CID =
'0' this is the analog input channel indicator; when
CID = '1', this is the MSB of the conversion result, or
the 15th bit of the selected register, followed by
output bits that are updated with the rising edge of
the CLOCK in half-clock mode, or falling edge of the
CLOCK in full-clock mode.
The RD input can be controlled separately or in
combination with the CONVST input (see Figure 43
for a detailed timing diagram of this case). If RD is
controlled separately, it can be issued whenever a
conversion process has been finished (that is, after
the falling edge of BUSY). However, in order to
achieve the maximum data rate, the conversion
results must be read during an ongoing conversion.
In this case, the RD pulse should not be issued
between the 16th and 19th clock cycle in half-clock
mode, or between the 34th and 36th clock cycle in
full-clock mode, after starting the conversion.
Note that in full-clock mode, only the first read access
delivers the correct channel information (if CID = '0' in
the CONFIG register), while the following readouts
contain invalid channel details. The channel
information is corrected with the next conversion.
Read access to verify the content of the internal
registers is described in the Register Map section.
SERIAL DATA OUTPUTS (SDOx)
The following sections explain the different modes of
operation in detail.
The
digital
output
code
format
of
the
ADS8363/7263/7223 is binary twos complement, as
shown in Table 13.
Consider both detailed timing diagrams (Figure 1 and
Figure 2) shown in the Timing Diagrams section. For
maximum data throughput, the description and
diagrams given in this data sheet assume that the
CONVST and RD pins are tied together; see
Figure 43 for timing details in this case. Note that
these pins can also be controlled independently.
If a read access is repeated without issuing a new
conversion, the result of the last conversion is
presented on the output(s) again. A repeated readout
should only be performed when BUSY is low.
Table 13. Output Data Format
DESCRIPTION
Positive full-scale
DIFFERENTIAL
INPUT VOLTAGE
VREF
Midscale
0V
Midscale – 1LSB
–VREF/resolution
Negative full-scale
28
–VREF
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INPUT VOLTAGE AT CHxxP
(CHxxN = VREF = 2.5V)
BINARY CODE
HEXADECIMAL
CODE
ADS8363: 0111 1111 1111 1111
7FFF
ADS7263: 0111 1111 1111 1100
7FFC
ADS7223: 0111 1111 1111 0000
7FF0
2.5V
0000 0000 0000 0000
0000
ADS8363: 2.499924V
ADS8363: 1111 1111 1111 1111
FFFF
ADS7263: 2.499847V
ADS7263: 1111 1111 1111 1100
FFFC
ADS7223: 2.499390V
ADS7223: 1111 1111 1111 0000
FFF0
0V
1000 0000 0000 0000
8000
5V
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Mode I
With the M0 and M1 pins both set to '0', the device
enters manual channel-control operation and outputs
data on both SDOA and SDOB, accordingly. The SDI
pin can be used to switch between the channels, as
explicitly shown in the corresponding timing
diagrams. A conversion is initiated by bringing
CONVST high.
With the rising edge of CONVST, the device switches
asynchronously to the external CLOCK from sample
to hold mode, and the BUSY output pin goes high
and remains high for the duration of the conversion
cycle. On the falling edge of the second CLOCK
cycle, the device latches in the channel for the next
conversion cycle, depending on the status of
This mode
can
be
used
for
fullyor
pseudo-differential inputs; in both cases, channel
information bits are '00' if CID = '0'. Note that FIFO is
not available in this mode.
20
1
20
1
1
CONFIG register bits C[1:0]. CS must be brought low
to enable both serial outputs. Data are valid on the
falling edge of every 20 clock cycles per conversion.
The first two bits are set to '0'. The subsequent data
contain the 16-, 14-, or 12-bit conversion result (the
most significant bit is transferred first), with trailing
zeroes, as shown in Figure 34.
20
1
20
1
20
1
CLOCK
Half-Clock Mode
SDI
C[1:0]=’00’ → CHx0 next
R[1:0]=’00’ → no update
C[1:0]=’11’ → CHx1 next
R[1:0]=’11’ → no update
C[1:0]=’11’ → CHx1 next
R[1:0]=’11’ → no update
conversion n - 1
of both CHxx
conversion n
of both CHx0
conversion n + 1
of both CHx1
C[1:0]=’00’ → CHx0 next
R[1:0]=’00’ → no update
C[1:0]=’00’ → CHx0 next
R[1:0]=’00’ → no update
CONVST
and RD
BUSY
SDOx(1)
16-bit data n - 1
CHxx
16-bit data n - 2
CHxx
16-bit data n
CHx0
conversion n + 2
of both CHx1
16-bit data n + 1
CHx1
conversion n + 3
of both CHx0
16-bit data n + 2
CHx1
Full-Clock Mode
SDI
C[1:0]=’00’ → CHx0 next
R[1:0]=’00’ → no update
C[1:0]=’11’ → CHx1 next
R[1:0]=’11’ → no update
CONVST
and RD
BUSY
conversion n - 1
of both CHxx
16-bit data n - 1
CHxx
SDOx(1)
(1)
conversion n
of both CHx0
conversion n + 1
of both CHx1
16-bit data n
CHx0
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 34. Mode I Timing
(M0 = '0', M1 = '0', PDE = '0', CID = '1', Fully-Differential Example)
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Mode II (Half-Clock Mode Only)
With M0 = '0' and M1 = '1', the ADS8363/7263/7223
also operate in manual channel-control mode and
output data on the SDOA pin only while SDOB is set
to high impedance. All other pins function in the same
manner as they do in Mode I.
In half-clock mode, because it takes 40 clock cycles
to output the results from both ADCs (instead of 20
cycles if M1 = '0'), the device requires 2.0ms to
perform a complete read cycle. If the CONVST signal
is issued every 1.0ms (required for the RD signal) as
in Mode I, every second pulse is ignored, as shown in
Figure 35. CONVST and RD signals must not be
longer than one clock cycle to ensure proper
functionality and avoid corruption of output data.
Full-clock mode is not supported in this operational
mode.
20
1
1
The output data consist of a '0', followed by an ADC
indicator ('0' for CHAx or '1' for CHBx), and then 16,
14, or 12 bits of conversion result along with any
trailing zeroes.
This mode
can
be
used
for
fullyor
pseudo-differential inputs. Channel information is
valid in fully-differential mode only if CID = '0' (it
contains correct ADC information while the channel
bit is invalid in pseudo-differential mode). Note that
FIFO is not available in this mode.
Changes to register bits FE, SR, PDE, and CID are
active with the start of the next conversion; this is
with a delay of one read access.
The register settings should be updated using every
other RD pulse, aligned either with the one starting
the conversion or the one to read the conversion
results of channel B, as shown in Figure 35.
20
1
20
1
20
1
20
1
CLOCK
SDI
C[1:0] = ‘00’ → CHx0/CMx
R[1:0] = ‘00’ → no update
C[1:0] are ignored
R[1:0] = ‘00’ → no update
CONVST
and RD
SDOA(1)
(1)
C[1:0] are ignored
R[1:0] = ‘11’ → no update
every 2nd CONVST
is ignored
M[1:0] = ‘00’
BUSY
C[1:0] = ‘01’ → CHx1/CMx
R[1:0] = ‘11’ → no update
C[1:0]=’10’ → CHx2/CMx
R[1:0]=’00’ → no update
every 2nd CONVST
is ignored
M[1:0] = ‘10’
conversion n - 1
of both CHx0
16-bit data n - 2
CHA0
no conversion
read access only
conversion n
of both CHx0/CMx
A
D
B
16-bit data n - 1
CHB0
A
D
A
16-bit data n
CHA0/CMA
conversion n + 1
of both CHx1
A
D
B
16-bit data n
CHB0/CMB
no conversion
read access only
A
D
A
16-bit data n + 1
CHA1/CMA
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 35. Mode II Timing
(M0 = '0', M1 = '1', PDE = '0', CID = '0', Pseudo-Differential Example)
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Special Read Mode II (Half-Clock Mode Only)
For Mode II, a special read mode is available in the
ADS8363/7263/7223 where both data results can be
read out triggered by a single RD pulse (refer to
Figure 36). To activate this mode, The SR bit in the
CONFIG register must be set to '1' (see Table 6). The
CONVST and RD pins can still be tied together but
are issued every 40 CLOCK cycles instead of 20.
Output data are presented on SDOA only while
SDOB is held in 3-state.
This special mode can be used for fully- or
pseudo-differential inputs. Channel information is
valid in fully-differential mode only if CID = '0' (it
contains correct ADC information while the channel
bit is invalid in pseudo-differential mode). Note that
FIFO is not available in this mode.
20
1
20
1
1
The RD signal in this mode must not be longer than
one clock cycle to avoid corruption of output data.
20
1
20
1
20
1
CLOCK
SDI
C[1:0] = ‘11’ → CHx1 next
C[1:0] = ‘00’ → CHx0 next
R[1:0] = ‘01’ → register update R[1:0] = ‘11’ → no update
→ SR = ‘1’
C[1:0] = ‘00’ → CHx0 next
R[1:0] = ‘00’ → no update
CONVST
and RD
SDOA(1)
A
D
x
16-bit data n - 2
CHAx
SDOB(1)
A
D
x
16-bit data n - 2
CHBx
(1)
no conversion,
read access only
conversion n
of both CHx0
conversion n-1
of both CHxx
BUSY
A
D
x
16-bit data n - 1
CHBx
A
D
A
16-bit data n
CHA0
no conversion,
read access only
conversion n + 1
of both CHx1
A
D
B
16-bit data n
CHB0
A
D
A
16-bit data n + 1
CHA1
High-Z
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 36. Special Read Mode II Timing Diagram
(M0 = '0', M1 = '1', PDE = '0', SR = '1', CID = '0', Fully-Differential Example)
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Mode III
This mode
can
be
used
for
fullyor
pseudo-differential inputs (in pseudo-differential mode
the sequencer is used to control the input
multiplexer). Channel information is available in
fully-differential mode only if CID = '0' (CID is forced
to '1' in pseudo-differential mode).
With M0 = '1' and M1 = '0', the device automatically
cycles between the differential inputs (CONFIG
register bits C[1:0] are ignored) while offering the
conversion result of CHAx on SDOA and the
conversion result of CHBx on SDOB, as shown in
Figure 37.
The internal FIFO is available in this mode; when
used, a single read pulse allows for reading of all
stored conversion data. The FIFO should be
completely filled when used for the first time in order
to ensure proper functionality.
Output data consist of a channel indicator ('0' for
CHx0, or '1' for CHx1), followed by a '0', and then 16,
14, or 12 bits of conversion result along with any
trailing zeroes.
20
1
20
1
1
20
1
20
1
20
1
CLOCK
M1
M0
Half-Clock Mode
CONVST
and RD
conversion n - 1
of both CHxx
BUSY
SDOx
(1)
C
H
x
conversion n
of both CHx0
16-bit data n - 2
CHxx
C
H
x
16-bit data n - 1
CHxx
conversion n + 1
of both CHx1
C
H
0
16-bit data n
CHx0
conversion n + 2
of both CHx0
C
H
1
16-bit data n + 1
CHx1
conversion n + 3
of both CHx1
C
H
0
16-bit data n + 2
CHx0
Full-Clock Mode
CONVST
and RD
BUSY
SDOx
(1)
conversion n - 1
of both CHxx
C
H
x
(1)
conversion n + 1
of both CHx1
conversion n
of both CHx0
16-bit data n - 1
CHxx
C
H
0
16-bit data n
CHx0
C
H
1
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 37. Mode III Timing
(M0 = '1', M1 = '0', PDE = '0', CID = '0', Fully-Differential Example)
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Fully-Differential Mode IV (Half-Clock Mode Only)
In the same way as Mode II, Mode IV uses the SDOA
output line exclusively to transmit data while the
differential channels are switched automatically.
Following the first conversion after M1 goes high, the
SDOB output 3-states, as shown in Figure 38.
Output data consist of a channel indicator ('0' for
CHx0, or '1' for CHx1), followed by the ADC indicator
('0' for CHAx or '1' for CHBx), and then 16 or 14 bits
of conversion result, ending with '00' for the
ADS8363, '0000' for the ADS7263, or '000000' for the
ADS7223.
CONVST and RD signals must not be longer than
one clock cycle to ensure proper functionality and
avoid corruption of output data.
20
1
1
Full-clock mode is not supported in this operational
mode.
Channel information is available in fully-differential
mode if CID = '0'. In pseudo-differential mode, the
sequencer controls the channel selection in this mode
and must be set appropriately using the SEQFIFO
register. The internal FIFO is not available in this
mode.
Changes to CONFIG register bits FE, SR, PDE, and
CID are active with the start of the next conversion
with a delay of one read access.
The register settings should be updated using every
other RD pulse (aligned either with the one starting
the conversion or the one to read the conversion
results of channel B; compare with Figure 35).
20
1
20
1
20
1
20
1
CLOCK
M0
M1
CONVST
and RD
every 2nd CONVST
is ignored
SDOA(1)
(1)
CA
HD
xA
16-bit data n - 2
CHAx
no conversion
read access only
Conversion n
of both CHx0
no conversion
read access only
BUSY
every 2nd CONVST
is ignored
CA
HD
xB
16-bit data n - 1
CHBx
CA
HD
0A
16-bit data n
CHA0
Conversion n + 1
of both CHx1
CA
HD
0B
16-bit data n
CHB0
no conversion
read access only
CA
HD
1A
16-bit data n + 1
CHA1
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 38. Fully-Differential Mode IV Timing
(M0 = '1', M1 = '1', PDE = '0', and CID = '0' Example)
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Special Mode IV (Half-Clock Mode Only)
If auto-sleep power-down mode is enabled, the
conversion results are presented during the next
conversion, as shown in Figure 39.
As with Special Mode II, these devices also offer a
special read mode for Mode IV, where both data
results of a conversion can be read by triggering a
single RD pulse (refer to Figure 39). Additionally, in
this case, the SR bit in the CONFIG register must be
set to '1' while the CONVST and RD pins can still be
tied together, but are issued every 40 CLOCK cycles
instead of 20. The RD signal in this mode must not
be longer than one clock cycle to avoid corruption of
output data.
This mode
can
be
used
for
fullyor
pseudo-differential
inputs
(note
that
in
pseudo-differential mode, the sequencer is used to
control the input multiplexer); channel information is
available if CID = '0' in fully-differential mode only
(CID forced to '1' in pseudo-differential mode).
The internal FIFO is available in this mode; when
used, a single read pulse allows for reading of all
stored conversion data. The FIFO should be
completely filled when used for the first time in order
to ensure proper functionality.
Data are available on the SDOA pin, accordingly.
20
1
20
1
1
20
1
20
1
20
1
CLOCK
SDI
C[1:0] are ignored
R[1:0] = ‘00’ → no update
C[1:0] are ignored
C[1:0] are ignored
R[1:0] = ‘01’ → register update R[1:0] = ‘11’ → no update
→ SR = ‘1’
CONVST
and RD
conversion n - 1
of both CHxx
BUSY
SDOA(1)
CA
HD
xx
16-bit data n - 2
CHAx
SDOB(1)
CA
HD
xx
n - 2 16-bit
data CHBx
SDOA(1)
CA
HD
xx
16-bit data n - 2
CHAx
SDOB(1)
CA
HD
xx
16-bit data n - 2
CHBx
no conversion,
read access only
conversion n
of both CHx0
CA
HD
xx
16-bit data n - 1
CHBx
CA
HD
0A
16-bit data n
CHA0
no conversion,
read access only
conversion n + 1
of both CHx1
CA
HD
0B
16-bit data n
CHB0
CA
HD
1A
16-bit data n + 1
CHA1
CA
HD
0A
16-bit data n
CHA0
High-Z
Auto-Sleep Mode
(1)
CA
HD
xx
16-bit data n - 1
CHBx
CA
HD
0B
16-bit data n
CHB0
High-Z
ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 39. Special Read Mode IV Timing
(M0 = '1', M1 = '1', PDE = '0', SR = '1', CID = '0', Fully-Differential Example)
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PROGRAMMING THE REFERENCE DAC
When channel information is enabled (CID = '0'), the
first two bits of the data output contain the currently
selected analog input channel indicator ('0' for CHx0
or '1' for CHx1), followed by the 16-bit DAC register
contents and an additional '00'. While the register
contents are valid on SDOA, the conversion result of
channel Ax is lost (if a conversion was performed in
parallel), the conversion result of channel Bx is valid
on SDOB (if enabled), and data on SDI are ignored,
as shown in Figure 40).
The internal reference DACs can be set by issuing an
RD pulse while providing an control word with R[1:0]
= '01' and A[3:0] = 'X010' or 'X101', depending on
which DAC is going to be updated. Thereafter, a
second RD pulse must be generated with a control
word that starts with the first five bits being ignored
followed by the reference power control and the
corresponding 10-bit DAC value (refer to Figure 40).
To verify the DACs settings, an RD pulse must be
generated while providing a control word containing
R[1:0] = '01' and A[3:0] = '0011' or '0110' to initialize
the read access of the appropriate DAC register.
Triggering the RD line again causes the SDOA output
to provide the 16-bit DAC register value followed by
'0000', if channel information is disabled (CID = '1').
CID = ‘0’
20
1
1
The default value of the DAC registers after power-up
is 7FFh, corresponding to a disabled reference
voltage of 2.5V on both REFIOx pins.
20
1
20
1
20
20
1
CLOCK
Half-Clock Mode
CONVST
and RD
conversion n
BUSY
SDI
CC
1 0
conversion n + 1
SFPCC
RCD I E
ED
R[1:0] = ‘01’ → CR update
A[3:0] = ‘x010’ → REFDAC1
update
SDOA(1)
C
H
x
16-bit data n - 1
CHAx
12-bit data
DAC settings
RPD = ‘1’ → REFDAC1
enabled
C
H
x
16-bit data n
CHAx
conversion n + 2
CC
1 0
conversion n + 3
SFPCC
RCD I E
ED
conversion n + 4
new settings
ignored
R[1:0] = ‘01’ → CR update
A[3:0] = ‘0011’ → read
REFDAC1
C
H
x
16-bit data n + 1
CHAx
C
H
x
16-bit REFDAC1
register content
C
H
x
16-bit data n + 3
CHAx
Full-Clock Mode
CONVST
and RD
BUSY
SDI
(Write)
conversion n
conversion n + 1
CC
1 0
SFPCC
RCD I E
ED
R[1:0] = ‘01’ → CR update
A[3:0] = x010’ → REFDAC1 update
SDI
(Read)
CC
1 0
conversion n + 2
12-bit REFDAC1
register contents
RPD = ‘1’ → REFDAC1 enabled
SFPCC
RCD I E
ED
ignored
R[1:0] = ‘01’ → CR update
A[3:0] = ‘0011’ → read REFDAC1
SDOA(1)
C
H
x
16-bit data n
CHAx
C
H
x
16-bit REFDAC1
register content
C
H
x
Figure 40. DAC Register Write and Read Access Timing
(Both SDOx Active and CID = '0')
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ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
www.ti.com
POWER-DOWN MODES AND RESET
These devices have a comprehensive built-in
power-down feature. There are three power-down
modes: Power-Down, Sleep, and Auto-Sleep
Power-Down. All three power-down modes are
activated with the completion of the write access,
during which the related bit(s) are asserted (PD[1:0]).
All modes are deactivated by deasserting the
respective bit(s) in the CONFIG register. The content
of the CONFIG register is not affected by any of the
power-down modes. Any ongoing conversion is
finished before entering any of the power-down
modes. Table 14 summarizes the differences among
the three power-down modes.
Power-Down Mode
In Power-Down mode (PD[1:0] = '01'), all functional
blocks except the digital interface are disabled. In this
mode, the current demand is reduced to 5µA within
20µs. The wakeup time from Power-Down mode is
8ms when using a reference capacitor of 22µF. The
device goes into Power-Down mode after completing
any ongoing conversions.
Sleep Mode
In Sleep mode (PD[1:0] = '10'), the device reduces its
current demand to approximately 0.9mA within 10µs.
The device goes into Sleep mode after completing
any ongoing conversions.
Auto-Sleep Mode
Auto-Sleep mode is almost identical to Sleep mode.
The only differences are the method of activating the
mode and waking up the device. CONFIG register
bits PD[1:0] = '11' are only used to enable/disable this
feature. If the Auto-Sleep mode is enabled, the
device automatically turns off the biasing after
finishing a conversion; thus, the end of conversion
actually activates Auto-Sleep mode. If Sequencer
mode is used and individual conversion start pulses
are chosen (S1 = '0'), the device automatically
powers-down after each conversion; in case of a
single CONVST pulse starting the sequence (S1 =
'1'), power-down is activated upon completion of the
entire sequence.
The device wakes up with the next CONVST pulse
but the analog input is held in sample mode for
another seven clock cycles in half-clock mode, or 14
clock cycles in full-clock mode, before starting the
actual conversion (BUSY goes high thereafter), as
shown in Figure 41. This time is required to settle the
internal circuitry to the required voltage levels. The
conversion result is delayed in Auto-Sleep mode as
shown in Figure 39.
In this mode, the current demand is reduced to
approximately 1.2mA within 10µs.
Reset
To issue a device reset, an RD pulse must be
generated along with a control word containing A[3:0]
= '0100'. With the completion of this write access, the
entire device including the serial interface is forced
into reset, interrupting any ongoing conversions,
setting the input into acquisition mode, and returning
the register contents to their default values. After
~20ns, the serial interface becomes active again. The
device also supports an automatic power-up reset
(POR) that ensures proper (default) settings of the
device.
Table 14. Power-Down Modes
DELAY TIME
TO
POWERDOWN
NORMAL
OPERATION
BY
WAKEUP
TIME
POWERDOWN
DISABLED BY
Write access
completed
20µs
PD[1:0] = '00'
8ms
PD[1:0] = '00'
PD[1:0] = '10'
Write access
completed
10µs
PD[1:0] = '00'
7 or 14 CLOCK
cycles
PD[1:0] = '00'
PD[1:0] = '11'
Each end of
conversion
10µs
CONVST pulse
7 or 14 CLOCK
cycles
PD[1:0] = '00'
POWERDOWN MODE
POWERDOWN
CURRENT
POWERDOWN
ENABLED BY
POWERDOWN START
BY
Power-Down
5µA
PD[1:0] = '01'
Sleep
1.2mA (3.6V)
Auto-Sleep
1.2mA (3.6V)
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SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
Half-Clock Mode
CLOCK
CONVST
tACQ
BUSY
Auto-Sleep Power-Down
conversion n
7 CLOCKs
conversion n + 1
Full-Clock Mode
CLOCK
CONVST
tACQ
BUSY
Auto-Sleep Power-Down
conversion n
14 CLOCKs
conversion n + 1
Figure 41. Actual Conversion Start in Auto-Sleep Mode
ADS8361 COMPATIBILITY
Pinout
This section describes the differences between the
ADS8361 and the ADS8363/7263/7223 family of
devices in default mode without changing the internal
register settings (that are not available on the
ADS8361).
The ADS8363/7263/7223 family is pin-compatible to
ADS8361IRHB. However, there are some differences
that must be considered when migrating from an
ADS8361-based design, as summarized in Table 15.
Table 15. Pinout Differences Between the ADS8363/7263/7223 and ADS8361
PIN NAME
PIN NO.
ADS8361
ADS8363/7263/7223
IMPACT
9
REFIN
REFIO1
If external reference is used, see the Internal Reference section for details.
If internal reference is used, REFIO1 must be enabled using the RPD bit in the DAC1
register.
10
REFOUT
REFIO2
Because REFIO2 is disabled by default, no adjustment is required.
11
NC
RGND
18
A0
SDI
29
NC
AVDD
This pin should be connected to the analog supply and decoupled with a 1µF capacitor
to ensure proper functionality of the ADS8363/7263/7223 family.
30
NC
AGND
This pin should be connected to the analog ground plane to ensure proper functionality
of the ADS8363/7263/7223 family.
31
NC
CMA
In default mode of the ADS8363 family; no changes required.
32
NC
CMB
In default mode of the ADS8363 family; no changes required.
If external reference is used, no changes required.
If REFIO1 is enabled, this pin should be tied to the analog ground plane with a dedicated
via. Furthermore, a 22µF ceramic capacitor should be used between this pin and pin 9.
See the SDI vs. A0 section for details.
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ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
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SDI versus A0
•
Pin 18 (SDI) of the ADS8363/7263/7223 is used to
update the internal registers, whereas on the
ADS8361, pin 18 (A0) is used in conjunction with M0
to select the input channel.
•
If, in an existing design, the ADS8361 is used in
two-channel mode (M0 = '0') and the status of the A0
pin is unchanged within the first four clock cycles
after issuing a conversion start (rising edge of
CONVST), the ADS8363/7263/7223 act similarly to
the ADS8361 and convert either channels CHx0 (if
SDI is held low during the entire period) or channels
CHx1 (if SDI is held high during the entire period).
Figure
37
shows
the
behavior
of
the
ADS8363/7263/7223 in such a situation.
In the latter case, while the capacitor stabilizes the
reference voltage during the entire conversion, the
buffer must recharge it by providing an average
current only; thus, the required minimum bandwidth of
the buffer can be calculated using Equation 4:
ln(2) × 2
f-3dB =
2p × 20tCLK
(4)
The ADS8363/7263/7223 can be also be used to
replace the ADS8361 when run in four-channel mode
(M0 = '1'). In this case, the A0 pin is held static (high
or low), which is also required in for the SDI pin to
prevent accidental update of the SDI register.
Timing
In both cases described above, the additional
features
of
the
ADS8363/7263/7223
(pseudo-differential input mode, programmable
reference voltage output, and the various
power-down modes) cannot be accessed, but the
hardware
and
software
would
remain
backward-compatible to the ADS8361.
Internal Reference
The internal reference of the ADS8361 delivers 2.5V
(typ) after power up, while the reference output of the
ADS8363/7263/7223 is powered down by default. In
this case, the unbuffered reference input has a
code-dependent input impedance, while the
ADS8361 offers a high-impedance (buffered)
reference input. If an existing ADS8361-based design
uses the internal reference of the device and relies on
an external resistor divider to adjust the input voltage
range of the ADC, migration to the ADS8363 family
requires one of the following conditions:
38
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A software change to setup internal reference
DAC1 properly through SDI while removing the
external resistors; or
An additional external buffer between the resistor
divider and the required 22µF (min) capacitor on
the REFIO1 input.
The buffer must also be capable of driving the 22µF
load while maintaining its stability.
In half-clock mode (default), the ADS8363/7263/7223
family of devices provides the conversion delay after
completion of the conversion (see Figure 1), while the
ADS8361 offers the conversion result during the
conversion process.
RD
The ADS8363/7263/7223 output the first bit with the
falling edge of the RD input. The ADS8361 starts the
data transfer with the first falling edge of the clock if
RD is high.
If the ADS8363/7263/7223 operate with half-clock
timing in modes II and IV, the RD input should not be
held high longer than one clock cycle to ensure
proper function of the data output SDOA.
CONVST
If the ADS8363/7263/7223 operate with half-clock
timing in modes II and IV, the CONVST input must
not be held high longer than one clock cycle to
ensure proper function of the device.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8363 ADS7263 ADS7223
ADS8363
ADS7263
ADS7223
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SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
APPLICATION INFORMATION
MINIMUM CONFIGURATION EXAMPLE
Those values can be calculated using Equation 5:
ln(2)(n + 1)
fFILTER =
2p2RC
An example of a minimum configuration for the
ADS8363/7263/7223 is shown in Figure 42. In this
case, the device is used in dual-channel,
fully-differential input mode with a four-wire digital
interface connected to the controller device and with
default settings of the device after power up. Because
the internal reference is disabled upon power up (to
prevent driving against an external reference if used),
an external reference source is shown in this
example. To allow the use of the internal reference,
the SDI input must be connected to the controller,
allowing access to the REFDAC registers. The
corresponding timing diagram including the timing
requirements are shown in Figure 43 and the Timing
Characteristics table.
Where n = 16 as the resolution of the ADS8363
(n = 14 for ADS7263, n = 12 for ADS7223). (5)
As a good trade-off between required minimum driver
bandwidth and the capacitor value, it is
recommended to use a capacitor value of at least
1nF.
Keeping the acquisition time in mind, the resistor
value can be calculated as shown in Equation 6 for
each of the series resistors:
tACQ
R=
ln(2)(n + 1)2C
The input signal for the amplifiers must fulfill the
common-mode voltage requirements of the device in
this configuration. The actual values of the resistors
and capacitors depend on the bandwidth and
performance requirements of the application.
Where n = the device resolution.
(6)
DGND
AGND
AVDD
DVDD
1mF
1mF
32
31
30
29
28
27
26
25
CMA
AGND
AVDD
DGND
DVDD
NC
SDOA
R
CMB
AVDD
1
CHB1P
SDOB 24
2
CHB1N
BUSY 23
3
CHB0P
4
CHB0N
5
CHA1P
6
CHA1N
CONVST 19
7
CHA0P
SDI 18
8
CHA0N
M0 17
OPA2365
R
CLOCK 22
C
AGND
AVDD
ADS8363
ADS7263
ADS7223
CS 21
RD 20
DGND
Controller
Device
R
R
REFIO2
RGND
AGND
AVDD
NC
NC
M1
OPA2365
REFIO1
C
9
10
11
12
13
14
15
16
AVDD
22mF
AGND
DGND
1mF
DVDD
REF5025
AGND
AGND
AVDD
Figure 42. Four-Wire Application Configuration
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ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
www.ti.com
18
1
21
CLOCK
tCONV
tACQ
tDATA
CS
t1
tH1
t3
CONVST
and RD
conversion n
tD5
tD3
data n - 1
SDOA/B
(ADS8363)
CH
0/1
CH MSB D14 D13 D12 D11 D10
A/B
SDOA/B
(ADS7263)
CH
0/1
CH MSB D12 D11 D10
A/B
D9
D8
SDOA/B
(ADS7223)
CH
0/1
CH MSB D10
A/B
D7
D6
D9
D8
tH3
D7
D6
D5
D4
D3
D2
D5
D4
D3
D2
D1
LSB
D3
D2
D1
LSB
D1
LSB
CH
0/1
CH
A/B
CH
0/1
CH
A/B
CH
0/1
CH
A/B
data n - 1
D7
D6
data n - 1
D9
D8
D5
D4
Figure 43. Four-Wire Application Timing (Half-Clock Mode)
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ADS7263
ADS7223
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SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
LAYOUT
For optimum performance, care should be taken with
the physical layout of the ADS8363/7263/7223
circuitry, particularly if the device is used at the
maximum throughput rate. In this case, it is
recommended to have a fixed phase relationship
between CLOCK and CONVST.
Additionally, the high-performance SAR architecture
is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and
digital inputs that occur just before latching the output
of the internal analog comparator. Therefore, during
an operation of an n-bit SAR converter, there are n
windows in which large external transient voltages
(glitches) can affect the conversion result. Such
glitches might originate from switching power
supplies, nearby digital logic, or high-power devices.
The degree of impact depends on the reference
voltage, layout, and the actual timing of the external
event.
With this possibility in mind, power to the device
should be clean and well-bypassed. A 1µF ceramic
bypass capacitor should be placed at each supply pin
(connected to the corresponding ground pin) as close
to the device as possible.
If the reference voltage is external, the operational
amplifier should be able to drive the 22µF capacitor
without oscillation. A series resistor between the
driver output and the capacitor may be required. To
minimize any code-dependent voltage drop on this
path, a small value should be used for this resistor
(10Ω max). TI's REF50xx family is able to directly
drive such a capacitive load.
GROUNDING
The AGND, RGND, and DGND pins should be
connected to a clean ground reference. All
connections should be kept as short as possible to
minimize the inductance of these paths. It is
recommended to use vias connecting the pads
directly to the ground plane. In designs without
ground planes, the ground trace should be kept as
wide as possible. Avoid connections that are close to
the grounding point of a microcontroller or digital
signal processor.
Depending on the circuit density of the board,
placement of the analog and digital components, and
the related current loops, a single solid ground plane
for the entire printed circuit board (PCB) or a
dedicated analog ground area may be used. In case
of a separated analog ground area, ensure a
low-impedance connection between the analog and
digital ground of the ADC by placing a bridge
underneath (or next) to the ADC (see Figure 44).
Otherwise, even short undershoots on the digital
interface with a value of less than –300mV can lead
to conduction of ESD diodes, causing current flow
through the substrate and degrading the analog
performance.
During the layout of the PCB, care should be taken to
avoid any return currents crossing any sensitive
analog areas or signals. No signal must exceed the
limit of –300mV with respect to the corresponding
(AGND or DGND) ground plane.
SUPPLY
The ADS8363/7263 has two separate supplies: the
DVDD pin for the buffers of the digital interface and
the AVDD pin for all the remaining circuits.
DVDD can range from 2.3V to 5.5V, allowing the
ADC to easily interface with processors and
controllers. To limit the injection of noise energy from
external digital circuitry, DVDD should be properly
filtered. A bypass capacitor of 1µF should be placed
between the DVDD pin and the digital ground plane.
AVDD supplies the internal analog circuitry. For
optimum performance, a linear regulator (for
example, the UA7805 family) is recommended to
generate the analog supply voltage in the range of
2.7V to 5.5V for the ADC and the necessary analog
front-end.
Bypass capacitors of 1µF should be connected to the
analog ground plane such that the current is allowed
to flow through the pad of these capacitors (that is,
the vias should be placed on the opposite side of the
connection between the capacitor and the
power-supply pin of the ADC).
DIGITAL INTERFACE
To further optimize performance of the device, a
series resistor of between 10Ω to 100Ω can be used
on each digital pin of the device. In this way, the slew
rate of the input and output signals is reduced,
limiting the noise injection from the digital interface.
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ADS7263
ADS7223
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to AVDD to DVDD
25
26
DGND
1 mF
AVDD
31
AGND
32
1 mF
DVDD
(Top View)
19
7
18
8
17
22mF
16
6
15
20
14
21
5
AVDD
22
4
AGND
23
3
RGND
2
REFIO2
24
REFIO1
1
1mF
LEGEND
22mF
Top layer: copper pour and traces
Lower layer: AGND area
to AVDD
Lower layer: DGND area
via
Figure 44. Optimized Layout Recommendation
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ADS7263
ADS7223
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SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December, 2010) to Revision B
Page
•
Revised test conditions for gain error parameter .................................................................................................................. 3
•
Revised test conditions for gain error parameter .................................................................................................................. 3
•
Revised test conditions for gain error parameter .................................................................................................................. 4
•
Updated CONVST high time specification .......................................................................................................................... 11
•
Revised CONVST section .................................................................................................................................................. 17
•
Revised Mode II section ..................................................................................................................................................... 30
•
Revised Special Read Mode II section ............................................................................................................................... 31
•
Revised Fully-Differential Mode IV section ......................................................................................................................... 33
•
Revised Special Mode IV section ....................................................................................................................................... 34
•
Added CONVST section in ADS8361 Compatibility ........................................................................................................... 38
Changes from Original (October, 2010) to Revision A
Page
•
Updated Figure 1 .................................................................................................................................................................. 9
•
Added RD high time (t3) parameter to Timing Characteristics table ................................................................................... 11
•
Revised RD section in ADS8361 Compatibility .................................................................................................................. 38
•
Added t3 timing trace to Figure 43 ...................................................................................................................................... 40
•
Deleted Four-Wire Application Timing Requirements table ................................................................................................ 40
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
ADS7223SRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS
7223
ADS7223SRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS
7223
ADS7263SRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS
7263
ADS7263SRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS
7263
ADS8363SRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS8363
ADS8363SRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS8363
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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27-Jul-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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