BB ADS7806P

®
ADS7806
Low-Power 12-Bit Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 35mW max POWER DISSIPATION
● 50µW POWER DOWN MODE
● 25µs max ACQUISITION AND
CONVERSION
● ±1/2LSB max INL AND DNL
● 72dB min SINAD WITH 1kHz INPUT
● ±10V, 0V TO +5V, AND 0V TO +4V INPUT
RANGES
The ADS7806 is a low-power 12-bit sampling analogto-digital using state-of-the-art CMOS structures. It
contains a complete 12-bit, capacitor-based, SAR A/D
with S/H, clock, reference, and microprocessor interface with parallel and serial output drivers.
The ADS7806 can acquire and convert to full 12-bit
accuracy in 25µs max while consuming only 35mW
max. Laser-trimmed scaling resistors provide standard
industrial input ranges of ±10V and 0V to +5V. In
addition, a 0V to +4V range allows development of
complete single supply systems.
The 28-pin ADS7806 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C temperature range.
●
●
●
●
SINGLE +5V SUPPLY OPERATION
PARALLEL AND SERIAL DATA OUTPUT
PIN-COMPATIBLE WITH 16-BIT ADS7807
USES INTERNAL OR EXTERNAL
REFERENCE
● 28-PIN 0.3" PLASTIC DIP AND SOIC
Clock
R/C
CS
BYTE
Power
Down
Successive Approximation Register and Control Logic
40kΩ
CDAC
R1IN
BUSY
Parallel
20kΩ
40kΩ
Serial Data
Clock
and
10kΩ
Comparator
R2IN
Serial
Serial Data
Data
CAP
Out
Parallel Data
Buffer
6kΩ
REF
8
Internal
+2.5V Ref
Reference
Power
Down
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1992 Burr-Brown Corporation
PDS-1158C
Printed in U.S.A. November, 1994
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.
ADS7806P, U
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
ADS7806PB, UB
MAX
MIN
TYP
12
ANALOG INPUT
Voltage Ranges
Impedance
Capacitance
MAX
UNITS
*
Bits
±10, 0 to +5, 0 to +4
(See Table II)
35
THROUGHPUT SPEED
Conversion Time
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise(2)
Gain Error
Full Scale Error(3,4)
Full Scale Error Drift
Full Scale Error(3,4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Unipolar Zero Error(3)
Unipolar Zero Error Drift
Recovery Time to Rated Accuracy
from Power Down(5)
Power Supply Sensitivity
(VDIG = VANA = VS)
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Usable Bandwidth(7)
Full Power Bandwidth (-3dB)
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(8)
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer.)
Internal Reference Drift
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
40
±7
Ext. 2.5000V Ref
Ext. 2.5000V Ref
±10V Range
±10V Range
0V to 5V, 0V to 4V Ranges
0V to 5V, 0V to 4V Ranges
2.2µF Capacitor to CAP
±0.5
±0.5
±0.5
1
±10V
±10V
±10V
±10V
80
70
70
*
*
*
*
±0.1
±0.5
±5
±0.5
90
–90
73
73
130
600
FS Step
±10
2.3
Ext. 2.5000V Ref
±0.45
±0.45
LSB(1)
LSB
Bits
LSB
%
%
ppm/°C
%
ppm/°C
mV
ppm/°C
mV
ppm/°C
ms
2.5
1
8
2.5
±0.25
±0.25
*
±3
*
*
*
*
*
–80
72
72
*
*
*
*
*
*
*
*
*
5
2.48
µs
µs
kHz
*
*
750
No Load
*
*
*
40
20
*
2.52
*
2.7
*
*
*
*
*
100
VIL = 0V
VIH = 5V
Output Capacitance
±0.9
±0.9
±0.5
+4.75V < VS < +5.25V
1kHz,
1kHz,
1kHz,
1kHz,
pF
*
±0.15
±0.15
Guaranteed
0.1
±0.2
–0.3
+2.0
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Leakage Current
*
20
25
Acquire and Convert
fIN =
fIN =
fIN =
fIN =
V
+0.8
VD +0.3V
±10
±10
*
*
*
LSB
dB(6)
dB
dB
dB
kHz
kHz
ns
ps
µs
ns
V
µA
*
ppm/°C
V
*
µA
*
*
*
*
V
V
µA
µA
*
Parallel 12-bits in 2-bytes; Serial
Binary Two’s Complement or Straight Binary
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
VOUT = 0V to VDIG
High-Z State
+0.4
±5
*
V
V
µA
15
*
pF
+4
*
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADS7806
2
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.
ADS7806P, U
PARAMETER
CONDITIONS
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
MIN
ADS7806PB, UB
TYP
MAX
RL = 3.3kΩ, CL = 50pF
RL = 3.3kΩ, CL = 10pF
POWER SUPPLIES
Specified Performance
VDIG
VANA
IDIG
IANA
Power Dissipation
MIN
TYP
83
83
Must be ≤ VANA
+4.75
+4.75
VANA = VDIG = 5V, fS = 40kHz
REFD HIGH
PWRD and REFD HIGH
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
Thermal Resistance (θJA)
Plastic DIP
SOIC
+5
+5
0.6
5.0
28
23
50
–40
–55
–65
+5.25
+5.25
*
*
35
+85
+125
+150
75
75
*
*
*
*
*
*
*
*
*
*
MAX
UNITS
*
*
ns
ns
*
*
V
V
mA
mA
mW
mW
µW
*
*
*
*
*
*
°C
°C
°C
°C/W
°C/W
NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 4.88mV. (2) Typical rms noise at worst case transition. (3) As measured with
fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed
deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5)
This is the time delay after the ADS7806 is brought out of Power Down Mode until all internal settling occurs and the analog input is acquired to rated accuracy.
A Convert Command after this delay will yield accurate results. (6) All specifications in dB are referred to a full-scale input. (7) Usable Bandwidth defined as FullScale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB. (8) Recovers to specified performance after 2 x FS input overvoltage.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
........................................................................... ±25V
........................................................................... ±25V
.................................... VANA +0.3V to AGND2 –0.3V
......................................... Indefinite Short to AGND2,
Momentary Short to VANA
Ground Voltage Differences: DGND, AGND1, and AGND2 ............. ±0.3V
VANA ....................................................................................................... 7V
VDIG to VANA ...................................................................................... +0.3V
VDIG ........................................................................................................ 7V
Digital Inputs .............................................................. –0.3V to VDIG +0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300°C
Analog Inputs: R1IN
R2IN
CAP
REF
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. BurrBrown Corporation recommends that this integrated circuit
be handled and stored using appropriate ESD protection
methods.
ORDERING INFORMATION
MODEL
ADS7806P
ADS7806PB
ADS7806U
ADS7806UB
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
MINIMUM
SIGNAL-TO(NOISE + DISTORTION)
RATIO (dB)
±0.9
±0.45
±0.9
±0.45
70
72
70
72
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
–40°C
–40°C
–40°C
–40°C
Plastic DIP
Plastic DIP
SOIC
SOIC
to
to
to
to
+85°C
+85°C
+85°C
+85°C
PACKAGE INFORMATION
MODEL
PACKAGE
PACKAGE DRAWING
NUMBER(1)
ADS7806P
ADS7806PB
ADS7806U
ADS7806UB
Plastic DIP
Plastic DIP
SOIC
SOIC
246
246
217
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
®
3
ADS7806
DIGITAL
I/O
PIN #
NAME
1
2
3
4
5
6
7
8
9
R1IN
AGND1
R2IN
CAP
REF
AGND2
SB/BTC
EXT/INT
D7
10
11
12
13
14
15
16
17
18
19
20
21
22
D6
D5
D4
D3
DGND
D2
D1
D0
DATACLK
SDATA
TAG
BYTE
R/C
O
O
O
I/O
O
I
I
I
23
CS
I
24
BUSY
O
25
26
27
28
PWRD
REFD
VANA
VDIG
I
I
DESCRIPTION
Analog Input. See Figure 7.
Analog Sense Ground.
Analog Input. See Figure 7.
Reference Buffer Output. 2.2µF tantalum capacitor to ground.
Reference Input/Output. 2.2µF tantalum capacitor to ground.
Analog Ground.
Selects Straight Binary or Binary Two’s Complement for Output Data Format.
External/Internal data clock select.
Data Bit 3 if BYTE is HIGH. Data bit 11 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave
unconnected when using serial output.
Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
LOW if BYTE is HIGH. Data bit 7 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Digital Ground.
LOW if BYTE is HIGH. Data bit 6 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
LOW if BYTE is HIGH. Data bit 5 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
LOW if BYTE is HIGH. Data bit 4 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH.
Serial Output Synchronized to DATACLK.
Serial Input When Using an External Data Clock.
Selects 8 most significant bits (LOW) or 4 least significant bits (HIGH) on parallel output pins.
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same
falling edge will start the transmission of serial data results from the previous conversion.
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active.
REFD HIGH shuts down the internal reference. External reference will be required for conversions.
Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors.
Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA.
I
I
O
O
O
O
O
TABLE I. Pin Assignments.
PIN CONFIGURATION
R1IN
1
28 VDIG
AGND1
2
27 VANA
R2IN
3
26 REFD
CAP
4
25 PWRD
REF
5
24 BUSY
AGND2
6
23 CS
SB/BTC
7
22 R/C
8
21 BYTE
D7
9
20 TAG
D6 10
19 SDATA
D5 11
18 DATACLK
D4 12
17 D0
D3 13
16 D1
DGND 14
15 D2
®
ADS7806
CONNECT R1IN
VIA 200Ω
TO
CONNECT R2IN
VIA 100Ω
TO
IMPEDANCE
±10V
0V to 5V
0V to 4V
VIN
AGND
VIN
CAP
VIN
VIN
45.7kΩ
20.0kΩ
21.4kΩ
TABLE II. Input Range Connections. See also Figure 7.
ADS7806
EXT/INT
ANALOG
INPUT
RANGE
4
TYPICAL PERFORMANCE CURVES
TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 15kHz, 0dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
–60
–80
–60
–80
–100
–100
–120
–120
0
5
10
15
0
20
5
10
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY (fIN = 0dB)
90
90
80
80
0dB
70
60
SINAD (dB)
SINAD (dB)
20
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY AND INPUT AMPLITUDE
70
50
40
60
–20dB
50
40
30
30
20
20
10
–60dB
0
10
100
1k
10k
100k
0
1M
2
4
6
8
10
12
14
16
Input Signal Frequency (Hz)
Input Signal Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE
(fIN = 1kHz, 0dB; fS = 10kHz to 40kHz)
A.C. PARAMETERS vs TEMPERATURE
(fIN = 1kHz, 0dB)
74.0
SFDR, SNR, and SINAD (dB)
30kHz
20kHz
73.9
10kHz
73.8
40kHz
73.7
73.6
–75
18
20
110
–60
105
SINAD (dB)
15
Frequency (kHz)
–65
SFDR
100
–70
95
–75
90
–80
85
–85
80
–90
SNR and SINAD
75
–95
70
–100
THD
65
–105
60
–50
–25
0
25
50
75
Temperature (°C)
100
125
150
THD (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 1kHz, 0dB)
–110
–75
–50
–25
0
25
50
75
100
125
150
Temperature (°C)
®
5
ADS7806
TYPICAL PERFORMANCE CURVES
(CONT)
TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.
POWER SUPPLY RIPPLE SENSITIVITY
INL/DNL DEGRADATION PER LSB OF P-P RIPPLE
1
Linearity Degradation (LSB/LSB)
12-Bit LSBs
0.10
0
All Codes INL
–0.10
0
512
1024
1536
2560
2048
3072
3584
4095
Decimal Code
12-Bit LSBs
0.10
All Codes DNL
10–1
10–2
INL
10–3
10–4
DNL
10–5
0
101
102
103
104
105
106
107
Power Supply Ripple Frequency (Hz)
–0.10
0
512
1024
1536
2560
2048
3072
3584
4095
Decimal Code
BPZ Error
+FS Error
0
–0.20
–FS Error
0
–0.20
–75
–50
0.40
Percent
From Ideal
Percent
From Ideal
0.20
mV From Ideal
0.20
ENDPOINT ERRORS (UNIPOLAR RANGES)
3
2
1
0
–1
–2
Percent
From Ideal
mV From Ideal
Percent
From Ideal
ENDPOINT ERRORS (20V BIPOLAR RANGE)
3
2
1
0
–1
–2
–25
0
25
50
75
100
125
UPO Error
+FS Error (4V Range)
0.20
0
0.40
+FS Error (5V Range)
0.20
0
–75
150
–50
–25
25
50
75
100
125
150
125
150
CONVERSION TIME vs TEMPERATURE
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
2.520
15.10
2.515
15.00
2.510
Conversion Time (µs)
Internal Reference (V)
0
Temperature (°C)
Temperature (°C)
2.505
2.500
2.495
2.490
2.485
14.90
14.80
14.70
14.60
14.50
14.40
14.30
14.20
2.480
–75
–50
–25
0
25
50
75
100
125
–75
150
®
ADS7806
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
6
100
BASIC OPERATION
output valid data from the previous conversion on SDATA
(pin 19) synchronized to 12 clock pulses output on
DATACLK (pin 18). BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the serial data
has been transmitted. Data will be output in Binary Two’s
Complement format, MSB first, and will be valid on both the
rising and falling edges of the data clock. BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
PARALLEL OUTPUT
Figure 1a) shows a basic circuit to operate the ADS7806
with a ±10V input range and parallel output. Taking R/C
(pin 22) LOW for 40ns (12µs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay LOW until the
conversion is completed and the output register is updated.
If BYTE (pin 21) is LOW, the 8 most significant bits will be
valid when BUSY rises; if BYTE is HIGH, the 4 least
significant bits will be valid when BUSY rises. Data will be
output in Binary Two’s Complement format. BUSY going
HIGH can be used to latch the data. After the first byte has
been read, BYTE can be toggled allowing the remaining
byte to be read. All convert commands will be ignored while
BUSY is LOW.
The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibration section).
The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal.
STARTING A CONVERSION
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibration section).
The combination of CS (pin 23) and R/C (pin 22) LOW for
a minimum of 40ns immediately puts the sample/hold of the
ADS7806 in the hold state and starts conversion ‘n’. BUSY
(pin 24) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be
ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient time to acquire a new signal.
SERIAL OUTPUT
Figure 1b) shows a basic circuit to operate the ADS7806
with a ±10V input range and serial output. Taking R/C (pin
22) LOW for 40ns (12µs max) will initiate a conversion and
Serial Output
Parallel Output
200Ω
200Ω
±10V
1
28
2
27
3
26
4
2.2µF
+ 5
25
66.5kΩ
100Ω
2.2µF
+5V
+
0.1µF 10µF
+
+
±10V
+5V
66.5kΩ
+5V
100Ω
BUSY
24
6
Convert Pulse
23
2.2µF
R/C
7
22
ADS7806
Pin 21 B11 B10
LOW (MSB)
B9
Pin 21
HIGH
B1
B3
B2
B8
B7
B0 LOW
(LSB)
28
2
27
3
26
4
25
5
24
6
23
0.1µF 10µF
+
+
21
9
20
10
19
11
18
12
17
13
16
7
40ns min
Convert Pulse
22
8
21
9
20
NC(1) 10
19
NC(1)
15
B5
R/C
ADS7806
NC(1)
B6
+5V
BUSY
BYTE
8
14
+
2.2µF
+
1
NC(1) 11
18
NC(1) 12
17 NC(1)
NC(1) 13
16 NC(1)
14
15 NC(1)
40ns min
SDATA
DATACLK
B4
LOW LOW LOW
NOTE: (1) These pins should be left
unconnected.They will be active when
R/C is HIGH.
NOTE: (1) SDATA (pin 19) is always active.
FIGURE 1b. Basic ±10V Operation with Serial Output.
FIGURE 1a. Basic ±10V Operation, both Parallel and Serial
Output.
®
7
ADS7806
The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. Refer to
Tables III and IV for a summary of CS, R/C, and BUSY
states and Figures 2 through 6 for timing diagrams.
CS
R/C
BUSY
1
X
X
None. Databus is in Hi-Z state.
↓
0
1
Initiates conversion “n”. Databus remains
in Hi-Z state.
0
↓
1
Initiates conversion “n”. Databus enters Hi-Z
state.
0
1
↑
Conversion “n” completed. Valid data from
conversion “n” on the databus.
↓
1
1
Enables databus with valid data from
conversion “n”.
↓
1
0
Enables databus with valid data from
conversion “n-1”(1). Conversion n in progress.
0
↑
0
Enables databus with valid data from
conversion “n-1”(1). Conversion “n” in progress.
0
0
↑
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
X
X
0
New convert commands ignored. Conversion
“n” in progress.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input. If EXT/INT
(pin 8) is LOW when initiating conversion ‘n’, serial data
from conversion ‘n-1’ will be output on SDATA (pin 19)
following the start of conversion ‘n’. See Internal Data
Clock in the Reading Data section.
OPERATION
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output and the serial
output (only when using an external data clock) will be
affected whenever R/C goes HIGH. Refer to the Reading
Data section.
READING DATA
The ADS7806 outputs serial or parallel data in Straight
Binary or Binary Two’s Complement data output format. If
SB/BTC (pin 7) is HIGH, the output will be in SB format,
and if LOW, the output will be in BTC format. Refer to
Table V for ideal output codes.
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.
The parallel output can be read without affecting the internal
output registers; however, reading the data through the serial
Table III. Control Functions When Using Parallel Output
(DATACLK tied LOW, EXT/INT tied HIGH).
CS
R/C
BUSY
EXT/INT
DATACLK
↓
0
1
0
Output
Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.
OPERATION
Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.
0
↓
1
0
Output
↓
0
1
1
Input
Initiates conversion “n”. Internal clock still runs conversion process.
0
↓
1
1
Input
Initiates conversion “n”. Internal clock still runs conversion process.
↓
1
1
1
Input
Conversion “n” completed. Valid data from conversion “n” clocked out on SDATA synchronized
to external data clock.
↓
1
0
1
Input
Valid data from conversion “n-1” output on SDATA synchronized to external data clock.
Conversion “n” in progress.
0
↑
0
1
Input
Valid data from conversion “n-1” output on SDATA synchronized to external data clock.
Conversion “n” in progress.
0
0
↑
X
X
New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C
must be HIGH when BUSY goes HIGH.
X
X
0
X
X
New convert commands ignored. Conversion “n” in progress.
NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion “n-1”.
Table IV. Control Functions When Using Serial Output.
DESCRIPTION
ANALOG INPUT
±10
4.88mV
Full-Scale Range
Least Significant Bit (LSB)
0V to 5V
1.22mV
0V to 4V
976µV
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
STRAIGHT BINARY
(SB/BTC LOW)
(SB/BTC HIGH)
HEX
+Full Scale (FS – 1LSB)
CODE
HEX
BINARY CODE
CODE
9.99512V
4.99878V
3.999024V
0111 1111 1111 1111
7FF
1111 1111 1111 1111
FFF
0V
2.5V
2V
0000 0000 0000 0000
000
1000 0000 0000 0000
800
–4.88mV
2.49878V
1.999024V
1111 1111 1111 1111
FFF
0111 1111 1111 1111
7FF
–10V
0V
0V
1000 0000 0000 0000
800
0000 0000 0000 0000
000
Midscale
One LSB Below Midscale
BINARY CODE
–Full Scale
Table V. Output Codes and Ideal Input Voltages.
®
ADS7806
8
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going high can be used to latch the data.
Refer to Table VI and Figures 2 and 3 for timing constraints.
port will shift the internal output registers one bit per data
clock pulse. As a result, data can be read on the parallel port
prior to reading the same data on the serial port, but data
cannot be read through the serial port prior to reading the
same data on the parallel port.
PARALLEL OUTPUT
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table VI and Figures 2 and 3 for timing constraints.
To use the parallel output, tie EXT/INT (pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left
unconnected. The parallel output will be active when R/C
(pin 22) is HIGH and CS (pin 23) is LOW. Any other
combination of CS and R/C will tri-state the parallel output.
Valid conversion data can be read in two 8-bit bytes on D7D0 (pins 9-13 and 15-17) . When BYTE (pin 21) is LOW,
the 8 most significant bits will be valid with the MSB on D7.
When BYTE is HIGH, the 4 least significant bits will be
valid with the LSB on D4. BYTE can be toggled to read both
bytes within one conversion cycle.
Upon initial power up, the parallel output will contain
indeterminate data.
t1
t1
R/C
t3
t3
t4
BUSY
t5
t6
t6
t7
MODE
t8
Convert
Acquire
t12
Acquire
Convert
t12
t11
t10
Parallel
Data Bus
Previous
High Byte Valid
Previous High
Byte Valid
Hi-Z
Previous Low
Byte Valid
Not Valid
Low Byte
Valid
High Byte
Valid
High Byte
Valid
t9
t2
t12
t12
t9
Hi-Z
t12
t12
BYTE
FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH).
t21
t21
t21
t21
t21
t21
t21
t21
t21
t21
R/C
t1
CS
t3
BUSY
t4
BYTE
DATA
BUS
Hi-Z State
High Byte
t12
Hi-Z State
t9
Low Byte
t12
Hi-Z State
t9
FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.
®
9
ADS7806
SERIAL OUTPUT
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful
with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as
these pins will come out of Hi-Z state whenever CS (pin 23)
is LOW and R/C (pin 22) is HIGH. The serial output can not
be tri-stated and is always active.
SYMBOL
DESCRIPTION
t1
Convert Pulse Width
t2
Data Valid Delay after R/C LOW
t3
BUSY Delay from
Start of Conversion
INTERNAL DATA CLOCK (During A Conversion)
To use the internal data clock, tie EXT/INT (pin 8) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7806 will output 12
bits of valid data, MSB first, from conversion ‘n-1’ on
SDATA (pin 19), synchronized to 12 clock pulses output on
DATACLK (pin 18). The data will be valid on both the
rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 12th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to whatever logic level was input on TAG (pin 20) during the first
clock pulse. Refer to Table VI and Figure 4.
MIN TYP MAX UNITS
0.04
14.7
t4
BUSY LOW
14.7
t5
BUSY Delay after
End of Conversion
90
12
µs
20
µs
85
ns
20
µs
ns
t6
Aperture Delay
40
t7
Conversion Time
14.7
t8
Acquisition Time
t9
Bus Relinquish Time
10
t10
BUSY Delay after Data Valid
20
60
ns
t11
Previous Data Valid
after Start of Conversion
12
14.7
µs
t12
Bus Access Time and BYTE Delay
t13
Start of Conversion
to DATACLK Delay
1.4
µs
t14
DATACLK Period
1.1
µs
t15
Data Valid to DATACLK
HIGH Delay
20
75
ns
t16
Data Valid after DATACLK
LOW Delay
400
600
ns
t17
External DATACLK Period
100
ns
t18
External DATACLK LOW
40
ns
t19
External DATACLK HIGH
50
ns
t20
CS and R/C to External
DATACLK Setup Time
25
ns
EXTERNAL DATA CLOCK
To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7806, CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.
ns
20
µs
5
µs
83
ns
83
ns
t21
R/C to CS Setup Time
10
ns
t22
Valid Data after DATACLK HIGH
25
ns
t7 + t8
Throughput Time
25
An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions. While this is
perfectly acceptable, there is a possible problem when using
an external data clock. At an indeterminate point from 12µs
after the start of conversion 'n' until BUSY rises, the internal
logic will shift the results of conversion 'n' into the output
register. If CS is LOW, R/C is HIGH, and the external clock
is HIGH at this point, data will be lost. So, with CS LOW,
either R/C and/or DATACLK must be LOW during this
period to avoid losing valid data.
µs
TABLE VI. Conversion and Data Timing. TA = –40°C to
+85°C.
t7 + t8
CS or R/C(1)
t14
t13
DATACLK
1
2
3
11
12
1
2
Bit 9 Valid
Bit 1 Valid
LSB Valid
MSB Valid
Bit 10 Valid
t16
t15
MSB Valid
Bit 10 Valid
SDATA
(Results from previous conversion.)
BUSY
NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
®
ADS7806
10
FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion.
®
11
ADS7806
TAG
SDATA
BUSY
R/C
CS
EXTERNAL
DATACLK
t21
t3
t1
0
t18
t20
t19
Tag 0
t21
t17
t22
1
Tag 1
Bit 11 (MSB)
2
Tag 2
Bit 10
3
11
Tag 11
Bit 1
12
Tag 12
Bit 0 (LSB)
13
Tag 13
Tag 0
14
Tag 14
Tag 1
t20
t17
t18
t19
EXTERNAL
DATACLK
t20
t22
CS
t21
t20
R/C
t1
t11
BUSY
t3
DATA
Tag 0
TAG
Bit 11 (MSB)
Bit 0 (LSB)
Tag 0
Tag 1
Tag 1
Tag 12
Tag 13
Tag 14
FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion.
EXTERNAL DATA CLOCK
(After a Conversion)
TAG FEATURE
TAG (Pin 20) inputs serial data synchronized to the external
or internal data clock.
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. With CS
LOW and R/C HIGH, valid data from conversion ‘n’ will be
output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB will be valid
on the first falling edge and the second rising edge of the
external data clock. The LSB will be valid on the 12th falling
edge and 13th rising edge of the data clock. TAG (pin 20)
will input a bit of data for every external clock pulse. The
first bit input on TAG will be valid on SDATA on the 13th
falling edge and the 14th rising edge of DATACLK; the
second input bit will be valid on the 14th falling edge and the
15th rising edge, etc. With a continuous data clock, TAG
data will be output on SDATA until the internal output
registers are updated with the results from the next conversion. Refer to Table VI and Figure 5.
When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA until the
internal output register is updated with new conversion
results. See Table VI and Figures 5 and 6.
The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 12 bits
of valid data have been output.
INPUT RANGES
The ADS7806 offers three input ranges: standard ±10V and
0-5V, and a 0-4V range for complete, single supply systems.
Figures 7a and 7b show the necessary circuit connections for
implementing each input range and optional offset and gain
adjust circuitry. Offset and full scale error(1) specifications
are tested and guaranteed with the fixed resistors shown in
Figure 7b. Adjustments for offset and gain are described in
the Calibration section of this data sheet.
EXTERNAL DATA CLOCK
(During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to clock out
data from 12µs after the start of conversion ‘n’ until BUSY
(pin 24) rises; this will result in data loss. NOTE: For the
best possible performance when using an external data
clock, data should not be clocked out during a conversion.
The switching noise of the asynchronous data clock can
cause digital feedthrough degrading the converter’s performance. Refer to Table VI and Figure 6.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibration section).
The input impedance, summarized in Table II, results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
®
ADS7806
12
used for each input range (see Figure 8). The input resistor
divider network provides inherent overvoltage protection
guaranteed to at least ±25V.
INPUT RANGE
Analog inputs above or below the expected range will yield
either positive full scale or negative full scale digital outputs
respectively. There will be no wrapping or folding over for
analog inputs outside the nominal range.
GAIN ADJUST
RANGE (mV)
±10V
±15
±60
0 to 5V
±4
±30
0 to 4V
±3
±30
TABLE VII. Offset and Gain Adjust Ranges for Hardware
Calibration (see Figure 7a).
CALIBRATION
fications for offset and gain, the resistors shown in Figure 7b
are necessary. See the No Calibration section for more
details on the external resistors. Refer to Table VIII for the
range of offset and gain errors with and without the external
resistors.
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7806 in hardware, install the resistors shown in Figure 7a. Table VII lists
the hardware trim ranges relative to the input for each input
range.
NO CALIBRATION
See Figure 7b for circuit connections. Note that the actual
voltage dropped across the external resistors is at least two
orders of magnitude lower than the voltage dropped across
the internal resistor divider network. This should be consid-
SOFTWARE CALIBRATION
To calibrate the offset and gain in software, no external
resistors are required. However, to get the data sheet speci-
±10V
OFFSET ADJUST
RANGE (mV)
0-5V
0-4V
33.2kΩ
200Ω
200Ω
1
VIN
2
3
R1IN
4
+5V
2.2µF
+
5
50kΩ
50kΩ
1MΩ 2.2µF
R1IN
1
3
VIN
2
4
2.2µF
+
50kΩ
REF
AGND2
R2IN
3
100Ω
+5V
CAP
5
50kΩ
1MΩ 2.2µF
CAP
4
+
2.2µF
R2IN
CAP
50kΩ
REF
5
50kΩ
AGND2
AGND1
100Ω
+5V
+
6
R1IN
200Ω
AGND1
VIN
R2IN
+
6
+5V
2
33.2kΩ
AGND1
100Ω
33.2kΩ
1
REF
+
1MΩ 2.2µF
6
AGND2
FIGURE 7a. Circuit Diagrams (With Hardware Trim).
±10V
0-5V
200Ω
1
VIN
2
66.5kΩ
3
+5V
4
+
AGND1
1
2
33.2kΩ
R2IN
3
VIN
1
AGND1
R1IN
R2IN
2
VIN
AGND1
100Ω
CAP
4
+
REF
2.2µF
AGND2
3
CAP
R2IN
100Ω
5
+
6
33.2kΩ
R1IN
200Ω
2.2µF
5
2.2µF
200Ω
R1IN
100Ω
2.2µF
0-4V
4
REF
+
6
2.2µF
+
5
AGND2
2.2µF
CAP
REF
+
6
AGND2
FIGURE 7b. Circuit Diagrams (Without Hardware Trim).
®
13
ADS7806
ered when choosing the accuracy and drift specifications of
the external resistors. In most applications, 1% metal-film
resistors will be sufficient.
To further analyze the effects of removing any combination
of the external resistors, consider Figure 9. The combination
of the external and the internal resistors form a voltage
divider which reduces the input signal to a 0.3125V to
2.8125V input range at the CDAC. The internal resistors are
laser trimmed to high relative accuracy to meet full specifications. The actual input impedance of the internal resistor
network looking into pin 1 or pin 3 however, is only accurate
to ±20% due to process variations. This should be taken into
account when determining the effects of removing the external resistors.
The external resistors shown in Figure 7b may not be
necessary in some applications. These resistors provide
compensation for an internal adjustment of the offset and
gain which allows calibration with a single supply. Not
using the external resistors will result in offset and gain
errors in addition to those listed in the electrical specifications section. Offset refers to the equivalent voltage of the
digital output when converting with the input grounded. A
positive gain error occurs when the equivalent output voltage of the digital output is larger than the analog input. Refer
to Table VIII for nominal ranges of gain and offset errors
with and without the external resistors. Refer to Figure 8 for
typical shifts in the transfer functions which occur when the
external resistors are removed.
REFERENCE
The ADS7806 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
OFFSET ERROR
INPUT
RANGE
GAIN ERROR
W/ RESISTORS
W/OUT RESISTORS
(V)
RANGE (mV)
RANGE (mV)
TYP (mV)
W/ RESISTORS
RANGE (% FS)
RANGE (% FS)
W/OUT RESISTORS
TYP
±10
–10 ≤ BPZ ≤ 10
0 ≤ BPZ ≤ 35
+15
–0.4 ≤ G ≤ 0.4
0.15 ≤ G(1) ≤ 0.15
–0.3 ≤ G ≤ 0.5
–0.1 ≤ G(1) ≤ 0.2
+0.05
+0.05
0 to 5
–3 ≤ UPO ≤ 3
–12 ≤ UPO ≤ –3
–7.5
–0.4 ≤ G ≤ 0.4
0.15 ≤ G(1) ≤ 0.15
–1.0 ≤ G ≤ 0.1
–0.55 ≤ G(1) ≤ –0.05
–0.2
–0.2
0 to 4
–3 ≤ UPO ≤ 3
–10.5 ≤ UPO ≤ –1.5
–6
–0.4 ≤ G ≤ 0.4
–0.15 ≤ G(1) ≤ 0.15
–1.0 ≤ G ≤ 0.1
–0.55 ≤ G(1) ≤ –0.05
–0.2
–0.2
Note: (1) High Grade.
TABLE VIII. Range of Offset and Gain Errors with and without External Resistors
(a) Bipolar
(b) Unipolar
Digital Output
Digital Output
+Full Scale
+Full Scale
Analog Input
–Full Scale
Analog Input
–Full Scale
Typical Transfer Functions
With External Resistors
Typical Transfer Functions
Without External Resistors
FIGURE 8. Typical Transfer Functions With and Without External Resistors.
®
ADS7806
14
200Ω
39.8kΩ
CDAC (High Impedance)
VIN
(0.3125V to 2.8125V)
20kΩ
9.9kΩ
66.5kΩ
40kΩ
+5V
100Ω
+2.5V
+2.5V
200Ω
39.8kΩ
CDAC (High Impedance)
(0.3125V to 2.8125V)
33.2kΩ
40kΩ
20kΩ
9.9kΩ
100Ω
VIN
+2.5V
200Ω
+2.5V
39.8kΩ
CDAC (High Impedance)
VIN
(0.3125V to 2.8125V)
33.2kΩ
40kΩ
20kΩ
9.9kΩ
100Ω
+2.5V
+2.5V
FIGURE 9. Circuit Diagrams Showing External and Internal Resistors.
pin 5, the internal reference can be bypassed; REFD (pin 26)
tied HIGH will power-down the internal reference reducing
the overall power consumption of the ADS7806 by approximately 5mW.
ZCAP
CAP
(Pin 4)
The internal reference has approximately an 8 ppm/°C drift
(typical) and accounts for approximately 20% of the full
scale error (FSE = ±0.5% for low grade, ±0.25% for high
grade).
CDAC
Buffer
Internal
Reference
REF
(Pin 5)
The ADS7806 also has an internal buffer for the reference
voltage. See Figure 10 for characteristic impedances at the
input and output of the buffer with all combinations of
power down and reference down.
ZREF
PWRD 0
REFD 0
REF
REF (pin 5) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF tantalum capacitor
should be connected as close as possible to the REF pin from
ground. This capacitor and the output resistance of REF
create a low pass filter to bandlimit noise on the reference.
Using a smaller value capacitor will introduce more noise to
the reference, degrading the SNR and SINAD. The REF pin
should not be used to drive external AC or DC loads. See
Figure 10.
PWRD 0
REFD 1
PWRD 1
REFD 0
PWRD 1
REFD 1
ZCAP (Ω)
1
1
200
200
ZREF (Ω)
6k
100M
6k
100M
FIGURE 10. Characteristic Impedances of Internal Buffer.
CAP
CAP (pin 4) is the output of the internal reference buffer. A
2.2µF tantalum capacitor should be placed as close as
possible to the CAP pin from ground to provide optimum
switching currents for the CDAC throughout the conversion
cycle. This capacitor also provides compensation for the
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.
®
15
ADS7806
output of the buffer. Using a capacitor any smaller than 1µF
can cause the output buffer to oscillate and may not have
sufficient charge for the CDAC. Capacitor values larger than
2.2µF will have little affect on improving performance. See
Figures 10 and 11.
loading effects on the external reference. See Figure 10 for
the characteristic impedance of the reference buffer’s input
for both REFD HIGH and LOW. The internal reference
consumes approximately 5mW.
The output of the buffer is capable of driving up to 1mA of
current to a DC load. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degradation of the converter.
LAYOUT
POWER
For optimum performance, tie the analog and digital power
pins to the same +5V power supply and tie the analog and
digital grounds together. As noted in the electrical specifications, the ADS7806 uses 90% of its power for the analog
circuitry. The ADS7806 should be considered as an analog
component.
7000
6000
The +5V power for the A/D should be separate from the +5V
used for the system’s digital logic. Connecting VDIG (pin 28)
directly to a digital supply can reduce converter performance
due to switching noise from the digital logic. For best
performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal
conditioning. If +12V or +15V supplies are present, a simple
+5V regulator can be used. Although it is not suggested, if
the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered
digital supply or a regulated analog supply, both VDIG and
VANA should be tied to the same +5V source.
5000
µs
4000
3000
2000
1000
0
0.1
1
10
100
“CAP” Pin Value (µF)
FIGURE 11. Power-Down to Power-Up Time vs Capacitor
Value on CAP.
GROUNDING
Three ground pins are present on the ADS7806. DGND is the
digital supply ground. AGND2 is the analog supply ground.
AGND1 is the ground to which all analog signals internal to
the A/D are referenced. AGND1 is more susceptible to current
induced voltage drops and must have the path of least
resistance back to the power supply.
REFERENCE
AND POWER DOWN
The ADS7806 has analog power down and reference power
down capabilities via PWRD (pin 25) and REFD (pin 26)
respectively. PWRD and REFD HIGH will power down all
analog circuitry maintaining data from the previous conversion in the internal registers, provided that the data has not
already been shifted out through the serial port. Typical
power consumption in this mode is 50µW. Power recovery
is typically 1ms, using a 2.2µF capacitor connected to CAP.
See Figure 11 for power-down to power-up recovery time
relative to the capacitor value on CAP. With +5V applied to
VDIG, the digital circuitry of the ADS7806 remains active at
all times, regardless of PWRD and REFD states.
All the ground pins of the A/D should be tied to an analog
ground plane, separated from the system’s digital logic
ground, to achieve optimum performance. Both analog and
digital ground planes should be tied to the “system” ground
as near to the power supplies as possible. This helps to
prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The
amount of charge injection due to the sampling FET switch
on the ADS7806 is approximately 5-10% of the amount on
similar ADCs with the charge redistribution DAC (CDAC)
architecture. There is also a resistive front end which attenuates any charge which is released. The end result is a
minimal requirement for the drive capability on the signal
conditioning preceding the A/D. Any op amp sufficient for
the signal in an application will be sufficient to drive the
ADS7806.
PWRD
PWRD HIGH will power down all of the analog circuitry
except for the reference. Data from the previous conversion
will be maintained in the internal registers and can still be
read. With PWRD HIGH, a convert command yields meaningless data.
REFD
REFD HIGH will power down the internal 2.5V reference.
All other analog circuitry, including the reference buffer,
will be active. REFD should be HIGH when using an
external reference to minimize power consumption and the
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ADS7806
16
The resistive front end of the ADS7806 also provides a
guaranteed ±25V overvoltage protection. In most cases, this
eliminates the need for external over voltage protection
circuitry.
bus. This interface and the following discussion assume a
master clock for the QSPI interface of 16.78MHz. Notice
that the serial data input of the microcontroller is tied to the
MSB (D7) of the ADS7806 instead of the serial output
(SDATA). Using D7 instead of the serial port offers tri-state
capability which allows other peripherals to be connected to
the MISO pin. When communication is desired with those
peripherals, PCS0 and PCS1 should be left HIGH; that will
keep D7 tri-stated and prevent a conversion from taking
place.
INTERMEDIATE LATCHES
The ADS7806 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
In this configuration, the QSPI interface is actually set to do
two different serial transfers. The first, an eight bit transfer,
causes PCS0 (R/C) and PCS1 (CS) to go LOW starting a
conversion. The second, a twelve bit transfer, causes only
PCS1 (CS) to go LOW. This is when the valid data will be
transferred.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7806 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance. The effects of this phenomenon will
be more obvious when using the pin-compatible ADS7807
or any of the other 16-bit converters in the ADS Family. This
is due to the smaller internal LSB size of 38µV.
APPLICATIONS INFORMATION
QSPI INTERFACING
Figure 12 shows a simple interface between the ADS7806
and any QSPI equipped microcontroller. This interface assumes that the convert pulse does not originate from the
microcontroller and that the ADS7806 is the only serial
peripheral.
SCK
DATACLK
MISO
D7 (MSB)
For the fastest conversion rate, the baud rate should be set to
two (4.19MHz SCK), DT set to ten, the first serial transfer
set to eight bits, the second set to twelve bits, and DSCK
disabled (in the command control byte). This will allow for
a 23kHz maximum conversion rate. For slower rates, DT
should be increased. Do not slow SCK as this may increase
the chance of affecting the conversion results or accidently
initiating a second conversion during the first eight bit
transfer.
In addition, CPOL and CPHA should be set to zero (SCK
normally LOW and data captured on the rising edge). The
command control byte for the eight bit transfer should be set
to 20H and for the twelve bit transfer to 61H.
R/C
BUSY
SDATA
DATACLK
CS
EXT/INT
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode.
EXT/INT
For both transfers, the DT register (delay after transfer) is
used to cause a 19µs delay. The interface is also set up to
wrap to the beginning of the queue. In this manner, the QSPI
is a state machine which generates the appropriate timing for
the ADS7806. This timing is thus locked to the crystal based
timing of the microcontroller and not interrupt driven. So,
this interface is appropriate for both AC and DC measurements.
ADS7806
SCK
CS
FIGURE 13. QSPI Interface to the ADS7806. Processor
Initiates Conversions.
Convert Pulse
MOSI
R/C
PCS1
BYTE
Figure 13 shows another interface between the ADS7806
and a QSPI equipped microcontroller. The interface allows
the microcontroller to give the convert pulses while also
allowing multiple peripherals to be connected to the serial
PCS0/SS
PCS0
+5V
CPOL = 0
CPHA = 0
Before enabling the QSPI interface, the microcontroller
must be configured to monitor the slave select line. When a
transition from LOW to HIGH occurs on Slave Select (SS)
from BUSY (indicating the end of the current conversion),
the port can be enabled. If this is not done, the microcontroller
and the and the A/D may be “out-of-sync.”
QSPI
ADS7806
QSPI
BYTE
FIGURE 12. QSPI Interface to the ADS7806.
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ADS7806
SPI INTERFACE
The SPI interface is generally only capable of 8-bit data
transfers. For some microcontrollers with SPI interfaces, it
might be possible to receive data in a similar manner as
shown for the QSPI interface in Figure 12. The
microcontroller will need to fetch the 8 most significant bits
before the contents are overwritten by the least significant
bits.
the pulse width is (0.7)RC. Choosing a pulse width as close
to the minimum value specified in this data sheet will offer
the best performance. See the Starting A Conversion section of this data sheet for details on the conversion pulse
width.
The maximum conversion rate for a 20.48MHz DSP56000
is 35.6kHz. If a slower oscillator can be tolerated on the
DSP56000, a conversion rate of 40kHz can be achieved by
using a 19.2MHz clock and a prescale modulus of four.
A modified version of the QSPI interface shown in Figure 13
might be possible. For most microcontrollers with SPI interface, the automatic generation of the start-of-conversion
pulse will be impossible and will have to be done with
software. This will limit the interface to ‘DC’ applications
due to the insufficient jitter performance of the convert pulse
itself.
Convert Pulse
ADS7806
DSP56000
R/C
DSP56000 INTERFACING
The DSP56000 serial interface has an SPI compatibility
mode with some enhancements. Figure 14 shows an interface between the ADS7806 and the DSP56000 which is very
similar to the QSPI interface seen in Figure 12. As mentioned in the QSPI section, the DSP56000 must be programmed to enable the interface when a LOW to HIGH
transition on SC1 is observed (BUSY going HIGH at the end
of conversion).
The DSP56000 can also provide the convert pulse by including a monostable multi-vibrator as seen in Figure 15. The
receive and transmit sections of the interface are decoupled
(asynchronous mode) and the transmit section is set to
generate a word length frame sync every other transmit
frame (frame rate divider set to two). The prescale modulus
should be set to five.
SC1
BUSY
SRD
SDATA
SCO
DATACLK
CS
EXT/INT
SYN = 0 (Asychronous)
BYTE
GCK = 1 (Gated clock)
SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)
FIGURE 14. DSP56000 Interface to the ADS7806.
The monostable multi-vibrator in this circuit will provide
varying pulse widths for the convert pulse. The pulse width
will be determined by the external R and C values used with
the multi-vibrator. The 74HCT123N data sheet shows that
DSP56000
74HCT123N
+5V
+5V
R
B1
REXT1
CLR1
CEXT1
C
SC2
A1
Q1
ADS7806
R/C
SC0
DATACLK
SRD
SDATA
CS
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 16 bits)
FIGURE 15. DSP56000 Interface to the ADS7806. Processor Initiates Conversions.
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ADS7806
18
EXT/INT
BYTE