BB ADS7805P

ADS7805
®
DEMO BOARD
AVAILABLE
See Appendix A
16-Bit 10µs Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 100kHz min SAMPLING RATE
● STANDARD ±10V INPUT RANGE
The ADS7805 is a complete 16-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 16-bit, capacitor-based, SAR A/D with S/H,
reference, clock, interface for microprocessor use, and
three-state output drivers.
● 86dB min SINAD WITH 20kHz INPUT
● ±3.0 LSB max INL
● DNL: 16-bits “No Missing Codes”
● SINGLE +5V SUPPLY OPERATION
The ADS7805 is specified at a 100kHz sampling rate,
and guaranteed over the full temperature range. Lasertrimmed scaling resistors provide an industrystandard ±10V input range, while the innovative design allows operation from a single +5V supply, with
power dissipation under 100mW.
● PIN-COMPATIBLE WITH 12-BIT ADS7804
● USES INTERNAL OR EXTERNAL
REFERENCE
● FULL PARALLEL DATA OUTPUT
● 100mW max POWER DISSIPATION
The 28-pin ADS7805 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –25°C to +85°C range.
● 28-PIN 0.3" PLASTIC DIP AND SOIC
Clock
Successive Approximation Register and Control Logic
R/C
CS
BYTE
BUSY
CDAC
20kΩ
±10V Input
10kΩ
4kΩ
Comparator
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
CAP
Buffer
Internal
+2.5V Ref
4kΩ
REF
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1992 Burr-Brown Corporation
PDS-1157E
Printed in U.S.A. August, 1996
SPECIFICATIONS
ELECTRICAL
TA = –25°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7805P, U
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
ADS7805PB, UB
MAX
MIN
TYP
16
ANALOG INPUT
Voltage Ranges
Impedance
Capacitance
±10V
23
35
THROUGHPUT SPEED
Conversion Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
No Missing Codes
Transition Noise(2)
Full Scale Error(3,4)
Full Scale Error Drift
Full Scale Error(3,4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Power Supply Sensitivity
(VDIG = VANA = VD)
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Full-Power Bandwidth(6)
SAMPLING DYNAMICS
Aperture Delay
Transient Response
Overvoltage Recovery(7)
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer.)
Internal Reference Drift
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
Acquire and Convert
10
±4
±7
±2
±2
+4.75V < VD < +5.25V
Output Capacitance
±0.5
±10
±3
LSB(1)
Bits
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
LSB
±0.25
±0.25
✻
✻
±8
✻
94
83
–94
86
30
32
83
86
✻
✻
40
FS Step
✻
2
✻
150
Ext. 2.5000V Ref
µs
kHz
✻
–90
2.5
1
8
2.5
2.52
✻
2.7
✻
100
–0.3
+2.0
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Leakage Current
±5
250
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
✻
✻
±0.5
90
2.3
V
kΩ
pF
16
1.3
2.48
Bits
✻
15
fIN = 20kHz
fIN = 20kHz
fIN = 20kHz
–60dB Input
fIN = 20kHz
UNITS
✻
✻
✻
✻
100
Ext. 2.5000V Ref
Ext. 2.5000V Ref
MAX
+0.8
VD +0.3V
±10
±10
✻
✻
✻
✻
✻
✻
✻
dB(5)
dB
dB
dB
dB
kHz
ns
µs
ns
V
µA
✻
ppm/°C
V
✻
µA
✻
✻
✻
✻
V
V
µA
µA
✻
Parallel 16-bits
Binary Two’s Complement
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
VOUT = 0V to VDIG
High-Z State
+0.4
±5
✻
V
V
µA
15
15
pF
83
83
✻
✻
ns
ns
✻
+4
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADS7805
2
SPECIFICATIONS (CONT)
ELECTRICAL
TA = –25°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7805P, U
PARAMETER
POWER SUPPLIES
Specified Performance
VDIG
VANA
IDIG
IANA
Power Dissipation
ADS7805PB, UB
CONDITIONS
MIN
TYP
MAX
Must be ≤ VANA
+4.75
+4.75
+5
+5
0.3
16
+5.25
+5.25
fS = 100kHz
MIN
✻
✻
TYP
✻
✻
✻
✻
100
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
Thermal Resistance (θJA)
Plastic DIP
SOIC
–25
–55
–65
+85
+125
+150
75
75
✻
✻
✻
✻
✻
MAX
UNITS
✻
✻
✻
V
V
mA
mA
mW
✻
✻
✻
°C
°C
°C
°C/W
°C/W
NOTES: (1) LSB means Least Significant Bit. For the 16-bit, ±10V input ADS7805, one LSB is 305µV. (2) Typical rms noise at worst case transitions and
temperatures. (3) As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full
Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: VIN .............................................................................. ±25V
CAP .................................... +VANA +0.3V to AGND2 –0.3V
REF .......................................... Indefinite Short to AGND2,
Momentary Short to VANA
Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V
VANA ....................................................................................................... 7V
VDIG to VANA ..................................................................................... +0.3V
VDIG ....................................................................................................... 7V
Digital Inputs ............................................................ –0.3V to +VDIG +0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300°C
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PACKAGE INFORMATION
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
ADS7805P
ADS7805PB
ADS7805U
ADS7805UB
Plastic DIP
Plastic DIP
SOIC
SOIC
246
246
217
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ORDERING INFORMATION
PRODUCT
ADS7805P
ADS7805PB
ADS7805U
ADS7805UB
MAXIMUM
LINEARITY
ERROR (LSB)
MINIMUM
SIGNAL-TO(NOISE +
DISTORTION)
RATIO (dB)
±4
±3
±4
±3
83
86
83
86
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
–25°C
–25°C
–25°C
–25°C
Plastic DIP
Plastic DIP
SOIC
SOIC
to
to
to
to
+85°C
+85°C
+85°C
+85°C
®
3
ADS7805
DIGITAL
I/O
PIN #
NAME
1
VIN
DESCRIPTION
2
AGND1
3
REF
Reference Input/Output. 2.2µF tantalum capacitor to ground.
Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground.
Analog Input. See Figure 7.
Analog Ground. Used internally as ground reference point.
4
CAP
5
AGND2
6
D15 (MSB)
O
Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
7
D14
O
Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW.
8
D13
O
Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW.
9
D12
O
Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW.
10
D11
O
Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW.
11
D10
O
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
12
D9
O
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
13
D8
O
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
14
DGND
15
D7
O
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
16
D6
O
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
17
D5
O
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
18
D4
O
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
19
D3
O
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
20
D2
O
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
21
D1
O
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
22
D0 (LSB)
O
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
23
BYTE
I
Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).
24
R/C
I
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
Analog Ground.
Digital Ground.
25
CS
I
Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.
26
BUSY
O
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
27
VANA
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors.
28
VDIG
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA.
TABLE I. Pin Assignments.
PIN CONFIGURATION
VIN
1
28 VDIG
AGND1
2
27 VANA
REF
3
26 BUSY
CAP
4
25 CS
AGND2
5
24 R/C
D15 (MSB)
6
23 BYTE
D14
7
D13
8
21 D1
D12
9
20 D2
D11 10
19 D3
D10 11
18 D4
D9 12
17 D5
D8 13
16 D6
DGND 14
15 D7
22 D0 (LSB)
ADS7805
®
ADS7805
4
TYPICAL PERFORMANCE CURVES
TA = +25°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 6b, unless otherwise specified.
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 45kHz, 0dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 20kHz, 0dB)
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
0.0
12.5
25.0
37.5
50.0
0.0
25.0
37.5
50.0
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY AND INPUT AMPLITUDE
SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE
(fIN = 20kHz, 0dB; fS = 50kHz, 100kHz)
90
100.0
0dB
80
95.0
70
–20dB
60
SINAD (dB)
SINAD (dB)
12.5
Frequency (kHz)
50
40
30
85.0
100kHz
–60dB
20
50kHz
90.0
80.0
10
75.0
0
0
5
10
15
20
25
30
35
40
45
–50
–25
0
Input Signal Frequency (kHz)
25
50
75
Temperature (°C)
100
125
150
–80
105
–85
16-Bit LSBs
110
SFDR
100
–90
95
THD
90
SNR
–95
THD (dB)
–105
80
–110
0
25
50
75
100
8192 16384 24576 32768 40960 49152 57344 65535
Decimal Code
SINAD
–25
All Codes INL
–100
85
–50
3
2
1
0
–1
–2
–3
0
16-Bit LSBs
SFDR, SNR, and SINAD (dB)
A.C. PARAMETERS vs TEMPERATURE
(fIN = 20kHz, 0dB)
125
150
Temperature (°C)
3
2
1
0
–1
–2
–3
All Codes DNL
0
8192 16384 24576 32768 40960 49152 57344 65535
Decimal Code
®
5
ADS7805
TYPICAL PERFORMANCE CURVES
(CONT)
TA = +25°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 6b, unless otherwise specified.
CONVERSION TIME vs TEMPERATURE
2.515
7.9
2.510
7.8
Conversion Time (µs)
8.0
2.505
2.500
2.495
2.490
7.7
7.6
7.5
7.4
7.3
2.485
2.480
7.2
–25
0
25
50
75
100
125
–50
150
–25
0
mV From Ideal
BPZ ERROR (INTERNAL REFERNCE)
8
4
0
–4
–8
ENDPOINT ERRORS (EXTERNAL REFERNCE)
0.2
+FS Error
0.1
0.0
–0.1
–0.2
ENDPOINT ERRORS (EXTERNAL REFERNCE)
0.2
–FS Error
0.1
0.0
–0.1
–0.2
–50
–25
0
25
50
75
Temperature (°C)
®
ADS7805
25
50
75
Temperature (°C)
Temperature (°C)
Percent
From Ideal
–50
Percent
From Ideal
Internal Reference (V)
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
2.520
6
100
125
150
100
125
150
BASIC OPERATION
Table II for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
Figure 1 shows a basic circuit to operate the ADS7805 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (7µs max) will initiate a conversion.
BUSY (pin 26) will go LOW and stay LOW until the
conversion is completed and the output registers are updated. Data will be output in Binary Two’s Complement
with the MSB on pin 6. BUSY going HIGH can be used to
latch the data. All convert commands will be ignored while
BUSY is LOW.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output will become
active whenever R/C goes HIGH. Refer to the Reading
Data section.
The ADS7805 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibration section).
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) LOW for
a minimum of 40ns immediately puts the sample/hold of the
ADS7805 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be
ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient time to acquire a new signal.
The ADS7805 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. Refer to
CS
R/C
BUSY
1
X
X
None. Databus is in Hi-Z state.
OPERATION
↓
0
1
Initiates conversion “n”. Databus remains
in Hi-Z state.
0
↓
1
Initiates conversion “n”. Databus enters Hi-Z
state.
0
1
↑
Conversion “n” completed. Valid data from
conversion “n” on the databus.
↓
1
1
Enables databus with valid data from
conversion “n”.
↓
1
0
Enables databus with valid data from
conversion “n-1”(1). Conversion n in progress.
0
↑
0
Enables databus with valid data from
conversion “n-1”(1). Conversion “n” in progress.
0
0
↑
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
X
X
0
New convert commands ignored. Conversion
“n” in progress.
NOTE: (1) See Figures 3 and 4 for constraints on data valid from
conversion “n-1”.
Table II. Control Line Functions for “Read” and “Convert”.
200Ω
+
33.2kΩ
1
28
2
27
2.2µF
3
26
4
25
5
24
B15 (MSB)
6
23
B14
7
2.2µF
+
+
0.1µF
+
+5V
10µF
Convert Pulse
22
B0 (LSB)
ADS7805
B13
8
21
B1
B12
9
20
B2
B11
10
19
B3
B10
11
18
B4
B9
12
17
B5
B8
13
16
B6
14
15
B7
40ns min
6µs max
FIGURE 1. Basic Operation.
®
7
ADS7805
READING DATA
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 7µs after
the start of conversion ‘n’. Do not attempt to read data from
7µs after the start of conversion ‘n’ until BUSY (pin 26)
goes HIGH; this may result in reading invalid data. Refer to
Table IV and Figures 3 and 5 for timing specifications.
The ADS7805 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS
(pin 25) is LOW. Any other combination of CS and R/C will
tri-state the parallel output. Valid conversion data can be
read in a full parallel, 16-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read
both bytes within one conversion cycle. Refer to Table III
for ideal output codes and Figure 2 for bit locations relative
to the state of BYTE.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 3.
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
DESCRIPTION
ANALOG INPUT
Full Scale Range
±10V
Least Significant
Bit (LSB)
305µV
+Full Scale
(10V – 1LSB)
Midscale
One LSB below
Midscale
–Full Scale
BINARY CODE
HEX CODE
SYMBOL
DESCRIPTION
t1
Convert Pulse Width
7000
ns
Data Valid Delay after R/C LOW
8
µs
65
8
ns
µs
9.999695V
0111 1111 1111 1111
7FFF
t2
0V
0000 0000 0000 0000
0000
t3
t4
BUSY Delay from R/C LOW
BUSY LOW
–305µV
1111 1111 1111 1111
FFFF
t5
BUSY Delay after
End of Conversion
–10V
1000 0000 0000 0000
8000
Table III. Ideal Input Voltages and Output Codes.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D15-D0 (pin 6-13
and 15-22). BUSY going HIGH can be used to latch the
data. Refer to Table IV and Figures 3 and 5 for timing
specifications.
MIN TYP MAX UNITS
40
220
t6
Aperture Delay
40
t7
Conversion Time
7.6
8
µs
2
µs
83
Acquisition Time
t9
Bus Relinquish Time
10
35
t10
BUSY Delay after Data Valid
50
200
ns
t11
Previous Data Valid
after R/C LOW
7.4
µs
9
R/C to CS Setup Time
10
ns
t13
Time Between Conversions
10
µs
t14
Bus Access Time
and BYTE Delay
10
+5V
Bit 14
7
23
Bit 7
6
22 Bit 0 (LSB)
Bit 6
7
ADS7805
23
22 Bit 8
ADS7805
Bit 13
8
21 Bit 1
Bit 5
8
21 Bit 9
Bit 12
9
20 Bit 2
Bit 4
9
20 Bit 10
Bit 11 10
19 Bit 3
Bit 3 10
19 Bit 11
Bit 10 11
18 Bit 4
Bit 2 11
18 Bit 12
Bit 9 12
17 Bit 5
Bit 1 12
17 Bit 13
Bit 8 13
16 Bit 6
Bit 0 (LSB) 13
16 Bit 14
14
15 Bit 7
14
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
®
ADS7805
8
µs
Throughput Time
t12
BYTE HIGH
15 Bit 15 (MSB)
10
ns
t7 + t6
BYTE LOW
6
ns
t8
TABLE IV. Conversion Timing.
Bit 15 (MSB)
ns
83
ns
t1
R/C
t13
t2
t4
BUSY
t3
t6
t5
Convert
Acquire
MODE
Acquire
t7
DATA BUS
Previous
Data Valid
t8
Previous
Data Valid
Hi-Z
t9
Convert
Data Valid
Not Valid
Hi-Z
Data Valid
t10
t11
FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.)
t12
t12
t12
t12
R/C
t1
CS
t3
t4
BUSY
t6
MODE
Convert
Acquire
Acquire
t7
Hi-Z State
DATA BUS
Data Valid
Hi-Z State
t9
t14
FIGURE 4. Using CS to Control Conversion and Read Timing.
t12
t12
R/C
CS
BYTE
Pins 6 - 13
Hi-Z
High Byte
t14
Pins 15 - 22
Hi-Z
Low Byte
t14
Low Byte
High Byte
Hi-Z
t9
Hi-Z
FIGURE 5. Using CS and BYTE to Control Data Bus.
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ADS7805
INPUT RANGES
SOFTWARE CALIBRATION
The ADS7805 offers a standard ±10V input range. Figure 6
shows the necessary circuit connections for the ADS7805
with and without hardware trim. Offset and full scale error(1)
specifications are tested and guaranteed with the fixed resistors shown in Figure 6b. Adjustments for offset and gain are
described in the Calibration section of this data sheet.
To calibrate the offset and gain of the ADS7805 in software,
no external resistors are required. See the No Calibration
section for details on the effects of the external resistors. Refer
to Table V for range of offset and gain errors with and without
external resistors.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibration section).
NO CALIBRATION
See Figure 6b for circuit connections. The external resistors
shown in Figure 6b may not be necessary in some applications. These resistors provide compensation for an internal
adjustment of the offset and gain which allows calibration
with a single supply. The nominal transfer function of the
ADS7805 will be bound by the shaded region seen in Figure
7 with a typical offset of –30mV and a typical gain error of
–1.5%. Refer to Table V for range of offset and gain errors
with and without external resistors.
The nominal input impedance of 23kΩ results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors.
The input resistor divider network provides inherent overvoltage protection guaranteed to at lease ±25V. The 1% resistors
used for the external circuitry do not compromise the accuracy
or drift of the converter. They have little influence relative to
the internal resistors, and tighter tolerances are not required.
WITH
EXTERNAL
RESISTORS
WITHOUT
EXTERNAL
RESISTORS
UNITS
BP0
–10 < BPO < 10
–30 < BPO < 30
–50 < BPO < –15
–150 < BPO < –45
mV
LSBs
Gain
Error
–0.5 < error < 0.5
–2 < error < –1
% of FSR
NOTE: (1) Full scale error includes offset and gain errors measured at both +FS
and –FS.
CALIBRATION
TABLE V. Offset and Gain Errors With and Without External Resistors.
The ADS7805 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain. To achieve optimum performance,
several iterations may be required.
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7805, install the
proper resistors and potentiometers as shown in Figure 6a. The
calibration range is ±15mV for the offset and ±60mV for the
gain.
±10V With Hardware
a)
±10V Without Hardware
b)
Trim
Trim
200Ω
1
±10V
2
33.2kΩ
+5V
2.2µF
50kΩ
Offset
50kΩ
+
3
200Ω
2
AGND1
33.2kΩ
2.2µF
+
3
REF
VIN
AGND1
REF
576kΩ
4
Gain
2.2µF
4
CAP
+
2.2µF
5
FIGURE 6. Circuit Diagram With and Without External Resistors.
®
10
CAP
+
5
AGND2
NOTE: Use 1% metal film resistors.
ADS7805
1
±10V
VIN
AGND2
Digital
Output
7FFF
–10V
–9.99983V –9.9998V
–50mV
–15mV
9.9997V
9.999815V
+10V
Analog
Input
Ideal Transfer Function
With External Resistors
Range of Transfer Function
Without External Resistors
8000
FIGURE 7. Full Scale Transfer Function.
REFERENCE
CAP
The ADS7805 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
pin 5, the internal reference can be bypassed. The reference
voltage at REF is buffered internally with the output on CAP
(pin 4).
REF
CAP (pin 4) is the output of the internal reference buffer. A
2.2µF capacitor should be placed as close to the CAP pin as
possible to provide optimum switching currents for the
CDAC throughout the conversion cycle and compensation
for the output of the internal buffer. Using a capacitor any
smaller than 1µF can cause the output buffer to oscillate and
may not have sufficient charge for the CDAC. Capacitor
values larger than 2.2µF will have little affect on improving
performance.
REF (pin 3) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF capacitor should be
connected as close to the REF pin as possible. The capacitor
and the output resistance of REF create a low pass filter to
bandlimit noise on the reference. Using a smaller value
capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used
to drive external AC or DC loads.
The output of the buffer is capable of driving up to 2mA of
current to a DC load. DC loads requiring more than 2mA of
current from the CAP pin will begin to degrade the linearity
of the ADS7805. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degradation of the converter.
The internal reference has an 8 ppm/°C drift (typical) and
accounts for approximately 20% of the full scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade).
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.
®
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ADS7805
LAYOUT
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The
FET switch on the ADS7805, compared to the FET switches
on other CMOS A/D converters, releases 5%-10% of the
charge. There is also a resistive front end which attenuates
any charge which is released. The end result is a minimal
requirement for the anti-alias filter on the front end. Any op
amp sufficient for the signal in an application will be
sufficient to drive the ADS7805.
POWER
For optimum performance, tie the analog and digital power
pins to the same +5V power supply and tie the analog and
digital grounds together. As noted in the electrical specifications, the ADS7805 uses 90% of its power for the analog
circuitry. The ADS7805 should be considered as an analog
component.
The +5V power for the A/D should be separate from the +5V
used for the system’s digital logic. Connecting VDIG (pin 28)
directly to a digital supply can reduce converter performance
due to switching noise from the digital logic. For best
performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal
conditioning. If +12V or +15V supplies are present, a simple
+5V regulator can be used. Although it is not suggested, if
the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered
digital supply or a regulated analog supply, both VDIG and
VANA should be tied to the same +5V source.
The resistive front end of the ADS7805 also provides a
guaranteed ±25V overvoltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7805 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus. Tri-state
outputs can also be used when the A/D is the only peripheral
on the data bus.
GROUNDING
Three ground pins are present on the ADS7805. DGND is
the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals
internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path
of least resistance back to the power supply.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7805 has an internal LSB size of 38µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance.
All the ground pins of the A/D should be tied to the analog
ground plane, separated from the system’s digital logic
ground, to achieve optimum performance. Both analog and
digital ground planes should be tied to the “system” ground
as near to the power supplies as possible. This helps to
prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.
®
ADS7805
12