49% 172 FPO 0 ® PCM PCM1720 ® Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE TM FEATURES DESCRIPTION ● ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA The PCM1720 is a complete low cost stereo audio digital-to-analog converter (DAC), operating off of a 256fS or 384fS system clock. The DAC contains a 3rdorder ∆Σ modulator, a digital interpolation filter, and an analog output amplifier. The PCM1720 can accept 16-, 20-, or 24-bit input data in either normal or I2S formats. ● COMPLETE STEREO DAC: Includes Digital Filter and Output Amp ● DYNAMIC RANGE: 96dB ● MULTIPLE SAMPLING FREQUENCIES: 16kHz to 96kHz 8X Oversampling at All Sampling Frequencies The digital filter performs an 8X interpolation function and includes selectable features such as soft mute, digital attenuation and digital de-emphasis. The PCM1720 can accept standard digital audio sampling frequencies as well as one-half and double sampling frequencies. ● SYSTEM CLOCK: 256fS/384fS ● NORMAL OR I2S DATA INPUT FORMATS ● SELECTABLE FUNCTIONS: Soft Mute Digital Attenuator (256 Steps) Digital De-emphasis The PCM1720 is ideal for applications which combine compressed audio and video data such as DVD, DVDROM, set-top boxes and MPEG sound cards. ● OUTPUT MODE: Left, Right, Mono, Mute BCKIN LRCIN DIN Serial Input I/F 8X Oversampling Digital Filter with Function Controller ML Multi-level Delta-Sigma Modulator DAC Low-pass Filter VOUTL CAP Multi-level Delta-Sigma Modulator DAC Low-pass Filter VOUTR MC MD Mode Control I/F ZERO BPZ-Cont. Open Drain RSTB 256fS/384fS Power Supply SCKI VCC AGND VDD DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1333B Printed in U.S.A. August, 1996 SPECIFICATIONS All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1720 PARAMETER CONDITIONS RESOLUTION DATA FORMAT Audio Data Format Data Bit Length Sampling Frequency (fS) MIN Standard fS One-half fS Double fS 32 16 64 Internal System Clock Frequency DIGITAL INPUT/OUTPUT LOGIC LEVEL DYNAMIC PERFORMANCE(1) THD+N at fS (0dB) THD+N at –60dB Dynamic Range Signal-to-Noise Ratio(2) Channel Separation ANALOG OUTPUT Output Voltage Center Voltage Load Impedance fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz 90 92 90 POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: ICC + IDD UNITS 24 Bits 48 24 96 kHz kHz kHz –90 –88 –34 –31 96 93 100 97 97 –80 dB dB dB dB dB dB dB dB dB ±1.0 ±1.0 ±5.0 ±5.0 % of FSR % of FSR Standard/I2S 16/20/24 Selectable 44.1 22.05 88.2 256fS/384fS VOUT = VCC/2 at BPZ ±30 mV Full Scale (0dB) 0.62 x VCC VCC/2 Vp-p VDC kΩ AC Load 5 DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-emphasis Error INTERNAL ANALOG FILTER –3dB Bandwidth Passband Response MAX TTL DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error TYP 16 0.445 0.555 ±0.17 –35 11.125/fS –0.2 +0.55 100 –0.16 f = 20kHz VDD, VCC VCC = VDD = 5V, fS = 44.1kHz VCC = VDD = 5V, fS = 96kHz TEMPERATURE RANGE Operation Storage 4.5 –25 –55 5 18 25 fS fS dB dB sec dB kHz dB 5.5 25 35 VDC mA mA +85 +100 °C °C NOTES: (1) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode. (2) SNR is tested with Infinite Zero Detection off. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1720 2 PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SSOP PIN NAME TYPE 1 NC — FUNCTION No Connection. 2 SCKI IN System Clock Input: 256fS or 384fS. NC 1 20 DGND 3 TEST OUT SCKI 2 19 VDD 4* ML IN Latch Enable for Serial Control Data. 5* MC IN Clock for Serial Control Data. Reserved for Factory Use. TEST 3 18 NC 6* MD IN Data Input for Serial Control. ML 4 17 GND 7* RSTB IN Reset Input. When this pin is low, the digital filters and modulators are held in reset. MC 5 16 LRCIN 8 ZERO OUT MD 6 15 DIN Zero Data Flag. This pin is low when the data is continuously zero for more than 65,535 cycles of BCKIN. RSTB 7 14 BCKIN ZERO 8 13 CAP VOUTR 9 12 VOUTL AGND 10 11 VCC PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) PCM1720 20-Pin SSOP 334-1 9 VOUTR OUT Right Channel Analog Output. 10 AGND PWR Analog Ground. 11 VCC PWR Analog Power Supply (+5V). 12 VOUTL OUT 13 CAP — Common Pin for Analog Output Amplifiers. 14* BCKIN IN Bit Clock for Clocking in the Audio Data. 15* DIN IN Serial Audio Data Input. 16* LRCIN IN 17 GND PWR Left Channel Analog Output. Left/Right Word Clock. Frequency is equal to fs. Ground. 18 NC — 19 VDD PWR Digital Power Supply (+5V). Recommended connection is to the analog power supply. No Connection. 20 DGND PWR Digital Ground. Recommended connection is to the digital ground plane. * These pins include internal pull-up resistors. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Power Supply Voltage ....................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C Thermal Resistance, θJA .............................................................. +70°C/W ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® 3 PCM1720 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, 16-bit input data, unless otherwise noted. Measurement bandwidth is 20kHz DYNAMIC PERFORMANCE THD+N vs VCC, VDD THD+N vs TEMPERATURE –84 –30 –84 fS = 96kHz –88 –34 –90 fS = 44.1kHz –92 –86 THD+N at FS (dB) –38 5.0 –90 fS = 44.1kHz –92 –94 4.5 –88 –90 –25 5.5 0 VCC, VDD (V) 25 50 75 85 100 Temperature (°C) THD+N and DYNAMIC RANGE vs fS DYNAMIC RANGE and SNR vs VCC, VDD –86 100 90 SNR 98 THD+N (dB) –88 (dB) 96 Dynamic Range 94 92 THD+N –90 94 Dynamic Range –92 96 92 –94 90 3.5 4.0 4.5 5.0 5.5 48 88.2 Sampling Frequency, fS (kHz) VCC, VDD ® PCM1720 98 44.1 6.0 4 96 Dynamic Range (dB) THD+N at FS (dB) –86 THD+N at –60dB (dB) fS = 96kHz TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, RL = 44.1kHz, fSYS = 384fS, and 16-bit input data, unless otherwise noted. DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC PASSBAND RIPPLE CHARACTERISTIC 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –100 –1 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS 0 0.1134fS 5k 10k 15k 20k 25k 0 3628 15k 20k 25k 0 4999.8375 15k 14999.5125 19999.35 DE-EMPHASIS ERROR (48kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 10k 9999.675 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 14512 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 10884 DE-EMPHASIS ERROR (44.1kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 10k 7256 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 0.4535fS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 0.3402fS DE-EMPHASIS ERROR (3kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (3kHz) 0 –2 –4 –6 –8 –10 –12 0 0.2268fS Frequency (Hz) Frequency (Hz) 20k 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 25k Frequency (Hz) 5442 10884 16326 21768 Frequency (Hz) ® 5 PCM1720 1/fs L_ch R_ch LRCIN (pin 4) BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 14 15 16 1 2 MSB AUDIO DATA WORD = 20-BIT DIN (pin 5) 18 19 20 1 2 23 24 1 18 3 2 15 16 1 2 LSB MSB AUDIO DATA WORD = 24-BIT DIN (pin 5) 14 3 MSB 19 20 1 2 LSB 22 3 MSB 14 3 LSB 18 3 MSB 23 24 1 2 LSB 15 16 19 20 LSB 22 3 MSB 23 24 LSB FIGURE 1. “Normal” Data Input Timing. 1/fs L_ch LRCIN (pin 4) R_ch BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 1 2 MSB AUDIO DATA WORD = 20-BIT DIN (pin 5) 1 2 14 15 16 1 2 3 MSB 18 3 2 1 LSB MSB AUDIO DATA WORD = 24-BIT DIN (pin 5) 3 19 20 1 2 LSB 22 3 MSB 3 MSB 23 24 1 LSB 2 3 MSB 14 1 2 19 20 1 2 23 24 1 2 15 16 LSB 18 LSB 22 LSB FIGURE 2. “I2S” Data Input Timing. LRCKIN 1.4V tBCH tBCL tLB BCKIN 1.4V tBL tBCY 1.4V DIN tDS tDH BCKIN Pulse Cycle Time : tBCY : 100ns (min) BCKIN Pulse Width High : tBCH : 50ns (min) BCKIN Pulse Width Low : tBCL : 50ns (min) BCKIN Rising Edge to LRCIN Edge : tBL : 30ns (min) LRCIN Edge to BCKIN Rising Edge : tLB : 30ns (min) DIN Set-up Time : tDS : 30ns (min) DIN Hold Time : tDH : 30ns (min) FIGURE 3. Audio Data Input Timing. ® PCM1720 6 SPECIAL FUNCTIONS TYPICAL CONNECTION DIAGRAM Figure 4 illustrates the typical connection diagram for PCM1720 used in a stand-alone application. PCM1720 includes several special functions, including digital attenuation, digital de-emphasis, soft mute, data format selection and input word resolution. These functions are controlled using a three-wire interface. MD (pin 6) is used for the program data, MC (pin 5) is used to clock in the program data, and ML (pin 4) is used to latch in the program data. Table II lists the selectable special functions. SYSTEM CLOCK The system clock for PCM1720 must be either 256fS or 384fS, where fS is the audio sampling frequency (LRCIN), typically 32kHz, 44.1kHz or 48kHz. The system clock is used to operate the digital filter and the noise shaper. The system clock input (SCKI) is at pin 2. FUNCTION Input Audio Data Format Selection Normal Format I2S Format PCM1720 has a system clock detection circuit which automatically detects the frequency, either 256fS or 384fS. The system clock should be synchronized with LRCIN (pin 16), but PCM1720 can compensate for phase differences. If the phase difference between LRCIN and system clock is greater than ±6 bit clocks (BCKIN), the synchronization is performed automatically. The analog outputs are forced to a bipolar zero state (VCC/2) during the synchronization function. Table I shows the typical system clock frequency inputs for the PCM1720. DEFAULT MODE Normal Format Input Audio Data Bit Selection 16/20/24 Bits 16 Bits Input LRCIN Polarity Selection Lch/Rch = High/Low Lch/Rch = Low/High Lch/Rch = High/Low De-emphasis Control OFF Soft Mute Control OFF Attenuation Control Lch, Rch Individually Lch, Rch Common 0dB Lch, Rch Individually Fixed Infinite Zero Detection Circuit Control SAMPLING RATE (LRCIN) SYSTEM CLOCK FREQUENCY (MHz) OFF Operation Enable (OPE) 256fS 384fS 32kHz 8.192 12.288 44.1kHz 11.2896 16.9340 48kHz 12.288 18.432 Enabled Sample Rate Selection Internal System Clock Selection 256fS 384fS Sampling Frequency 44.1kHz Group 48kHz Group 32kHz Group TABLE I. System Clock Frequencies vs Sampling Rate. 384fS 44.1kHz Analog Output Mode L, R, Mono, Mute Stereo TABLE II. Selectable Functions. +5V Analog 20 DGND 15 14 PCM Audio Data Processor 16 2 19 VDD VOUTL DIN BCKIN CAP 12 13 200Ω + LRCIN SCKI VOUTR 256fS/384fS CLK PCM1720 ZERO ML MC MD RSTB AGND 10 Post LPF Analog Mute Lch Analog Out Post LPF Analog Mute Rch Analog Out 10µF 9 8 4 STRB 5 SCKO 6 SDO 7 System Controller PIO VCC 11 +5V Analog FIGURE 4. Typical Connection Diagram. ® 7 PCM1720 MAPPING OF PROGRAM REGISTERS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 REGISTER 2 res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUT REGISTER 3 res res res res res A1 A0 IZD SF1 SF0 res res res ATC LRP I2S PROGRAM REGISTER BIT MAPPING ATTENUATION DATA LOAD CONTROL, LCH Bit 8 (LDL) is used to simultaneously set analog outputs of Lch and Rch. An output level is controlled by AL[0:7] attenuation data when this bit is set to 1. When set to 0, an output level is not controlled and remains at the previous attenuation level. A LDR bit in Register 1 has an equivalent function as the LDL. When one of LDL or LDR is set to 1, the output level of the left and right channel is simultaneously controlled. The attenuation level is given by: PCM1720’s special functions are controlled using four program registers which are 16 bits long. These registers are all loaded using MD. After the 16 data bits are clocked in, ML is used to latch in the data to the appropriate register. Table III shows the complete mapping of the four registers and Figure 6 illustrates the data input timing. REGISTER NAME BIT NAME Register 0 AL (7:0) LDL A (1:0) res DAC Attenuation Data for Lch Attenuation Data Load Control for Lch Register Address Reserved Register 1 AR (7:0) LDL A (1:0) res DAC Attentuation Data for Rch Attenuation Data Load Control for Rch Register Address Reserved Register 2 MUT DEM OPE IW (1:0) PL (3:0) A (1:0) res Left and Right DACs Soft Mute Control De-emphasis Control Left and Right DACs Operation Control Input Audio Data Bit Select Output Mode Select Register Address Reserved I2S LRP ATC SYS SF (1:0) IZD A (1:0) res Audio Data Format Select Polarity of LRCIN (pin 7) Select Attenuator Control System Clock Select Sampling Rate Select Infinite Zero Detection Circuit Control Register Address Reserved Register 3 DESCRIPTION ATT = 20 log (y/256) (dB), where y = x, when 0 ≤ x ≤ 254 y = x + 1, when x = 255 X is the user-determined step number, an integer value between 0 and 255. Example: let x = 255 255 + 1 ATT = 20 log = 0dB 256 let x = 254 254 ATT = 20 log = –0. 068dB 256 let x = 1 1 = –48.16dB ATT = 20 log 256 TABLE III. Internal Register Mapping. let x = 0 0 ATT = 20 log = –∞ 256 REGISTER 0 (A1 = 0, A0 = 0) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 1 (A1 = 0, A0 = 1) res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 B15 B14 B13 B12 B11 B10 B9 B8 Register 0 is used to control left channel attenuation. Bits 0 - 7 (AL0 - AL7) are used to determine the attenuation level. The level of attenuation is given by: res res res res res Register 1 is used to control right channel attenuation. As in Register 1, bits 0 - 7 (AR0 - AR7) control the level of attenuation. ATT = [20 log10 (ATT_DATA/255)] dB ® PCM1720 B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 8 REGISTER 2 (A1 = 1, A0 = 0) B15 B14 B13 B12 B11 B10 B9 B8 res res res res res A1 B7 B6 B5 B4 B3 B2 B1 Bits 5, 6, 7, and 8 (PL0:3) are used to control output format. The output of PCM1720 can be programmed for 16 different states, as shown in Table VII. B0 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE Register 2 is used to control soft mute, de-emphasis, operation enable, input resolution, and output format. Bit 0 is used for soft mute: a “HIGH” level on bit 0 will cause the output to be muted (this is ramped down in the digital domain, so no “click” is audible). Bit 1 is used to control de-emphasis. A “LOW” level on bit 1 disables de-emphasis, while a “HIGH” level enables de-emphasis. PL0 PL1 PL2 PL3 Lch OUTPUT Rch OUTPUT NOTE 0 0 0 0 MUTE MUTE MUTE 0 0 0 1 MUTE R 0 0 1 0 MUTE L 0 0 1 1 MUTE (L + R)/2 0 1 0 0 R MUTE 0 1 0 1 R R 0 1 1 0 R L Bit 2, (OPE) is used for operational control. Table IV illustrates the features controlled by OPE. 0 1 1 1 R (L + R)/2 1 0 0 0 L MUTE 1 0 0 1 L R 1 0 1 0 L L DATA INPUT DAC OUTPUT SOFTWARE MODE INPUT 1 0 1 1 L (L + R)/2 Zero Forced to BPZ(1) Enabled 1 1 0 0 (L + R)/2 MUTE Other Forced to BPZ(1) Enabled 1 1 0 1 (L + R)/2 R Zero Controlled by IZD Enabled 1 1 1 0 (L + R)/2 L Other Normal Enabled 1 1 1 1 (L + R)/2 (L + R)/2 OPE = 1 OPE = 0 TABLE IV. Output Enable (OPE) Function. Zero IZD = 1 IZD = 0 Forced to BPZ(1) Other Normal Zero Zero(2) Other Normal DATA INPUT DAC OUTPUT Zero Controlled by OPE and IZD Enabled Other Controlled by OPE and IZD Enabled Zero Forced to BPZ(1) Disabled Other Forced to BPZ(1) Disabled Bits 3 (IW0) and 4 (IW1) are used to determine input word resolution. PCM1720 can be set up for input word resolutions of 16, 20, or 24 bits: Input Resolution 0 0 1 0 0 1 0 0 16-bit Data Word 20-bit Data Word 24-bit Data Word Reserved B5 B4 B3 B2 B1 B0 IZD SF1 SF0 res res res ATC LRP I2S res res res res A1 A0 Bit 2 (ATC) is used for controlling the attenuator. When bit 2 is “HIGH”, the attenuation data loaded in program Register 0 is used for both left and right channels. When bit 2 is “LOW”, the attenuation data for each register is applied separately to left and right channels. NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to output amplifier. Bit 3 (IW0) B8 B7 B6 res Bits 0 (I2S) and 1 (LRP) are used to control the input data format. A “LOW” on bit 0 sets the format to “Normal” (MSB-first, right-justified Japanese format) and a “HIGH” sets the format to I2S (Philips serial data protocol). Bit 1 (LRP) is used to select the polarity of LRCIN (sample rate clock). When bit 1 is “LOW”, left channel data is assumed when LRCIN is in a “HIGH” phase and right channel data is assumed when LRCIN is in a “LOW” phase. When bit 1 is “HIGH”, the polarity assumption is reversed. TABLE VI. Reset (RSTB) Function. Bit 4 (IW1) B15 B14 B13 B12 B11 B10 B9 Register 3 is used to control input data format and polarity, attenuation channel control, system clock frequency, sampling frequency and infinite zero detection. DAC OUTPUT SOFTWARE MODE INPUT RSTB = “LOW” MONO REGISTER 3 (A1 = 1, A0 = 1) TABLE V. Infinite Zero Detection (IZD) Function. RSTB = “HIGH” STEREO TABLE VII. Programmable Output Format. OPE controls the operation of the DAC: when OPE is “LOW”, the DAC will convert all non-zero input data. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be forced to zero only if IZD is “HIGH”. When OPE is “HIGH”, the output of the DAC will be forced to bipolar zero, irrespective of any input data. DATA INPUT REVERSE Bits 6 (SF0) and 7 (SF1) are used to select the sampling frequency: SF1 SF0 0 0 1 1 0 1 0 1 Sampling Frequency 44.1kHz group 48kHz group 32kHz group Reserved 22.05/44.1/88.2kHz 24/48/96kHz 16/32/64kHz Not Defined Bit 8 is used to control the infinite zero detection function (IZD). ® 9 PCM1720 When IZD is “LOW”, the zero detect circuit is off. Under this condition, no automatic muting will occur if the input is continuously zero. When IZD is “HIGH”, the zero detect feature is enabled. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be immediately forced to a bipolar zero state (VCC/2). The zero detection feature is used to avoid noise which may occur when the input is DC. When the output is forced to bipolar zero, there may be an audible click. PCM1720 allows the zero detect feature to be disabled so the user can implement external muting circuit. ML (pin 4) MC (pin 5) MD (pin 6) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 FIGURE 5. Serial Interface Timing. tMLS tMLH ML 1.4V tMCH tMLL tMCL MC 1.4V tMCY MD 1.4V tMDS tMDH MC Pulse Cycle Time : tMCY : 100ns (min) MC Pulse Width LOW : tMCL : 50ns (min) MC Pulse Width HIGH : tMCH : 50ns (min) MD Set-up Time : tMDS : 30ns (min) MC Hold Time : tMDH : 30ns (min) ML Low Level Time : tMLL : 30ns + 1SYSCLK (min) ML Set-up Time : tMLS : 30ns (min) ML Hold Time : tMLH : 30ns (min) FIGURE 6. Program Register Input Timing. ® PCM1720 10 APPLICATION CONSIDERATIONS INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0 DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1720: dB 0.5 0 –0.5 TD = 11.125 x 1/fS For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs –1.0 Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. 20 100 1k Frequency (Hz) 10k 24k FIGURE 7. Low Pass Filter Frequency Response. OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1720 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. dB INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) The performance of the internal low pass filter from DC to 24kHz is shown in Figure 7. The higher frequency rolloff of the filter is shown in Figure 8. If the user’s application has the PCM1720 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 9. For some applications, a passive RC filter or 2nd-order filter may be adequate. 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M 10M Frequency (Hz) FIGURE 8. Low Pass Filter Wideband Frequency Response. GAIN vs FREQUENCY 6 90 + VSIN 10kΩ 10kΩ 680pF OPA604 10kΩ 0 –34 –90 –54 –180 Phase (°) 1500pF Gain (dB) Gain –14 Phase 100pF – –74 –270 –94 –360 100 1k 10k Frequency (Hz) 100k 1M FIGURE 9. 3rd-Order LPF. ® 11 PCM1720 THEORY OF OPERATION POWER SUPPLY CONNECTIONS The delta-sigma section of PCM1720 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 11. This 5-level delta-sigma modulator has the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 48fS for a 384fS system clock, and 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 12. PCM1720 has two power supply connections: digital (VDD) and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.6V. An application circuit to avoid a latch-up condition is shown in Figure 10. Digital Power Supply Analog Power Supply 3rd ORDER ∆Σ MODULATOR 20 VCC DGND AGND 0 –20 Gain (–dB) VDD FIGURE 10. Latch-up Prevention Circuit. –40 –60 –80 –100 –120 BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. Refer to Figure 13 for optimal values of bypass capacitors. It is also recommended to include a 0.1µF ceramic capacitor in parallel with the 10µF tantalum capacitor. + + In 8fS 18-Bit –140 –160 0 5 + + – 15 FIGURE 12. Quantization Noise Spectrum. + Z–1 + Z–1 – + + 5-level Quantizer + 4 3 Out 48fS (384fS) 64fS (256fS) 2 1 0 FIGURE 11. 5-Level ∆Σ Modulator Block Diagram. ® PCM1720 10 Frequency (kHz) 12 Z–1 20 25 AC-3 APPLICATION Figure 13 shows the typical circuit diagram for Dolby AC-3, 5.1 channel system. 10µF + +5V Analog 20 SCKO AC-3 Audio Decoder 19 DGND LRCKO 15 14 SERO_0 SERO_1 16 SERO_2 2 SYSCKI VDD VOUTL BCKIN DIN CAP 6 7 13 Analog Mute Analog Out 200Ω + 10µF Post Low Pass Filter 9 ML MC ZERO 8 Mute Control MD RSTB AGND STRB µP Analog Out SCKI VOUTR 5 Analog Mute LRCIN PCM1720 4 Post Low Pass Filter 12 VCC 10 3.3µF + SCKO 11 +5V Analog SDO 10µF + Three-wire I/F (Serial I/O) +5V Analog 20 3 19 DGND 15 14 16 2 VDD VOUTL BCKIN Post Low Pass Filter 12 DIN CAP 13 6 7 + MC Post Low Pass Filter 9 ZERO 8 Mute Control MD RSTB VCC 10 3.3µF + 11 +5V Analog 10µF + 23 16 18 2 4 1 6 7 8 Reset 9 +5V Analog 22 PGND DGND Master Clock Generator or PLL Analog Out 10µF ML AGND 17 Analog Mute 200Ω SCKI VOUTR 5 Analog Out LRCIN PCM1720 4 Analog Mute 21 3 VDD VDP VOUTL BCKIN Post Low Pass Filter 14 Analog Mute Analog Out Analog Mute Analog Out LRCIN DIN CAP 15 200Ω + 10µF SCKO SCKI PCM1721 VOUTR MCKI 11 Post Low Pass Filter ML MC ZERO 10 Mute Control MD RSTB AGND 12 3.3µF + 19 VCC 13 +5V Analog FIGURE 13. Connection Diagram for a 6-Channel AC-3 Application. ® 13 PCM1720