® PWS750 Isolated, Unregulated DC/DC CONVERTER COMPONENTS FEATURES APPLICATIONS ● 100% TESTED FOR HIGH-VOLTAGE BREAKDOWN ● COMPACT-SURFACE MOUNT ● MULTICHANNEL OPERATION ● INDUSTRIAL PROCESS CONTROL EQUIPMENT ● GROUND-LOOP ELIMINATION ● PC-BASED DATA ACQUISITION ● 5V OR 15V INPUT OPTIONS ● FLEXIBLE USE WITH PWS740/PWS745 COMPONENTS ● VENDING MACHINES The PWS750-2U and PWS750-4U are split-bobbin wound isolation transformers using a ferrite core. They are encapsulated in plastic packages, allowing a high isolation voltage rating. DESCRIPTION The PWS750 consists of three building blocks for building a low cost DC/DC converter. With them you can optimize DC/DC converter PC board layout or build a multichannel isolated DC/DC converter. All parts are surface mount, requiring minimal space to build the converter. The modular design minimizes the cost of isolated power. The PWS750-1U is a high-frequency (800kHz nominal) driver that can drive N-channel MOSFETs up to the size of a 1.3A 2N7010. The recommended MOSFET for individual transformer drivers is the 2N7008. The PWS750-1U is supplied in a 16-pin double-wide SO package. PWS750 SINGLE-CHANNEL CONNECTION +V 10µH Reference Comparator (3) 1 RS VD 3 Driver Input Gnd 10Ω 2N7002 (2) or 2N7008 D G Differential Amplifier TTLOUT 14 16 PWS750-3U 4 6 3 7 2 0.3µF (3) Soft Start Oscillator 12 PWS750-2U 5 3 4 6 1 S T 11 0.3µF One PWS750-1U can be used to drive up to four channels (15V nominal operation). One PWS750-2U and PWS750-3U and two 2N7002 (surface mount) or 2N7008 (TO-92) MOSFETs made by Siliconix are used per isolated channel. When a PWS750-4U is used as the transformer (5V input), then two TN0604s made by Supertex must be used, due to the higher currents of the primary (lower RDS on) and the lower VGS threshold. With 5V operation only one channel can be directly driven by the PWS750-1U (a simple FET booster circuit can be used for multichannel operation; see Figure 3). (1) PWS750-1U +VIN 7 The PWS750-3U is a high-speed monolithic diode bridge in a plastic 8-pin SO package. D 10Ω G T 10 Enable TTLIN Typical Connection for Internal Oscillator Operation S Output (2) 2N7002 Ground or 2N7008 Duplicate for multichannel operation with PWS750-2U. 0.3µF 0.3µF (1) (1) 10Ω 10Ω –VO +VO NOTES: (1) User option. (2) Use TN0604 for 5V to ±15V operation. (3) Multichannel Operation. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1988 Burr-Brown Corporation PDS-838F 1 PWS750 Printed in U.S.A. April, 1997 SPECIFICATIONS ELECTRICAL At TA = 25°C; +V IN = +15V; and IOUT = ±15mA balanced loads, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS TTLIN = 0V 725 1 10 4.5 800 875 2.5 18 5.5 50 7 0.7 0.8 15 kHz MHz V V mApk V V nA µA V V mA 1.5 Vrms Vrms Ω || pF µArms 1.5 1.8 ns V µA V 1.5 Vrms Vrms Ω || pF µArms +70 +85 +85 °C °C °C PWS750-1U OSCILLATOR Frequency: Internal OSC External OSC Supply: 15V Operation 5V Operation T, T Drive Current T, T Drive Voltage, High Low TTLIN, IIH IIL VIH VIL TTLOUT, IOL 15 5 3 10 –1 2 PWS750-2U +VIN TO ±VOUT ISOLATION TRANSFORMER ISOLATION Voltage Rated Continuous AC 60Hz 100% Test (1) Barrier Impedance Leakage Current at 60Hz Winding Ratio 60Hz, 1s, <5pC PD 750 1200 1012 || 8 1 48/48 VISO = 240Vrms Primary/Secondary PWS750-3U DIODE BRIDGE Reverse Recovery Reverse Breakdown Reverse Current Forward Voltage IF = I R = 50mA IR = 100µA VR = 40V IF = 100mA 40 55 PWS750-4U +5VIN to ±15VOUT ISOLATION TRANSFORMER ISOLATION Voltage Rated Continuous AC 60Hz 100% Test (1) Barrier Impedance Leakage Current at 60Hz Winding Ratio 60Hz, 1s, <5pC PD 750 1200 1012 || 8 1 24/70 VISO = 240Vrms Primary/Secondary TEMPERATURE RANGE Specification Operating Storage Derated performance 0 –40 –40 NOTES: (1) Tested at 1.6 x rated, fail on 5pC partial discharge leakage current on five successive pulses at 60Hz. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PWS750 2 PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS PWS750-1U T VD +VIN PWS750-3U 1 16 2 15 3 14 TTL IN 4 13 5 12 TTLOUT T 6 11 Gnd 7 10 Enable 8 9 16-Pin SO Double-Wide Surface Mount –V 1 8 2 7 AC 3 6 AC +V 4 5 Supply Voltage ..................................................................................... 18V Junction Temperature ...................................................................... 150°C Storage Temperature ........................................................ –40°C to +85°C Lead temperature (soldering, SOIC, 3s) ........................................ +260°C Max Load, Sum of Both Outputs (PWS750-2U, 4U) ......................... 60mA ORDERING INFORMATION 8-Pin SO Surface Mount PWS750-XU Basic Model Number Components 1U : High-Frequency Driver 2U, 4U : Isolation Transformer 3U : High-Speed Monolithic Diode Bridge PWS750-2U PWS750-4U NC 1 8 NC AC 2 7 TO Gnd 3 6 VD 4 5 TO AC PACKAGE INFORMATION PRODUCT 8-Pin DIP Surface Mount PWS750-1U PWS750-2U PWS750-3U PWS750-4U PACKAGE PACKAGE DRAWING NUMBER(1) 16-Pin SOIC 8-Pin Plastic 8-Pin SO 8-Pin Plastic 211 226 182 226 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 PWS750 TYPICAL PERFORMANCE CURVES TA = +25°C, VIN = 15VDC, ILOAD = ±15mA unless otherwise noted. PWS750-4U LINE REGULATION PWR750-2U LINE REGULATION 5.4 18 5.3 16 5.2 Input (V) Input (V) 5.1 5 4.9 14 12 4.8 4.7 4.6 10 13 14 15 16 17 18 10 12 14 ±V OUT (V) 16 18 ±V OUT (V) PWR750-2U AND PWS70-4U LOAD LINES OUTPUT RIPPLE VOLTAGE 50 Ripple Voltage (mVp-p) ±VOUT (V) 20 PWS750-2U 15 40 Ripple Frequency = Oscillator Frequency 30 20 10 PWS750-4U 10 0 0 5 10 15 20 25 30 0.1 Load (mA) 0.2 0.4 0.6 0.8 1 Filter Capacitance (µF) TTL IN SIGNAL DUTY CYCLE EFFICIENCY/LOAD CURVE 80 100 PWS750-4U Acceptable Duty Cycle 75 % Duty Cycle Efficiency (%) 70 60 4 Channel PWS750-1U 50 PWS750-2U tH tL 50 DC = tH % t H + tL 25 40 Nominal Operating Frequency 0 30 0 5 10 15 20 25 30 1 Load Current (±mA) ® PWS750 1.5 2 Synchronization Frequency (MHz) (= Twice the FET Drive Frequency) 4 2.5 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VIN = 15VDC, ILOAD = ±15mA unless otherwise noted. THE OUTPUT VOLTAGE CAN BE ADJUSTED ±3% BY VARYING THE DRIVER FREQUENCY 15.5 16 15.25 15.5 ±VOUT (V) VOUT (V) OUTPUT VOLTAGE DRIFT WITH A ±15mA LOAD 15 15 14.5 14.75 14 14.5 –25 0 25 50 75 1 100 1.5 1.6 2 TTLIN Frequency (MHz) Temperature (°C) THEORY OF OPERATION The PWS750 components are basic building blocks to be used with other standard components to build an isolated push-pull DC/DC converter. The oscillator runs at 800kHz nominal, making it possible to reduce the size of the transformer and lower the output ripple voltage. During overload conditions the output drive shuts off for approximately 80µs, then turns back on for 20µs, resulting in a 25% power up duty cycle. If the overload condition still exists, then the output will shut off again. When the fault or the excessive load is removed, the converter resumes normal operation. PWS750-1U OSCILLATOR PIN FUNCTIONS The T and T pins are the complementary FET drive outputs and are tied directly to the corresponding FET gate. The connection must be as short as possible. For multiple channel operation they cannot be located above any ground or power planes, because capacitive loading will not allow fast enough charging of the FET gate. TTLIN is used to control the driver frequency with an external TTL level frequency source. The input frequency must be twice the desired driver frequency, since there is an internal divide-by-2 circuit to produce a 50% duty cycle output. The input duty cycle can vary from 12% to 95% (see Typical Performance Curves). When in the free running mode, the TTLIN pin must be tied to ground. PWS750-2U AND PWS750-4U TRANSFORMER PIN FUNCTIONS TTLOUT is used when it is desired to synchronize the outputs of multiple PWS750-1Us to minimize beat frequency problems. A standard open collector output is provided, therefore a 330Ω to 3.3kΩ pull-up resistor will be necessary depending on stray capacitance on the sync line. A maximum of eight PWS750-1Us can be connected without the use of an external TTL buffer. On the primary side the VD pin of the PWS750-2U is tied directly to the VD pin of the PWS750-1U. Remember to place a 0.1µF capacitor as close to the PWS750-2U VD pin as possible. The TO and TO pins are connected to the drains of the corresponding FETs, whose sources are connected to ground. On the secondary side of the transformer, the Gnd pin is tied directly to the isolated ground. AC pins are 800kHz square wave signals at twice the output voltage, and are connected directly to the corresponding pin on the PWS750-3U. Pins 2 and 4 can be interchanged for ease of hook up. The connection to the diode bridge must be as direct as possible to minimize radiated noise. An Enable pin is provided so that the driver (T, T) can be shut down to minimize power use if required. A TTL low applied to the pin will shut down the driver within one cycle. A TTL high will enable the driver within one cycle. The TTLOUT will still have an 800kHz signal when a master driver is disabled, so other synchronized drivers will not be shut down. The pin can be left open for normal operation. The winding ratio for the PWS750-2U is 1:1. This means that the output would normally be less than the input due to voltage drops in the FETs, transformer and diode bridge. Since the DC/DC converter is operating at 800kHz, the transformer is starting to operate close to the resonant frequency, which causes the output to increase in magnitude. The +VIN pin supplies power to the oscillator. The VD pin connects the power to the transformer through the internal overcurrent sense resistor. The other end of the overcurrent sense resistor is tied to +VIN. A 0.3µF bypass capacitor must be connected to the VD pin to reduce the ripple current through the shunt resistor; otherwise false current limit conditions can occur due to ripple voltage peaks. ® 5 PWS750 +VIN FIGURE 1. Sample PC Board Layout, 4:1. ® PWS750 6 MULTIPLE CHANNEL OPERATION The oscillator can drive up to four-channels (eight FETs) directly when operating at 10-18V. A 10Ω resistor must be placed in series with T and T to stabilize the FET gate charging. For more than four-channel operation, or 5Vmultiple-channel operation, the driver circuit needs a FET booster circuit, as shown in Figure 2. Large gate drive surge currents (>100mA) are needed to turn on the gates. PWS750-3U HIGH SPEED DIODE BRIDGE PIN FUNCTIONS The AC pins are tied directly to the AC pins of the PWS7502U. The +V and –V pins are rectified output voltages. The filter capacitors must be located as close as possible to these pins to minimize series inductance and therefore noise. Bypass capacitors will be needed at each device in the circuit. If the total output current drawn by all the channels exceeds 250mA, then it will be necessary to circumvent the current limit circuit by leaving the VD pin of the PWS750-1U open, and connect the VD pin of the PWS750-2U directly to the supply. BASIC OPERATION SINGLE CHANNEL OPERATION, PC BOARD LAYOUT CONSIDERATIONS A simple two-layer board can be used on single channel applications to create a DC/DC converter with low radiated noise. A ground plane should be located directly under both the input and the output components for optimum ground return paths. The surface mount components make it easy to design with a ground plane. The output filter capacitors should be located as close to the PWS750-3U as possible. A sample layout is shown in Figure 1. 5V OPERATION With 5V operation, the transformer winding current ratio is 3:1, therefore generating much greater currents in the primary. The input ripple voltage will be larger, so an input pi filter will be necessary to isolate the converter noise from the rest of the circuit. For example, when the output is ±15mA the input current will be at least 120mA. For multiple channel applications, T and T traces must have minimum capacitive loading. Therefore, there should be no ground plane (or power plane) under these two traces. The driver signal is a 4-6V low current 800kHz signal, which will generate little radiated noise if the traces are kept short. MOSFET MAX DRIVE CURRENT PACKAGE BREAKDOWN 4A 115mA 500mA 1.3A 1.2A TO-92 SO-T23 TO-92 TO-237 4-Pin DIP 40V 60V 60V 60V 60V TN0604 2N7002 2N7008 2N7010 2N7012 TABLE I. MOSFET Selector Guide. 3 +V +V IN VD 7 16 T Input Gnd D G S PWS750-1U 56Ω 1 11 0.3µF 2N7002 14 12 TTLOUT TTLIN 10 2N7002 T G D S EN 56Ω 10µH 2N7002 D User Option G 5 2 3 S 2N7002 D G +VO 0.3µF PWS750-2U 0.3µF 4 PWS750-3U 6 3 7 4 0.3µF 6 1 –VO Output Gnd S Duplicate for Up to 8 Channels FIGURE 2. MOSFET Driver Booster Circuits. ® 7 PWS750 OUTPUT CURRENT RATING The PWS750-1U oscillator contains soft start circuitry to protect the FETs from high inrush currents during turn on. The internal input current limit is 250mA peak to prevent thermal overload of the MOSFETs. The maximum output rating is ±30mA. Total current, which can be drawn from each isolation channel, is the total of the power being drawn from both the +V and –V outputs. For example, if one output is not used, then maximum current can be drawn from the other output. In all cases the maximum current that can be drawn from any individual channel is: When multiple channel operation is used, the maximum current of all channels must be reduced to prevent the overcurrent limit to trip. Alternately, bypass the overcurrent by leaving the VD pin of the PWS750-1U open and connecting the VD pin of the PWS750-2U directly to the supply. HIGH VOLTAGE TESTING Burr-Brown Corporation has adopted a partial discharge test criterion that conforms to the German VDE0884 optocoupler standard. This method requires that less than 5pC partial discharge crosses the isolation barrier with 1200Vrms 60Hz applied. This criterion confirms transient overvoltage (1.5 x 750Vrms) protection without damage to the PWS750-2U or PWS750-4U. Life test results verify the absence of high voltage breakdown under continuous rated voltage and maximum temperature. |+IOUT| + |–IOUT| < 60mA It should be noted that many analog circuit functions do not simultaneously draw equal current from both the positive and negative supplies. PWS750-1U 11 +VIN 7 14 0.33µF 16 1 3 ISO122P ISO122P 16 16 +VIN 8 8 15 7 VOUT 15 7 VOUT 9 10 10µH 9 2 1 2 1 1µF 4 1 3 +VIN 10 PWS750-2U 2 7 PWS750-2U 7 2 3 6 6 3 4 5 5 4 1 4 3 PWS750-3U PWS750-3U 6 6 2N7008, 8ea. 4 1 3 PWS750-2U 2 7 PWS750-2U 7 2 3 6 6 3 4 5 5 4 1 4 3 PWS750-3U PWS750-3U 6 4 6 1 4 1 1µF 1 1 2 2 9 +VIN 15 10 7 10 VOUT VOUT 8 9 15 7 8 16 16 ISO122P ISO122P FIGURE 3. Four-Channels of ±10V Signal Isolation with Channel-to-Channel Isolation. ® PWS750 8 +VIN The minimum AC barrier voltage that initiates partial discharge above 5pC is defined as the “inception voltage.” Decreasing the barrier voltage to a lower level is required before partial discharge ceases; this is known as “extinction voltage.” We have developed a package insulation system to yield an inception voltage greater than 1200Vrms so that transient voltages below this level will not damage the isolation barrier. The extinction voltage is above 750Vrms so that even overvoltage-induced partial discharge will cease once the barrier voltage is reduced to the rated value. Previous high voltage test methods relied on applying a large enough overvoltage (above rating) to break down marginal units, but not so high as to permanently damage good ones. Our partial discharge testing gives us more confidence in barrier reliability than breakdown/no breakdown criteria. 10µH TNO604 D +VIN PWS750-4U 1 7 5V PWS750-1U TNO604 D 0.3µF 3 16 VD 11 4 6 3 7 2 3 PWS750-3U 6 S T 0.3µF 5 S T TN0604 PWS750-4U D 4 5 S 14 Input Gnd TN0604 D 6 3 7 2 1 4 0.3µF 0.3µF PWS750-3U 6 S 0.3µF Power for output circuitry Power for input signal conditioning circuitry 3 1 4 16 0.3µF 10 V OUT 7 2 1 9 8 V IN ±10V 15 ±10V ISO122P FIGURE 4. A Complete ±10V Signal Acquisition System Operating From a Single 5V Supply. H7F TO7-14-3.5 1µF 180mA 3 Turns –VO TNO604 +5V 7 1 VD PWS750-1U 16 14 4 1 15 30 32 D – T G S PWS726 3 11 0.3µF 19 14 Gnd TTL In +VO 47pF FIGURE 5. A PWS750 Driver Can Be Used to Boost the Input Voltage to 15V to Power a PWS726 From a 5V Supply. ® 9 PWS750 Power for input signal conditioning circuits –V +V 2 1 3 4 11 10 VOUT ±10V 22 ISO103 V IN ±10V 12 16 24 14 21 0.3µF 10µH +VIN 0.3µF TN0604 PWS750-4U D 5 4 G S 1 7 5V PWS750-1U VD 3 16 11 4 6 3 7 2 6 1 TN0604 PWS750-4U D 5 4 S 3 4 TN0604 D G S 0.3µF 3 +VO PWS750-3U –VO 0.3µF 14 Input Gnd G TN0604 D G S 0.3µF 6 3 7 2 PWS750-3U 6 1 FIGURE 6. Powering the Internally Powered ISO103 Isolation Buffer From a Single 5V Supply. Two Power Channels Are Necessary to Provide the 80mA Nominal for the +V of the ISO103. 10µH 1 7 +VIN T PWS750-1U 3 VD 11 16 PWS740-2 2N7008 D G S 0.3µF 2N7008 D G S 4 3 5 2 6 1 3 6 +VO 0.3µF PWS750-3U 1 –VO 0.3µF 14 Input Gnd Output Gnd FIGURE 7. 1500VAC Isolation Using PWS740-2 Transformer. ® PWS750 4 10 2N7010 +VIN S PWS750-1U VD 3 T 11 1 D G T 16 7 2N7010 G D S 14 0.3µF Duplicate for up to 8 Channels PWS750-2U Input Gnd 10µH 5 3 4 4 +VO 0.3µF 6 3 7 2 PWS750-3U 0.3µF 6 1 –VO Output Gnd FIGURE 8. FET Pair Driving Up to Eight-Channels. 23 10 11 9 VOUT1 VIN1 ISO120 16 23 10 11 VOUT2 12 21 15 4 V– –VS1 VIN2 ISO120 16 12 21 15 4 22 Ext 3 Osc +VS1 24 V+ 9 V– 22 Ext 3 Osc +VS2 24 V+ 0.3µF 0.3µF 0.3µF 0.3µF 20pF Gnd1 VIN 1 V– PWS740-3 PWS750-3 20kΩ 20kΩ AC AC AC 6 3 6 GND AC PWS745-2 PWS740-2 PWS750-2 TO T 8 PWS740-3 PWS750-3 AC V+ 5 4 V+ 3 AC 4 20pF 4 V+ Gnd2 1 V– VD TO AC GND AC TO VD TO PWS745-2 PWS740-2 PWS750-2 2, 3 5V 0.3µF 6, 7 PWS745-1 T TTLIN 11 12 13 16 1 Up to 6 more channels 20µH 14, 15 10µF 0.3µF 0.3µF FIGURE 9. Synchronized-Multichannel Isolation System. ® 11 PWS750