CIRRUS CS3318

CS3318
8-Channel Analog Volume Control
Features
Description
 Complete Analog Volume Control
–
–
8 Independently Controllable Channels
3 Configurable Master Volume and Muting
Controls
 Wide Adjustable Volume Range
–
The CS3318 includes arrays of well-matched resistors
and complementary low-noise active output stages. A
total adjustable range of 118 dB, in ¼ dB steps, is
spread evenly over 96 dB of attenuation and 22 dB of
gain.
-96 dB to +22 dB in ¼ dB Steps
 Low Distortion & Noise
–
–
-112 dB THD+N
127 dB Dynamic Range
The CS3318 implements configurable zero-crossing
detection to provide glitch-free volume-level changes.
 Noise-Free Level Transitions
–
Zero-Crossing Detection with
Programmable Time-Out
 Low Channel-to-Channel Crosstalk
–
120 dB Inter-Channel Isolation
 Comprehensive Serial Control Port
–
–
–
Supports I²C® and SPITM Communication
Independent Control of up to 128 Devices
on a Shared 2-Wire I²C or 3-Wire SPI
Control Bus
Supports Individual and Grouped Control of
all CS3318 Devices on the I²C or SPI
Control Bus
 Flexible Power Supply Voltages
–
–
±8 V to ±9 V Analog Supply
+3.3 V Digital Supply
8-Channel
Analog
Inputs
The CS3318 is an 8-channel digitally controlled analog
volume control designed specifically for high-end audio
systems. It features a comprehensive I²C/SPI serial
control port for easy device and volume configuration.
The I²C/SPI control interface provides for easy system
integration of up to 128 CS3318 devices over a single 2wire I²C or 3-wire SPI bus, allowing many channels of
volume control with minimal system controller I/O requirements. Devices may be controlled on an individual
and grouped basis, simplifying simultaneous configuration of a group of channels across multiple devices,
while allowing discrete control over all channels on an
individual basis.
The device operates from ±8 V to ±9 V analog supplies
and has an input/output voltage range of ±6.65 V to
±7.65 V. The digital control interface operates at +3.3 V.
The CS3318 is available in a 48-pin LQFP package in
Commercial grade (-10° to 70° C). The CS3318 Customer Demonstration board is also available for device
evaluation. Refer to “Ordering Information” on page 44
for complete details.
±8 V to ±9 V
8
+3.3 V
+
I²C/SPI
Serial
Control
I²C / SPI
Control
Port
_
8
8-Channel
Analog
Outputs
Zero Crossing
Detector
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
DECEMBER '06
DS693F1
CS3318
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................ 5
2. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 7
SPECIFIED OPERATING CONDITIONS .................................................................................................... 7
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 7
ANALOG CHARACTERISTICS ................................................................................................................... 8
DIGITAL INTERFACE CHARACTERISTICS............................................................................................... 9
MUTE SWITCHING CHARACTERISTICS .................................................................................................. 9
CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT...................................................... 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT ................................................. 11
3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 12
4. DETAILED BLOCK DIAGRAM .......................................................................................................... 13
5. APPLICATIONS ................................................................................................................................. 14
5.1 General Description ..................................................................................................................... 14
5.2 System Design ............................................................................................................................ 14
5.2.1 Analog Inputs .................................................................................................................... 14
5.2.2 Analog Outputs .................................................................................................................. 15
5.2.3 Recommended Layout, Grounding, and Power Supply Decoupling ................................. 15
5.3 Power-Up and Power-Down ........................................................................................................ 15
5.3.1 Recommended Power-Up Sequence ................................................................................ 16
5.3.2 Recommended Power-Down Sequence ........................................................................... 16
5.4 Volume & Muting Control Architecture ........................................................................................ 17
5.4.1 Control Mapping Matrix ..................................................................................................... 17
5.4.2 Volume & Muting Control Implementation ......................................................................... 18
5.5 Volume Controls .......................................................................................................................... 19
5.5.1 Individual Channel Volume Controls ................................................................................. 19
5.5.2 Master Volume Controls .................................................................................................... 19
5.5.3 Volume Limits .................................................................................................................... 20
5.6 Muting Controls ........................................................................................................................... 21
5.6.1 Individual Channel Mute Controls ..................................................................................... 21
5.6.2 Master Mute Controls ........................................................................................................ 21
5.6.3 Hardware Mute Control ..................................................................................................... 21
5.7 Zero-Crossing Detection .............................................................................................................. 22
5.7.1 Zero-Crossing Modes ........................................................................................................ 22
5.7.2 Zero-Crossing Time-Out .................................................................................................... 22
5.8 System Serial Control Configuration ........................................................................................... 23
5.8.1 Serial Control within a Single-CS3318 System ................................................................. 23
5.8.2 Serial Control within a Multiple-CS3318 System ............................................................... 24
5.8.2.1 SPI Mode Serial Control Configuration .......................................................................................... 24
5.8.2.2 I²C Mode Control Configuration ..................................................................................................... 26
5.9 I²C/SPI Serial Control Formats .................................................................................................... 27
5.9.1 I²C Mode ............................................................................................................................ 27
5.9.2 SPI Mode ........................................................................................................................... 28
6. CS3318 REGISTER QUICK REFERENCE ........................................................................................ 29
7. CS3318 REGISTER DESCRIPTIONS ................................................................................................ 31
7.1 Ch 1-8 Volume - Addresses 01h - 08h ........................................................................................ 31
7.1.1 Volume Control (Bits 7:0) .................................................................................................. 31
7.2 ¼ dB Control - Address 09h ........................................................................................................ 32
7.2.1 ¼ dB Control (Bit 0 - 7) ...................................................................................................... 32
7.3 Mute Control - Address 0Ah ........................................................................................................ 33
7.3.1 Mute Channel X (Bit 0 - 7) ................................................................................................. 33
7.4 Device Configuration 1 - Address 0Bh (Bit 5) .............................................................................. 33
7.4.1 Enable MUTE Input (Bit 5) ................................................................................................ 33
2
DS693F1
CS3318
7.4.2 MUTE Input Polarity (Bit 4) ................................................................................................ 33
7.4.3 Channel B = Channel A (Bit 0 - 3) ..................................................................................... 34
7.5 Device Configuration 2 - Address 0Ch ........................................................................................ 34
7.5.1 Zero-Crossing Time-Out Period (Bits 4:2) ......................................................................... 34
7.5.2 Zero-Crossing Mode (Bits 1:0) .......................................................................................... 35
7.6 Channel Power - Address 0Dh .................................................................................................... 35
7.6.1 Power Down Channel X (Bit 0 - 7) .................................................................................... 35
7.7 Master Power - Address 0Eh ....................................................................................................... 35
7.7.1 Power Down All (Bit 0) ...................................................................................................... 35
7.8 Freeze Control - Address 0Fh ..................................................................................................... 36
7.8.1 Freeze (Bit 7) ..................................................................................................................... 36
7.9 Master 1 Mask - Address 10h ...................................................................................................... 36
7.10 Master 1 Volume - Address 11h ................................................................................................ 36
7.10.1 Master 1 Volume Control (Bits 7:0) ................................................................................. 36
7.11 Master 1 Control - Address 12h ................................................................................................. 37
7.11.1 Master 1 Mute (Bit 1) ....................................................................................................... 37
7.11.2 Master 1 ¼ dB Control (Bit 0) .......................................................................................... 37
7.12 Master 2 Mask - Address 13h .................................................................................................... 37
7.13 Master 2 Volume - Address 14h ................................................................................................ 37
7.13.1 Master 2 Volume Control (Bits 7:0) ................................................................................. 37
7.14 Master 2 Control - Address 15h ................................................................................................. 38
7.14.1 Master 2 Mute (Bit 1) ....................................................................................................... 38
7.14.2 Master 2 ¼ dB Control (Bit 0) .......................................................................................... 38
7.15 Master 3 Mask - Address 16h .................................................................................................... 38
7.16 Master 3 Volume - Address 17h ................................................................................................ 38
7.16.1 Master 3 Volume Control (Bits 7:0) ................................................................................. 38
7.17 Master 3 Control - Address 18h ................................................................................................. 39
7.17.1 Master 3 Mute (Bit 1) ....................................................................................................... 39
7.17.2 Master 3 ¼ dB Control (Bit 0) .......................................................................................... 39
7.18 Group 2 Chip Address 19h ........................................................................................................ 40
7.18.1 Group 2 Chip Address (Bits 7:1) ..................................................................................... 40
7.18.2 Enable Group 2 Address (Bit 0) ...................................................................................... 40
7.19 Group 1 Chip Address 1Ah ........................................................................................................ 40
7.19.1 Group 1 Chip Address (Bits 7:1) ..................................................................................... 40
7.19.2 Enable Group 1 Address (Bit 0) ...................................................................................... 40
7.20 Individual Chip Address 1Bh ..................................................................................................... 41
7.20.1 Individual Chip Address (Bits 7:1) ................................................................................... 41
7.20.2 Enable Next Device (Bit 0) .............................................................................................. 41
7.21 Chip ID - Address 1Ch ............................................................................................................... 41
7.21.1 Chip ID (Bits 7:4) ............................................................................................................. 41
7.21.2 Chip Revision (Bits 3:0) ................................................................................................... 41
8. PARAMETER DEFINITIONS .............................................................................................................. 42
9. PACKAGE DIMENSIONS .................................................................................................................. 43
10. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................ 43
11. ORDERING INFORMATION ............................................................................................................ 44
12. REVISION HISTORY ........................................................................................................................ 44
DS693F1
3
CS3318
LIST OF FIGURES
Figure 1.Control Port Timing - I²C Format.................................................................................................. 10
Figure 2.Control Port Timing - SPI Format................................................................................................. 11
Figure 3.Typical Connection Diagram........................................................................................................ 12
Figure 4.Detailed Block Diagram ............................................................................................................... 13
Figure 5.CS3318 Control Mapping Matrix.................................................................................................. 17
Figure 6.Volume & Muting Control Implementation ................................................................................... 18
Figure 7.Standard I²C Connections............................................................................................................ 23
Figure 8.Standard SPI Connections........................................................................................................... 23
Figure 9.SPI Serial Control Connections ................................................................................................... 24
Figure 10.Individual Device Address Configuration Process ..................................................................... 25
Figure 11.I²C Serial Control Connections .................................................................................................. 26
Figure 12.Control Port Timing, I²C Write.................................................................................................... 27
Figure 13.Control Port Timing, I²C Read.................................................................................................... 28
Figure 14.SPI Write Cycle.......................................................................................................................... 28
LIST OF TABLES
Table 1. Example Volume Settings ............................................................................................................ 20
Table 2. Zero-Crossing Modes................................................................................................................... 22
Table 3. Zero-Crossing Time-Out Periods ................................................................................................. 22
Table 4. I²C Mode Default Chip Address ................................................................................................... 27
Table 5. Example Volume Settings ............................................................................................................ 31
Table 6. Example Volume Settings ............................................................................................................ 32
Table 7. Channel B = Channel A Settings ................................................................................................. 34
Table 8. Zero-Crossing Time-Out Settings ................................................................................................ 34
Table 9. Zero-Crossing Mode Settings ...................................................................................................... 35
Table 10. Chip Revision Register Codes ................................................................................................... 41
4
DS693F1
CS3318
OUT3
REFO3
IN3
REFI3
REFI2
IN2
REFO2
OUT2
VA+
VA-
OUT1
REFO1
1. PIN DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
IN1
1
36
VA-
REFI1
2
35
VA+
RESET
3
34
OUT4
MUTE
4
33
REFO4
SCL/CCLK
5
32
IN4
SDA/MOSI
6
31
REFI4
AD0/CS
7
30
REFI5
ENOut
8
29
IN5
DGND
9
28
REFO5
VD
10
27
OUT5
REFI8
11
26
VA-
IN8
12
25
VA+
CS3318
Pin Name
#
IN1
1
IN2
42
IN3
39
IN4
32
IN5
29
IN6
22
IN7
19
IN8
12
DS693F1
OUT6
REFO6
IN6
REFI6
REFI7
IN7
REF07
VA-
OUT7
VA+
OUT8
REFO8
13 14 15 16 17 18 19 20 21 22 23 24
Pin Description
Analog Inputs (Input) - The full-scale level is specified in the Analog Characteristics specification
table.
5
CS3318
Pin Name
#
OUT1
47
OUT2
44
OUT3
37
OUT4
34
OUT5
27
OUT6
24
OUT7
17
OUT8
14
REFI1
2
REFI2
41
REFI3
40
REFI4
31
REFI5
30
REFI6
21
REFI7
20
REFI8
11
REFO1
48
REFO2
43
REFO3
38
REFO4
33
REFO5
28
REFO6
23
REFO7
18
REFO8
13
Pin Description
Analog Outputs (Output) - The full-scale output level is specified in the Analog Characteristics specification table.
Reference In (Input) - Analog reference pin.
Reference Out (Output) - Analog reference pin.
15,
VA+
25,
35,
Positive Analog Power (Input) - Positive power for the internal analog section.
45
16,
VA-
26,
36,
Negative Analog Power (Input) - Negative power for the internal analog section.
46
RESET
3
Reset (Input) - The device enters a low-power mode when this pin is driven low.
MUTE
4
Mute (Input) - This pin defaults to an active low mute input, and may be configured as an active high
mute input.
SCL/CCLK
5
Serial Control Port Clock (Input) - Serial clock for the serial control port.
SDA/MOSI
6
Serial Control Data (Input/Output) - SDA is a data I/O line for the control port interface in I²C Mode.
MOSI is the input data line for the control port interface in SPI Mode.
AD0/CS
7
Default Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 sets the LSB of the default
chip address in I²C Mode. CS is the chip-select signal for SPI format.
ENOut
8
Enable Output (Output) - Enable output signal for multi-device serial control chain configuration.
DGND
9
Digital Ground (Input) - Ground reference for the internal digital section.
VD
10
Digital Power (Input) - Positive power for the internal digital section.
6
DS693F1
CS3318
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25°C.
SPECIFIED OPERATING CONDITIONS
(DGND = 0 V; All voltages with respect to ground.)
Parameters
DC Power Supplies:
Positive Analog
Negative Analog
Digital
Ambient Operating Temperature (Power Applied)
Symbol
Min
Nom
Max
Units
VA+
VAVD
TA
7.6
-9.45
3.1
-10
9.0
-9.0
3.3
-
9.45
-7.6
3.5
+70
V
V
V
°C
ABSOLUTE MAXIMUM RATINGS
(DGND = 0 V; All voltages with respect to ground. (Note 1)
Parameter
Symbol
Min
Max
Units
VA+
VAVD
-0.3
-10.5
-0.3
10.5
0.3
3.63
V
V
V
Iin
-
±10
mA
Analog Input Voltage
VINA
(VA-) - 0.3
(VA+) + 0.3
V
Digital Input Voltage
VIND
VD - 0.3
VD + 0.3
V
Ambient Operating Temperature (Power Applied)
TA
-55
+125
°C
Storage Temperature
Tstg
-65
+150
°C
DC Power Supplies:
Input Current
Positive Analog
Negative Analog
Digital
(Note 2)
Notes:
1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS693F1
7
CS3318
ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): RS = 0; RL = 20 kΩ; CL = 20 pF; 10 Hz to 20 kHz Measurement
Bandwidth)
Parameter
Symbol
Min
Typ
Max
Unit
RIN
CIN
8
-
0.25
±0.5
±0.1
10
10
-
dB
dB
dB
kΩ
pF
121
(VA-) + 1.35
-
0.00025
127
1.8
-120
VOS
ROUT
RLOAD
2
-
0.75
100
20
5
5
100
-
mV
Ω
kΩ
pF
mA
MHz
IVA+
IVAIVD
IPD
-
36
36
0.6
60
650
540
80
50
50
1.07
904
-
mA
mA
mA
μA
mW
μW
dB
DC Characteristics
Step Size
Gain Error
Gain Matching Between Channels
Input Resistance
Input Capacitance
(Vol = +22 dB)
(Vol = +22 dB)
AC Characteristics
Total Harmonic Distortion + Noise
Dynamic Range
Input/Output Voltage Range
Output Noise
Interchannel Isolation
(Note 3) THD+N
(THD+N < 1 %)
(Note 4)
(1 kHz)
VFS
0.00063
%
dB
(VA+) - 1.35
V
3.6
μVrms
dB
Output Buffer
Offset Voltage
Output Resistance
AC Load Resistance
Load Capacitance
Short Circuit Current
Unity Gain Bandwidth, Small Signal
(Note 4)
Power Supplies
Supply Current (No Load, Vin = 0 V)
Normal Operation
Power-Down, All Supplies (Note 5)
Normal Operation
Power Down (Note 5)
Power Supply Rejection Ratio (250 Hz)
Power Consumption
PSRR
3. Vin = [(VFS Max - VFS Min) - 1.6 V] Vp-p, 1 kHz, Volume = 0 dB.
Note that for (VA+) = -(VA-) = 9 V, Vin = 13.7 Vp-p = 4.8 VRMS.
4. Measured with input grounded and volume = 0 dB. Will increase as a function of volume settings >0 dB.
5. Power-down is defined as RESET = low, all clock and data lines held static, and no analog input signals
applied.
8
DS693F1
CS3318
DIGITAL INTERFACE CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at Io=2 mA
VIH
VIL
VOH
0.7 x VD
VD - 1.0
-
0.2 x VD
-
V
V
V
Low-Level Output Voltage at Io=2 mA
VOL
-
-
0.4
V
Iin
-
8
±10
-
μA
pF
Symbol
Min
Typ
Max
Units
-
2
-
-
ms
Input Leakage Current
Input Capacitance
MUTE SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = DGND, Logic 1 = VD)
Parameters
MUTE Active Pulse Width
(Note 6)
6. The MUTE active state (low/high) is set by the MutePolarity bit in the Device Configuration 1 register
(see page 33).
DS693F1
9
CS3318
CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Symbol
Min
Max
Unit
SCL Clock Frequency
Parameter
fscl
-
100
kHz
RESET Rising Edge to Start
tirs
100
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
SDA Hold Time from SCL Falling
(Note 7)
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trd
-
1
µs
Fall Time SCL and SDA
tfc, tfd
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
SDA Setup time to SCL Rising
7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RESET
t
irs
Stop
R e p e ate d
Sta rt
Start
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 1. Control Port Timing - I²C Format
10
DS693F1
CS3318
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsck
0
6.0
MHz
RESET Rising Edge to CS Falling
tsrs
100
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
μs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 8)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 9)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 9)
tf2
-
100
ns
8. Data must be held for sufficient time to bridge the transition time of CCLK.
9. For fsck <1 MHz.
t srs
RESET
CS
t scl
t css
t sch
t csh
CCLK
t r2
t f2
MOSI
t dsu
t dh
Figure 2. Control Port Timing - SPI Format
DS693F1
11
CS3318
3. TYPICAL CONNECTION DIAGRAM
+8 V to +9V
+8 V to +9V
10 µF
0.1 µF
0.1 µF
10 µF
-8 V to -9V
-8 V to -9V
Audio
Source
36
+
VA
-
35
VA
45
VA
VA
+
46
1
IN1
OUT1 47
42
IN2
OUT2 44
39
IN3
OUT3 37
32
IN4
OUT4 34
29
IN5
OUT5 27
22
IN6
19
IN7
12
IN8
Audio
Outputs
OUT6 24
CS3318
OUT7 17
OUT8 14
See Note
2 kΩ
5
+3.3 V
6
SDA/MOSI
7
AD0/CS
3
RESET
4
MUTE
DGND 9
2
REFI1
REFO1 48
41
REFI2
REFO2 43
40
REFI3
REFO3 38
31
REFI4
REFO4 33
30
REFI5
REFO5 28
21
REFI6
REFO6 13
20
REFI7
REFO7 18
11
REFI8
REFO8 13
VD 10
VA
VA
VA
VA
+
0.1 µF
+
Host
Controller
To Next CS3318
ENOut 8
SCL/CCLK
-
2 kΩ
-
+3.3 V
25
26
16
15
+8 V to +9V
+8 V to +9V
10 µF
0.1 µF
0.1 µF
10 µF
-8 V to -9V
-8 V to -9V
Note:
Resistors are required for
I²C control port operation.
Figure 3. Typical Connection Diagram
12
DS693F1
CS3318
4. DETAILED BLOCK DIAGRAM
Zero Crossing Detector
IN1 1
0 ~ -96 dB
VA+ 45
+
_
RIN
VA- 46
ROUT
47
OUT1
48
REFO1
44
OUT2
43
REFO2
37
OUT3
38
REFO3
34
OUT4
33
REFO4
8
ENOut
10
VD
9
DGND
27
OUT5
28
REFO5
24
OUT6
23
REFO6
17
OUT7
18
REFO7
14
OUT8
13
REFO8
REFI1 2
0 ~ +22 dB
Zero Crossing Detector
IN2 42
0 ~ -96 dB
+
_
RIN
ROUT
REFI2 41
0 ~ +22 dB
Zero Crossing Detector
IN3 39
0 ~ -96 dB
VA+ 35
+
_
RIN
VA- 36
ROUT
REFI3 40
0 ~ +22 dB
Zero Crossing Detector
IN4 32
0 ~ -96 dB
RIN
+
_
ROUT
REFI4 31
0 ~ +22 dB
Ch. 4
Ch. 3
Ch. 2
Ch. 1
Control Control Control Control
RESET 3
SDA/MOSI 6
Control Registers
SCL/CLLK 5
AD0/CS 7
Ch. 8
Ch. 7
Ch. 6
Ch. 5
Control Control Control Control
MUTE 4
Zero Crossing Detector
IN5 29
0 ~ -96 dB
VA+ 25
VA-
+
_
RIN
26
ROUT
REFI5 30
0 ~ +22 dB
Zero Crossing Detector
IN6 22
0 ~ -96 dB
+
_
RIN
ROUT
REFI6 21
0 ~ +22 dB
Zero Crossing Detector
IN7 19
0 ~ -96 dB
VA+ 15
VA-
+
_
RIN
16
ROUT
REFI7 20
0 ~ +22 dB
Zero Crossing Detector
IN8 12
0 ~ -96 dB
RIN
+
_
ROUT
REFI8 11
0 ~ +22 dB
Refer to the Analog Characteristics
table on page 8 for the specified
values of RIN and ROUT.
DS693F1
Figure 4. Detailed Block Diagram
13
CS3318
5. APPLICATIONS
5.1
General Description
The CS3318 is an 8-channel digitally controlled analog volume control designed for audio systems. It incorporates a total adjustable range of 118 dB in ¼ dB steps, spread evenly over 96 dB of attenuation and
22 dB of gain.
The internal analog architecture includes one op-amp per channel, each with an input resistor network for
attenuation and a feedback resistor network for gain. Analog switch arrays are used to select taps in the
input and feedback resistor networks, thereby setting the gain or attenuation of each channel. These switch
arrays are controlled via the digital control port, bridging the gap between the analog and digital domains.
Figure 4 on page 13 provides a detailed diagram of the CS3318’s internal architecture.
The CS3318 incorporates highly configurable zero-crossing detection for glitch-free volume level changes.
Volume changes may be configured to occur immediately or on a signal zero-crossing. In the event that the
signal does not cross zero, the CS3318 provides 8 selectable time-out periods in the range of 5 ms to 50 ms
after which the volume level will be changed immediately. When the CS3318 receives more than one volume change command before a zero-crossing or a time-out, the CS3318 is able to implement the previous
volume change command immediately or discard it and act only on the most recent command. The “ZeroCrossing Detection” section on page 22 provides a detailed description of the CS3318’s zero-crossing detection functionality and controls.
The CS3318 includes a comprehensive I²C/SPI serial control port interface for volume changes and device
configuration. This interface provides for easy system integration of up to 128 CS3318 devices over a single
2-wire I²C or 3-wire SPI bus, allowing many channels of volume control with minimal system controller I/O
requirements. Devices may be addressed on an individual and grouped basis, simplifying simultaneous
configuration of a group of channels across multiple devices, while allowing discrete control over all channels on an individual basis. The “System Serial Control Configuration” section on page 23 provides a detailed description of the serial control port features and functionality.
5.2
System Design
Very few external components are required to support the CS3318. Typical power supply decoupling components are the only external requirements, as shown in Figure 3 on page 12.
5.2.1
Analog Inputs
No external circuitry is required to interface between the audio source and the CS3318’s inputs. However,
as with any adjustable gain stage, the affects of a DC offset at the input must be considered. Capacitively
coupling the analog inputs may be required to prevent “clicks and pops” which occur with gain changes if
an appreciable offset is present.
The addition of an input coupling capacitor will form a high-pass filter with the CS3318’s input impedance.
Given nominal values of input impedance and coupling capacitor, a 10 µF coupling capacitor will result in
less than 0.03 dB of attenuation at 20 Hz. If additional low-frequency attenuation can be tolerated, a smaller coupling capacitor may be used.
The CS3318 requires a low source impedance to achieve maximum performance, and a source-impedance of 600 Ω or less is recommended.
The maximum input level is limited by the input signal swing capability of the internal op-amp. Signals approaching the analog supply voltages may be applied to the analog input pins if the internal attenuator
limits the output signal to within 1.35 V of the analog supply rails.
14
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CS3318
5.2.2
Analog Outputs
The analog outputs are capable of driving 2 kΩ loads to within 1.35 V of the analog supply rails and are
short-circuit protected to 20 mA.
The minimum output load resistance is 2 kΩ; a load smaller than 2 kΩ may cause increased distortion.
As the load resistance decreases, the potential for increased internal heating and the possibility of damage to the device is introduced. Additionally, the load capacitance should be less than 100 pF. Increased
load capacitance may cause increased distortion, and the potential for instability in the output amplifiers.
If a low-impedance or high-capacitance load must be driven, an external amplifier should be used to isolate the outputs of the CS3318.
5.2.3
Recommended Layout, Grounding, and Power Supply Decoupling
As with any high-performance device that contains both analog and digital circuitry, careful attention must
be provided to power supply and grounding arrangements to optimize performance. Figure 3 on page 12
shows the recommended power arrangements, with VA+, VA-, and VD connected to clean supplies.
Power supply decoupling capacitors should be placed as near to the CS3318 as possible, with the low
value ceramic capacitor being the nearest. Care should be taken to ensure that there is minimal resistance in the analog ground leads to the device to prevent any changes in the defined gain/attenuation settings. The use of a unified ground plane is recommended for optimal performance and minimal radiated
noise. The CS3318 evaluation board demonstrates the optimum layout and power supply arrangements.
Should the printed circuit board have separate analog and digital regions with independent ground planes,
the CS3318 should reside in the analog region of the board.
Extensive use of ground plane fill on the circuit board will yield large reductions in radiated noise effects.
5.3
Power-Up and Power-Down
The CS3318 will remain in a completely powered-down state with the control port inaccessible until the RESET pin is brought high. Once RESET is high, the control port will be accessible, but the internal amplifiers
will remain powered-down until the PDN_ALL bit is cleared.
To bring a channel out of power-down, both the PDN_ALL and the channel’s PDNx bit must be cleared. By
default, all channels’ PDNx bits are cleared, and the PDN_ALL bit is set. To minimize audible artifacts during
power-up process, the CS3318 automatically holds each channel’s volume at mute until its amplifier has
completed its power-up sequence. Once the power-up process is complete, each channel’s volume will automatically be set to the correct level according to the CS3318’s control port settings.
To place a channel in power-down, either the channel’s PDNx bit or the PDN_ALL bit must be set. To minimize audible artifacts during the power-down process, the CS3318 automatically places each channel in
mute before the amplifier begins its power-down sequence.
The power-up and power-down muting/volume changes are implemented as dictated by the zero-crossing
detection settings (see “Zero-Crossing Detection” on page 22). If an immediate power-up or power-down is
required, the zero-crossing mode should be set to immediate before changing the power-down state of the
device or channel.
Referenced Control
Register Location
PDN_ALL ............................ “Power Down All (Bit 0)” on page 35
PDNx................................... “Channel Power - Address 0Dh” on page 35
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15
CS3318
5.3.1
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable. In this state, the control port is reset to its default
settings.
2. Bring RESET high. The device will remain in a low power state with the PDN_ALL bit set by default.
The control port will be accessible.
3. The desired register settings can be loaded while the PDN_ALL bit remains set.
4. Clear the PDN_ALL bit to initiate the power-up sequence.
5.3.2
Recommended Power-Down Sequence
1. Set the PDN_ALL bit to mute all channels and power-down all internal amplifiers.
2. If desired, hold RESET low to bring the CS3318’s power consumption to an absolute minimum.
16
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CS3318
5.4
Volume & Muting Control Architecture
The CS3318’s volume and muting control architecture provides the ability to control each channel on an
individual and master basis.
Individual control allows the volume and mute state of a single channel to be changed independently from
all other channels within the device. The CS3318 provides 8 individual volume and muting controls, each
permanently assigned to one channel within the device.
Master control allows the volume and mute state of multiple channels to be changed simultaneously with a
single register write. The CS3318 provides three master controls, and each may be configured to affect any
group of channels within a device.
Refer to the “Volume Controls” section beginning on page 19 and the “Muting Controls” section beginning
on page 21 for an in-depth description of the operation of the available controls.
5.4.1
Control Mapping Matrix
Figure 5 shows a conceptual drawing of the CS3318’s internal control-to-channel mapping matrix. Notice
that the individual channel controls are fixed to their respective channel, and the master controls may be
configured to affect any or all channels within the device.
Each master control has a corresponding Master X Mask register which allows the user to select which
channels are affected by the control. By default, each master control is configured to affect all channels
within the device. Referring to Figure 5 below, each configurable connection shown may be made and
broken by setting or clearing its corresponding bit in the control’s Master X Mask register.
The contents of the Master X Mask registers determine which channels are affected by both a master control’s volume and mute settings. Refer to the “Volume & Muting Control Implementation” section on
page 18 for a complete diagram of the CS3318’s volume and muting control architecture.
Volume & Muting
Controls
Control Mapping Matrix
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Master 1
Master 2
Master 3
Analog
Gain/Attenuation
Stages
Ch. 1
Ch. 2
Fixed Connection
Ch. 3
Ch. 4
Ch. 5
Ch. 6
Ch. 7
Ch. 8
Configurable Connection
Figure 5. CS3318 Control Mapping Matrix
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17
CS3318
Combining the multiple group addressing capabilities of the CS3318 (as detailed in section 5.8.2 on
page 24) with the internal master control mapping abilities described above allows the configuration and
direct addressing of multiple logical groups of channels across multiple CS3318 devices within a system.
Referenced Control
Register Location
Master X Mask .................... “Master 1 Mask - Address 10h” on page 36
“Master 2 Mask - Address 13h” on page 37
“Master 3 Mask - Address 16h” on page 38
5.4.2
Volume & Muting Control Implementation
Figure 6 below diagrams in detail the volume and muting control architecture of the CS3318 for an arbitrary channel ‘N’.
This diagram incorporates all volume and muting control concepts presented in sections 5.4 - 5.6; it is
included as a reference and will serve to corroborate the information presented in these sections.
Master 1 - Volume
Ch. N - Volume
Register N
Ch. N - ¼ dB Control
Σ
Register 10h, Bit N-1
Ch. N Master 2 Mask
Register 13h, Bit N-1
Master 1 - ¼ dB
Register 12h, Bit 0
Mask 1
Register 09h, Bit N-1
Ch. N Master 1 Mask
Register 11h
Σ
Σ
Master 2 - Volume
Mask 1
Register 14h
Σ
Σ
Master 2 - ¼ dB
Register 15h, Bit 0
Mask 2
Mask 2
Master 3 - Volume
Ch. N Master 3 Mask
Register 16h, Bit N-1
Mask 3
Register 17h
Σ
Σ
Master 3 - ¼ dB
Register 18h, Bit 0
Mask 3
Mute if result is
less than -96 dB.
Limit Volume Result
Master 1 - Mute
-96 dB to +22 dB
Register 12h, Bit 1
Mask 1
Hardware Mute Input
Master 2 - Mute
Pin 4
Register 15h, Bit 1
Mute
Mute Input Enable
Mask 2
Register 0Bh, Bit 5
Master 3 - Mute
Register 18h, Bit 1
Channel N - Mute
Register 0Ah, Bit N-1
Mask 3
Input
+
Output
_
Channel N
REFI
REFO
Figure 6. Volume & Muting Control Implementation
18
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CS3318
5.5
Volume Controls
The CS3318 provides comprehensive volume control functionality, allowing each channel’s volume to be
changed on an individual or master basis. Refer to the “Volume & Muting Control Architecture” section on
page 17 for complete details about the configuration of the CS3318’s individual and master controls.
The CS3318 incorporates zero-crossing detection capabilities, and all volume changes are implemented as
dictated by the zero-crossing detection settings (see “Zero-Crossing Detection” on page 22).
5.5.1
Individual Channel Volume Controls
The CS3318 provides 8 individual channel volume controls. These controls can be used to independently
gain and/or attenuate each of the input/output channels over a range of +22 dB to -96 dB in ¼ dB steps.
Each channel has a corresponding Ch. X Volume register used to gain or attenuate the channel from
+22 dB to -96 dB in ½ dB steps. The ¼ dB Control register contains one bit per channel used to add an
additional ¼ dB gain to the channel’s volume as set by its Ch. X Volume register.
Referenced Control
Register Location
Ch. X Volume ...................... “Ch 1-8 Volume - Addresses 01h - 08h” on page 31
¼ dB Control ....................... “¼ dB Control - Address 09h” on page 32
5.5.2
Master Volume Controls
The CS3318 master volume controls allow the user to simultaneously gain or attenuate a user defined set
of channels from +22 dB to -96 dB in ¼ dB increments. A total of 3 master volume controls, Master 1,
Master 2, and Master 3, are provided for comprehensive and flexible control.
Each master volume control has a corresponding Master X Volume register which is used to gain or attenuate the control’s respective unmasked channels from +22 dB to -96 dB in ½ dB steps. The LSB of the
corresponding Master X Control register contains one bit used to add an additional ¼ dB gain to the master volume control’s value as set by its Master X Volume register.
As discussed in the “Volume & Muting Control Architecture” section on page 17, each master volume control has a corresponding Master X Mask register which allows the user to select which channels are affected by the control. By default, each master control is configured to affect all channels within the device.
The effective volume setting of an individual channel is determined by the following equation:
EffVolChN = IndividualChN + (Master 1 & Mask 1ChN) + (Master 2 & Mask 2ChN) + (Master 3 & Mask 3ChN)
Equation 1. Effective Volume Setting
In this equation, EffVolChN represents the actual gain or attenuation level, in dB, of the individual channel
“N” as determined by the its constituent volume settings within the CS3318. The effective volume is limited
to the range of +22 dB to -96 dB; see “Volume Limits” on page 20.
IndividualChN is the individual channel volume setting in dB as set by the channel’s individual volume control register and ¼ dB bit (see “Individual Channel Volume Controls” on page 19).
Master X is the Master X volume setting in dB as set by the master volume control registers and their respective ¼ dB bits.
Mask XChN is the channel N mask bit associated with the Master X volume control setting.
This volume control architecture in combination with the multiple group addressing capabilities of the
CS3318 (as detailed in section 5.8.2 on page 24) allows easy volume control of multiple channels across
multiple devices in a system while eliminating the system controller overhead typically associated digitally
driven analog volume control devices.
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19
CS3318
Table 1 shows example volume settings using individual and master volume controls.
IndividualChX Master 1
Channel 1
+3.75 dB
Mask 1ChX
Master 2
Mask 2ChX
0
Master 3
0
Mask 3ChX
LevelChX
0
+3.75 dB
Channel 2
+2.5 dB
0
0
1
-6.0 dB
Channel 3
+1.25 dB
0
1
0
+6.5 dB
Channel 4
0 dB
Channel 5
-1.25 dB
+1.0 dB
0
1
+5.25 dB
1
0
-8.5 dB
1
-3.25 dB
0
-0.25 dB
Channel 6
-2.5 dB
1
0
1
-10.0 dB
Channel 7
-3.75 dB
1
1
0
+2.5 dB
Channel 8
-4.0 dB
1
1
1
-6.25 dB
Table 1. Example Volume Settings
Refer to Figure 6 on page 18 for a graphical representation of the volume controls’ functionality.
Referenced Control
Register Location
Master X Volume................. “Master 1 Volume - Address 11h” on page 36
“Master 2 Volume - Address 14h” on page 37
“Master 3 Volume - Address 17h” on page 38
Master X Control ................. “Master 1 Control - Address 12h” on page 37
“Master 2 Control - Address 15h” on page 38
“Master 3 Control - Address 18h” on page 39
Master X Mask .................... “Master 1 Mask - Address 10h” on page 36
“Master 2 Mask - Address 13h” on page 37
“Master 3 Mask - Address 16h” on page 38
5.5.3
Volume Limits
The analog section of the CS3318 is designed to accommodate gain and attenuation over the range of
+22 dB to -96 dB. Values outside this range may, however, be written to the CS3318’s internal registers.
As shown in Figure 6 on page 18, the value of the Individual and Master volume control registers are
summed before being limited to the range allowed by the CS3318’s analog section. This architecture has
the benefit of allowing both individual and master volume control input beyond the analog range of the
CS3318.
If the effective volume (See Equation 1 on page 19) of an individual channel is greater than +22 dB, the
channel’s volume will be set to +22 dB.
If the effective volume of an individual channel is less than -96 dB, the channel will mute, but the MuteChX
bit will not be set. When the channel’s effective volume returns to -96 dB or above, the mute condition will
be released. It should be noted that if the channel’s MuteChX bit or any of the channel’s unmasked
Master X Mute bits are set, the channel will remain muted until the necessary mute conditions are released.
Referenced Control
Register Location
MuteChX ............................. “Mute Control - Address 0Ah” on page 33
Master X Mute..................... “Master 1 Mute (Bit 1)” on page 37
“Master 2 Mute (Bit 1)” on page 38
“Master 3 Mute (Bit 1)” on page 39
20
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CS3318
5.6
Muting Controls
The CS3318 provides flexible muting capabilities to complement its comprehensive volume control abilities.
Each channel’s mute state may be controlled on an individual channel basis, by any of 3 master mute controls, and by the hardware MUTE input pin.
The mute state of any channel within the CS3318 is determined by the logical OR of four conditions, and
the channel will mute if any one or more of the conditions are met. These conditions are:
1.
2.
3.
4.
The channel’s individual mute condition is set.
One or more of the channel’s unmasked master mute conditions are set.
The hardware mute input is enabled and active.
The channel’s effective volume (See Equation 1 on page 19) is less than -96 dB.
The CS3318 incorporates zero-crossing detection capabilities, and all muting changes are implemented as
dictated by the zero-crossing detection settings (see “Zero-Crossing Detection” on page 22).
5.6.1
Individual Channel Mute Controls
The CS3318 provides 8 individual channel mute controls. These controls can be used to individually mute
each of the input/output channels independent of all other volume and mute settings.
Individual channel mute control is accomplished by setting or clearing the channel’s corresponding
MuteChX bit in the Mute Control register.
Referenced Control
Register Location
MuteChX ............................. “Mute Control - Address 0Ah” on page 33
5.6.2
Master Mute Controls
The CS3318 master mute controls allow the user to simultaneously control the mute state of all channels,
or a user-defined subset of all channels within a device. A total of 3 master mute controls, M1_Mute,
M2_Mute, and M3_Mute, are provided for comprehensive and flexible control.
Master mute control is accomplished by setting or clearing the MX_Mute bit in the corresponding Master
Control register. Each master mute control affects only those channels unmasked in its corresponding
Master X Mask register.
Register Location
Referenced Control
MX_Mute............................. “Master 1 Mute (Bit 1)” on page 37
“Master 2 Mute (Bit 1)” on page 38
“Master 3 Mute (Bit 1)” on page 39
Master X Mask .................... “Master 1 Mask - Address 10h” on page 36
“Master 2 Mask - Address 13h” on page 37
“Master 3 Mask - Address 16h” on page 38
5.6.3
Hardware Mute Control
The CS3318 implements a hardware MUTE input pin to allow the user to control the mute state of all channels with an external level-active signal. By default, the MUTE input is configured for active low operation,
and all channels will be held in a mute state whenever this input is low.
For enhanced flexibility, setting the MutePolarity bit will configure the MUTE input pin for active high operation. Additionally, the EnMuteIn bit may be cleared to disable the CS3318’s response to the MUTE input signal.
Referenced Control
Register Location
MutePolarity ........................ “MUTE Input Polarity (Bit 4)” on page 33
EnMuteIn............................. “Enable MUTE Input (Bit 5)” on page 33
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CS3318
5.7
Zero-Crossing Detection
The CS3318 incorporates comprehensive zero-crossing detection features to provide for noise-free level
transitions. Three zero-crossing detection modes and 8 selectable time-out periods are available for enhanced flexibility. Zero-crossing detection and time-out is implemented independently for each channel.
5.7.1
Zero-Crossing Modes
The zero-crossing mode for all channels within the CS3318 are configured via the ZCMode[1:0] bits in the
Device Config 2 register. By default, zero-crossing mode 1 is selected. The zero-crossing modes are detailed in Table 2.
Mode
Zero-Crossing Function
0
Volume changes take effect immediately.
1
Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected before the timeout period has elapsed, the volume change will be implemented immediately when the time-out period
elapses. If the volume setting is changed again before the original volume change has been implemented, the original change will be discarded, the time-out period will be reset, and the new volume setting will take effect when a zero-crossing is detected or the time-out period elapses.
2
Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected before the timeout period has elapsed, the volume change will be implemented immediately when the time-out period
elapses. If the volume setting is changed again before the original volume change has been implemented, the original volume change will be implemented immediately upon reception of the new volume
change command, the time-out period will be reset, and the new volume setting will take effect when a
zero-crossing is detected or the time-out period elapses.
Table 2. Zero-Crossing Modes
Referenced Control
Register Location
ZCMode[1:0] ....................... “Zero-Crossing Mode (Bits 1:0)” on page 35
5.7.2
Zero-Crossing Time-Out
When in zero-crossing mode 1 or 2, the zero-crossing time-out period dictates how long the CS3318 will
wait for a signal zero-crossing before implementing the requested volume change without a zero-crossing, thereby allowing the possibility of audible artifacts. The CS3318 provides 8 selectable time-out periods ranging from 5 ms to 50 ms; these are shown in Table 3.
Time-Out Setting
Time-Out Period
0
5 ms
1
10 ms
2
15 ms
3
18 ms
4
20 ms
5
30 ms
6
40 ms
7
50 ms
Table 3. Zero-Crossing Time-Out Periods
The zero-crossing time-out period for all channels within the CS3318 is configured via the TimeOut[2:0]
bits in the Device Config 2 register. The time-out period is set to 18 ms (setting 3) by default.
Referenced Control
Register Location
TimeOut[2:0] ....................... “Zero-Crossing Time-Out Period (Bits 4:2)” on page 34
22
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CS3318
5.8
System Serial Control Configuration
The CS3318 includes a comprehensive serial control port which supports both SPI and I²C modes of communication (See the “I²C/SPI Serial Control Formats” section on page 27). The control port uses the shared
serial control bus to define each device’s slave address. This allows independent control of up to 128 devices on the shared serial control bus without requiring hardware device address configuration pins or any
more than one CS signal (for SPI mode).
Each device will respond to three different chip addresses; Individual, Group 1, and Group 2. The device’s
Individual chip address provides read and write access to the CS3318’s internal registers. The device’s
Group 1 and Group 2 addresses provide write-only access to the CS3318’s internal registers. If a read operation is requested using either the Group 1 or Group 2 address, the devices will not respond to the request. Upon the release of RESET, each of these device addresses initializes to the default address. In this
state, the device will respond to both register reads and writes when addressed with this default address.
Each of the device’s addresses may be changed via a standard serial register write to an internal register
of the CS3318. Using this method, each device may be assigned a unique Individual address, and groups
of devices may be assigned shared Group 1 and Group 2 addresses for simultaneous control. Use of the
master volume and mute controls in combination with the available group addresses provides for easy master and sub-master control within a multiple CS3318 system.
Referenced Control
Register Location
Individual Address............... “Individual Chip Address 1Bh” on page 41
Group 1 Address ................. “Group 1 Chip Address 1Ah” on page 40
Group 2 Address ................. “Group 2 Chip Address 19h” on page 40
5.8.1
Serial Control within a Single-CS3318 System
In a single CS3318 system, no special attention must be given to the serial control port operation of the
CS3318. The standard serial control signals (SDA and SCL for I²C Mode, or MOSI, CCLK, and CS for SPI
Mode) should be connected to the system controller, and the ENOut signal is not used (see
Figures 7 and 8). Upon the release of RESET, the CS3318 must be addressed with its default chip address.
Although it is not necessary, the default Individual, Group 1, and Group 2 chip addresses may be changed
by writing their respective control port registers. Once the contents of these registers has been modified,
the device must be addressed with the registers’ new contents. When the device is reset, its device addresses will return to their default value.
CCLK
SDA
CS
SCL
SCL
μC
RST
CS
SDA
Reset
μC
ENout
RST
CCLK
ENout
Reset
MOSI
MOSI
Figure 7. Standard I²C Connections
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Figure 8. Standard SPI Connections
23
CS3318
5.8.2
Serial Control within a Multiple-CS3318 System
The CS3318 allows both independent and simultaneous control of up to 128 devices on a shared I²C or
SPI serial control bus. The address of each device is configured by the host controller via the shared serial
control bus. All serial communication, including the configuration of each device’s address, adheres to a
standard I²C or SPI bus protocol.
A device’s Individual device address, which provides read and write access to the device’s internal registers, should be set to a unique value, different from all other addresses recognized by devices on the serial
communication bus. This address facilitates independent control of each CS3318 on the serial control
bus.
A device’s Group 1 and Group 2 addresses, which provide write-only access to the device’s internal registers, may be set to the same value across multiple CS3318’s on the shared serial communication bus.
Assigning common Group addresses to multiple devices in a system allows system sub-master and system master volume control. For instance, a system containing 8 CS3318’s may configure the Group 1 address of the first set of 4 CS3318’s to 10h, the Group 1 address of the second set of 4 CS3318’s to 20h,
and the Group 2 address of all 8 CS3318’s to A0h. In this manner, a serial control data write to address
10h would act as a system sub-master control to the first set of 4 devices, a write to 20h would act as a
system sub-master control to the second set of 4 devices, and a write to A0h would act as a system master control to all devices.
By default, the CS3318 will not respond to serial communication when addressed with its Group 1 or
Group 2 address. The CS3318 will only respond to one or both of these addresses if the corresponding
address has been enabled via the control port. To enable a Group address, its corresponding Enable bit,
located in the LSB of its respective Group address register, must be set.
The CS3318 implements an ENOut signal to facilitate the device address configuration process. This signal is used to hold all but one un-configured device in a reset state. After the Individual device address of
each device has been set, the ENOut signal is used to enable the “next” device in the chain, allowing its
Individual device address to be set. See “SPI Mode Serial Control Configuration” section on page 24 and
“I²C Mode Control Configuration” on page 26 for more information about system configuration in each
communication mode.
5.8.2.1
SPI Mode Serial Control Configuration
Up to 128 CS3318’s sharing the same CS signal may be connected to a common SPI serial control bus.
This shared serial bus is used to assign a unique device address to each device on the bus such that they
may be independently addressed. To implement this method of device address configuration, the devices
must be connected as shown in Figure 9.
CCLK
CS
CS
μC
RST
RESET
CCLK
Device 1
MOSI
CS
ENout
RESET
CCLK
Device 2
CS
ENout
MOSI
RESET
CCLK
Device 3
ENout
MOSI
MOSI
Figure 9. SPI Serial Control Connections
Note that the serial control signals CCLK, CS, and MOSI are connected in parallel to each CS3318. The
active low reset output of the system controller is connected to the RESET input of the first CS3318 in the
chain. The ENOut of the first device is connected to the RESET input of the second CS3318 whose ENOut
signal is connected to the third CS3318. This pattern of connecting the ENOut of device N to the RESET
24
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CS3318
input of device N+1 may be repeated for up to 128 devices per single CS signal. If more than 128 devices
are required in a system, separate CS signals may be used to create additional chains of up to 128 devices
per CS signal.
As each device is placed into reset (RESET is low), its ENOut signal is driven low. The ENOut signal will
continue to be driven low until the device is taken out of reset (RESET is high) and the Enable bit (see “Enable Next Device (Bit 0)” on page 41) is set, at which time the ENOut signal will be driven high.
To configure a unique Individual device address for each device on the shared serial bus, the first device
must be reset (a low to high transition on its RESET pin), the Individual device address register must be
written (using the CS3318’s default device address) with a unique device address, and the Enable bit must
be set to take the next device in the serial control chain out of reset. This process may be repeated until all
devices in the serial control chain have been assigned a new Individual device address. Figure 10 diagrams this configuration process.
Start
Apply System Power
Reset the First Device
in the Chain
This loop steps through the
devices in a chain, setting a
unique Individual chip adress
for each device as it
progresses.
At this point, the chip addresses of each
device are set to their default value. The
ENout pin on each device is low, holding
each subsequent device in a reset state.
Using the default chip address,
perform a write cycle to change the
Individual chip address register to a
unique value.
From this point forward, the device will only
respond to register reads and writes when
addressed with this new Individual device address.
A device will also respond to register writes when
addressed with its Group 1 or Group 2 address.
Optionally, device configuration (initial
volume settings, Group addresses,
etc.) may be implemented using the
new Individual device address.
Using the new Individual chip address,
perform a write cycle to set the Enable
bit.
No
Have all the devices in the
chain been assigned a unique
chip address?
This will cause the device's
ENout pin to be driven high,
bringing the next device in the
chain out of its reset state.
Yes
Each device may now be
independently adressed through the
serial bus using the device's assigned
unique chip address.
The Reset input pins of all devices in the chain are
now high. The serial control interface will
communicate with each device in parallel, but each
device will only respond when the first byte clocked
in on the serial control bus matches its Individual,
Group 1 or Group 2 address. If the first byte
clocked in does not match the one of the device's
chip addresses, the device will ignore all
subsequent traffic on the bus until a new
communication cycle is initiated.
Figure 10. Individual Device Address Configuration Process
Notice that Figure 10 shows the setting of the Individual address and the setting of the Enable bit as two
discrete steps. While this demonstrates one approach to device configuration, it should be noted that two
steps are not necessary to complete the action of setting the Individual address and enabling the next device. This may be done simultaneously with one register write (containing the new Individual address and
the Enable bit set) to the Individual address register.
DS693F1
25
CS3318
Once this configuration process is complete, every device may be independently controlled with a standard
SPI communication cycle using the device’s newly assigned Individual device addresses.
5.8.2.2
I²C Mode Control Configuration
Up to 128 CS3318’s may be connected to a common I²C serial control bus. This shared serial bus is used
to assign a unique device address to each device on the bus such that they may be independently addressed. To implement this method of device address configuration, the devices must be connected as
shown in Figure 11.
SDA
SCL
SCL
μC
RST
RESET
SDA
Device 1
SCL
ENout
RESET
SDA
Device 2
SCL
ENout
RESET
SDA
Device 3
ENout
Figure 11. I²C Serial Control Connections
Note that the serial control signals SCL and SDA are connected in parallel to each CS3318. The active low
reset output of the system controller is connected to the RESET input of the first CS3318 in the chain. The
ENOut of the first device is connected to the RESET input of the second CS3318 whose ENOut signal is
connected to the third CS3318. This pattern of connecting the ENOut of device N to the RESET input of
device N+1 may be repeated for up to 128 devices per common I²C bus. If more than 128 devices are required in a system, separate SDA or SCL signals may be used to create additional chains of up to 128 devices.
As each device is placed into reset (RESET is low), its ENOut signal is driven low. The ENOut signal will
continue to be driven low until the device is taken out of reset (RESET is high) and the Enable bit (see “Enable Next Device (Bit 0)” on page 41) is set, at which time the ENOut signal will be driven high.
To configure a unique Individual device address for each device on the shared serial bus, the first device
must be reset (a low to high transition on its RESET pin), the Individual device address register must be
written (using the CS3318’s default device address) with a unique device address, and the Enable bit must
be set to take the next device in the serial control chain out of reset. This process may be repeated until all
devices in the serial control chain have been assigned a new Individual device address. Figure 10 diagrams this configuration process.
Notice that Figure 10 shows the setting of the Individual address and the setting of the Enable bit as two
discrete steps. While this demonstrates one approach to device configuration, it should be noted that two
steps are not necessary to complete the action of setting the Individual address and enabling the next device. This may be done simultaneously with one register write (containing the new Individual address and
the Enable bit set) to the Individual address register.
Once the configuration process is complete, every device may be independently controlled with a standard
I²C communication cycle using the device’s newly assigned Individual device addresses.
26
DS693F1
CS3318
5.9
I²C/SPI Serial Control Formats
The control port is used to access the internal registers of the CS3318. The control port has 2 modes: SPI
and I²C, with the CS3318 acting as a slave device. SPI Mode is selected if there is a high-to-low transition
on the CS pin after the RESET pin has been brought high. I²C Mode is selected by connecting the CS pin
to VD or DGND.
5.9.1
I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the CS3318 by the clock,
SCL. The AD0 pin sets the least significant bit of the default chip address and must be connected to VD
or DGND. The AD0 pin is read upon the release of the RESET signal (a low-to-high transition), and its
value (‘0’ when connected to DGND, ‘1’ when connected to VD) is reflected in the LSB of the chip address
in the Individual, Group 1, and Group 2 Chip Address registers. Table 4 shows the default chip addresses
in I²C Mode.
AD0 Connection
Default Chip Address
DGND
1000000b
VD
1000001b
Table 4. I²C Mode Default Chip Address
The signal timings for a read and write cycle are shown in Figure 12 and Figure 13. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low.
The first byte sent to the CS3318 after a Start condition consists of a 7-bit chip address field and a R/W
bit (high for a read, low for a write). To communicate with a CS3318, the chip address field should match
either the Individual, Group 1, or Group 2 device address as set by their respective control port registers.
The eighth bit of the address is the R/W bit. If the read/write bit is set high (indicating a read operation)
and the preceding 7 bits do not match its Individual address, the CS3318 will ignore all traffic on the I²C
bus until a Stop and Start condition occurs.
If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register
to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be
output.
There is a MAP auto-increment capability, enabled by the INCR bit (the MSB of the MAP byte). If INCR
is ‘0’, the MAP will stay constant for successive read or writes. If INCR is ‘1’, the MAP will automatically
increment after each byte is written, allowing block writes of successive registers. Each byte is separated
by an acknowledge (ACK) bit. The ACK bit is output from the CS3318 after each input byte is read and is
input to the CS3318 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
MSB
Chip Address
LSB
MAP BYTE
0
INCR
ACK
6
5
4
3
2
1
0
7
6
1
DATA +n
DATA +1
DATA
0
ACK
START
7
ACK
6
1
0
7
6
1
0
ACK
STOP
Figure 12. Control Port Timing, I²C Write
DS693F1
27
CS3318
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
MSB
Chip Address
LSB
STOP
MAP BYTE
0
INCR
6
5
4
3
2
1
CHIP ADDRESS (READ)
0
ACK
MSB
Chip Address
LSB
ACK
START
DATA
7
1
ACK
DATA +1
0
7
ACK
START
0
DATA + n
7
0
NO
ACK
STOP
Figure 13. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 13, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition.
Referenced Control
Register Location
Individual Address............... “Individual Chip Address 1Bh” on page 41
Group 1 Address ................. “Group 1 Chip Address 1Ah” on page 40
Group 2 Address ................. “Group 2 Chip Address 19h” on page 40
5.9.2
SPI Mode
In SPI Mode, CS is the CS3318 chip-select signal, CCLK, is the control port bit clock (input into the
CS3318 from the microcontroller), and MOSI is the input data line from the microcontroller. Data is
clocked in on the rising edge of CCLK. The default chip address in SPI Mode is 1000000b.
Figure 14 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on MOSI form the chip address and must be either the Individual, Group 1, or Group 2 chip
address as set by their respective control port registers. The eighth bit is a read/write indicator (R/W),
which must be low to write. If the read/write indicator is set high (indicating a read operation), the CS3318
will ignore all traffic on the SPI bus until CS is brought high and then low again. The next eight bits form
the Memory Address Pointer (MAP), which is set to the address of the register that is to be written. The
next eight bits are the data which will be placed into the register designated by the MAP.
There is a MAP auto increment capability, enabled by the INCR bit (the MSB of the MAP byte). If INCR is
‘0’, the MAP will stay constant for successive read or writes. If INCR is ‘1’, the MAP will automatically increment after each byte is written, allowing block writes of successive registers.
1 Byte
1 Byte
> 1 Byte
CS
CCLK
MOSI
MSB
Chip Address
LSB
W
INCR MSB
Memory Address Pointer
LSB
MSB
Data
LSB
Figure 14. SPI Write Cycle
Referenced Control
Register Location
Individual Address............... “Individual Chip Address 1Bh” on page 41
Group 1 Address ................. “Group 1 Chip Address 1Ah” on page 40
Group 2 Address ................. “Group 2 Chip Address 19h” on page 40
28
DS693F1
CS3318
6. CS3318 REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr
Function
01h Ch. 1 Volume
page 31
02h Ch. 2 Volume
page 31
03h Ch. 3 Volume
page 31
04h Ch. 4 Volume
page 31
05h Ch. 5 Volume
page 31
06h Ch. 6 Volume
page 31
07h Ch. 7 Volume
page 31
08h Ch. 8 Volume
page 31
09h ¼ dB Control
page 32
0Ah Mute Control
page 33
0Bh Device Config 1
page 33
0Ch Device Config 2
page 34
0Dh Channel Power
page 35
0Eh Master Power
page 35
0Fh Freeze Control
page 36
DS693F1
7
6
5
4
3
2
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
1
1
0
1
0
0
1
0
Quarter8
Quarter7
Quarter6
Quarter5
Quarter4
Quarter3
Quarter2
Quarter1
0
0
0
0
0
0
0
0
MuteCh8
MuteCh7
MuteCh6
MuteCh5
MuteCh4
MuteCh3
MuteCh2
MuteCh1
0
0
0
0
Reserved
Reserved
EnMuteIn MutePolarity
0
0
0
0
Ch8=7
Ch6=5
Ch4=3
Ch2=1
0
0
1
0
0
0
0
0
Reserved
Reserved
Reserved
TimeOut2
TimeOut1
TimeOut0
ZCMode1
ZCMode0
0
0
0
0
1
1
0
1
PDN8
PDN7
PDN6
PDN5
PDN4
PDN3
PDN2
PDN1
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PDN_ALL
0
0
0
0
0
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Freeze
0
0
0
0
0
0
0
0
29
CS3318
Addr
Function
10h Master 1 Mask
page 36
11h Master 1 Volume
page 36
12h Master 1 Control
page 37
13h Master 2 Mask
page 37
14h Master 2 Volume
page 37
15h Master 2 Control
page 38
16h Master 3 Mask
page 38
17h Master 3 Volume
page 38
18h Master 3 Control
page 39
19h Group 2 Chip
Addr
page 40
1Ah Group 1 Chip
Addr
page 40
1Bh Individual Chip
Addr
page 41
1Ch Chip ID
page 41
30
7
M1_Ch8M
6
5
M1_Ch7M M1_Ch6M
4
M1_Ch5M
3
2
1
0
M1_Ch4M M1_Ch3M M1_Ch2M M1_Ch1M
1
1
1
1
1
1
1
1
M1_Vol7
M1_Vol6
M1_Vol5
M1_Vol4
M1_Vol3
M1_Vol2
M1_Vol1
M1_Vol0
1
1
0
1
0
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1_Mute
M1_Qtr
0
0
0
0
0
0
0
0
M2_Ch8M
M2_Ch7M M2_Ch6M
M2_Ch5M
M2_Ch4M M2_Ch3M M2_Ch2M M2_Ch1M
1
1
1
1
1
1
1
1
M2_Vol7
M2_Vol6
M2_Vol5
M2_Vol4
M2_Vol3
M2_Vol2
M2_Vol1
M2_Vol0
1
1
0
1
0
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M2_Mute
M2_Qtr
0
0
0
0
0
0
0
0
M3_Ch8M
M3_Ch7M M3_Ch6M
M3_Ch5M
M3_Ch4M M3_Ch3M M3_Ch2M M3_Ch1M
1
1
1
1
1
1
1
1
M3_Vol7
M3_Vol6
M3_Vol5
M3_Vol4
M3_Vol3
M3_Vol2
M3_Vol1
M3_Vol0
1
1
0
1
0
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M3_Mute
M3_Qtr
0
0
0
0
0
0
0
0
G2_Addr6
G2_Addr5
G2_Addr4
G2_Addr3
G2_Addr2
G2_Addr1
1
0
0
0
0
0
G1_Addr6
G1_Addr5
G1_Addr4
G1_Addr3
G1_Addr2
G1_Addr1
1
0
0
0
0
0
Ind_Addr6
Ind_Addr5 Ind_Addr4
Ind_Addr3
G2_Addr0 EnG2Addr
X
0
G1_Addr0 EnG1Addr
X
Ind_Addr2 Ind_Addr1 Ind_Addr0
0
Enable
1
0
0
0
0
0
X
0
ID3
ID2
ID1
ID0
Rev3
Rev2
Rev1
Rev0
0
1
1
0
X
X
X
X
DS693F1
CS3318
7. CS3318 REGISTER DESCRIPTIONS
Notes:
1. When addressing the CS3318 with the Individual Chip Address, all registers are read/write in I²C Mode
and write-only in SPI Mode, unless otherwise noted.
2. When addressing the CS3318 with the Group Chip Addresses, all registers are write-only in both I²C
and SPI Mode.
7.1
Ch 1-8 Volume - Addresses 01h - 08h
7
Vol7
7.1.1
6
Vol6
5
Vol5
4
Vol4
3
Vol3
2
Vol2
1
Vol1
0
Vol0
Volume Control (Bits 7:0)
Default = 11010010
Function:
The individual volume control registers allow the user to gain or attenuate the respective channels in
0.5 dB increments. The volume changes are implemented as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device Configuration 2 - Address 0Ch” on
page 34).
The value of the Volume Control register is mapped to the desired 0.5 dB step volume setting by the
following equation:
Register Value = ( 2 × Desired Volume Setting in dB ) + 210
In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB
resolution volume setting down to ½ dB resolution.
It should be noted that input values outside the CS3318’s analog range of +22 dB to -96 dB are valid,
however, the volume of each channel will be limited to the CS3318’s analog range (see “Volume Limits” on page 20).
Register Setting
Gain or Attenuation (dB)*
11111110
+22
11111101
+21.5
11111100
+21
-
-
11010100
+1
11010011
+0.5
11010010
0
11010001
-0.5
11010000
-1
-
-
00010100
-95
00010011
-95.5
00010010
-96
* QuarterX = ‘0’. See “¼ dB Control (Bit 0 - 7)” on page 32.
Table 5. Example Volume Settings
DS693F1
31
CS3318
7.2
¼ dB Control - Address 09h
7
Quarter8
7.2.1
6
Quarter7
5
Quarter6
4
Quarter5
3
Quarter4
2
Quarter3
1
Quarter2
0
Quarter1
¼ dB Control (Bit 0 - 7)
Default = 0
Function:
When set, ¼ dB of gain will be added to each bit’s respective channel. The volume changes are implemented as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see
“Device Configuration 2 - Address 0Ch” on page 34).
It should be noted that input values outside the CS3318’s analog range of +22 dB to -96 dB are valid;
however, the volume of each channel will be limited to the CS3318’s analog range (see “Volume Limits” on page 20).
Table 6 shows example volume settings using the ¼ dB control.
Volume Control Register
Setting (Reg 01h - 08h)
Corresponding QuarterX
Bit Setting
Individual VolumeChX (dB)
11111110
0
+22
11111101
1
+21.75
11111101
0
+21.5
11111100
1
+21.25
11111100
0
+21
-
-
-
11010100
0
+1
11010011
1
+0.75
11010011
0
+0.5
11010010
1
+0.25
11010010
0
0
11010001
1
-0.25
11010001
0
-0.5
11010000
1
-0.75
11010000
0
-1
-
-
-
00010100
0
-95
00010011
1
-95.25
00010011
0
-95.5
00010010
1
-95.75
00010010
0
-96
Table 6. Example Volume Settings
32
DS693F1
CS3318
7.3
Mute Control - Address 0Ah
7
MuteCh8
7.3.1
6
MuteCh7
5
MuteCh6
4
MuteCh5
3
MuteCh4
2
MuteCh3
1
MuteCh2
0
MuteCh1
Mute Channel X (Bit 0 - 7)
Default = 0
Function:
Each bit controls the individual mute state of its respective channel. When set, the mute condition is
active. When cleared, the mute condition is released.
See “Muting Controls” on page 21 for more information about the muting behavior of the CS3318.
7.4
Device Configuration 1 - Address 0Bh (Bit 5)
7
Reserved
7.4.1
6
Reserved
5
EnMuteIn
4
MutePolarity
3
Ch8=7
2
Ch6=5
1
Ch4=3
0
Ch2=1
Enable MUTE Input (Bit 5)
Default = 1
Function:
When set, the MUTE input pin is enabled and will generate a mute condition when active. When
cleared, the MUTE input pin is ignored and will not generate a mute condition.
7.4.2
MUTE Input Polarity (Bit 4)
Default = 0
Function:
This bit controls the active level of the MUTE input pin.
When set, the mute condition is active when the MUTE pin is high. When cleared, the mute condition
is active when the MUTE pin is low.
DS693F1
33
CS3318
7.4.3
Channel B = Channel A (Bit 0 - 3)
Default = 0
Function:
When this bit is set, Channel A and Channel B volume levels and muting conditions are controlled by
the Channel A volume and muting register settings, and the Channel B register settings are ignored.
When this bit is cleared, Channel A and Channel B volume and mute settings are independently controlled by the A and B volume and muting bits.
Bit Name
Bit Setting
Ch8=7
0
Channel 7 and 8 mute and volume settings controlled independently
1
Channel 7 and 8 mute and volume settings controlled by Channel 7 register
settings. Channel 8 register settings are ignored.
0
Channel 5 and 6 mute and volume settings controlled independently
1
Channel 5 and 6 mute and volume settings controlled by Channel 5 register
settings. Channel 6 register settings are ignored.
0
Channel 3 and 4 mute and volume settings controlled independently
1
Channel 3 and 4 mute and volume settings controlled by Channel 3 register
settings. Channel 4 register settings are ignored
0
Channel 1 and 2 mute and volume settings controlled independently
1
Channel 1 and 2 mute and volume settings controlled by Channel 1 register
settings. Channel 2 register settings are ignored
Ch6=5
Ch4=3
Ch2=1
Control Configuration
Table 7. Channel B = Channel A Settings
7.5
Device Configuration 2 - Address 0Ch
7
Reserved
7.5.1
6
Reserved
5
Reserved
4
TimeOut2
3
TimeOut1
2
TimeOut0
1
ZCMode1
0
ZCMode0
Zero-Crossing Time-Out Period (Bits 4:2)
Default = 011
Function:
These bits set the zero-crossing time-out period as shown in Table 9. Refer to the “Zero-Crossing
Time-Out” section on page 22 for more information.
TimeOut[2:0]
Zero-Crossing
Time-Out Period
000
5 ms
001
10 ms
010
15 ms
011
18 ms
100
20 ms
101
30 ms
110
40 ms
111
50 ms
Table 8. Zero-Crossing Time-Out Settings
34
DS693F1
CS3318
7.5.2
Zero-Crossing Mode (Bits 1:0)
Default = 01
Function:
These bits control the Zero-Crossing detection mode as shown in Table 9. Refer to the “Zero-Crossing Modes” section on page 22 for more information.
ZCMode[1:0]
Zero-Crossing Mode
00
Volume changes take effect immediately.
01
Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected
before the period specified by the TimeOut[2:0] bits has elapsed, the volume change will be
implemented immediately when the time-out period elapses. If the volume setting is
changed again before the original volume change has been implemented, the original
change will be discarded, the time-out period will be reset, and the new volume setting will
take effect when a zero-crossing is detected or the time-out period elapses.
10
Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected
before the period specified by the TimeOut[2:0] bits has elapsed, the volume change will be
implemented immediately when the time-out period elapses. If the volume setting is
changed again before the original volume change has been implemented, the original volume change will be implemented immediately upon reception of the new volume change
command, the time-out period will be reset, and the new volume setting will take effect when
a zero-crossing is detected or the time-out period elapses.
11
Reserved
Table 9. Zero-Crossing Mode Settings
7.6
Channel Power - Address 0Dh
7
PDN8
7.6.1
6
PDN7
5
PDN6
4
PDN5
3
PDN4
2
PDN3
1
PDN2
0
PDN1
Power Down Channel X (Bit 0 - 7)
Default = 0
Function:
Each respective channel will enter a low-power state whenever this bit is set. A channel’s power-down
bit must be cleared for normal operation to occur.
7.7
Master Power - Address 0Eh
7
Reserved
7.7.1
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
PDN_ALL
Power Down All (Bit 0)
Default = 1
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default
and must be cleared before normal operation can occur. The control registers remain accessible, and
their contents are retained while the device is in power-down.
DS693F1
35
CS3318
7.8
Freeze Control - Address 0Fh
7
Reserved
7.8.1
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Freeze
Freeze (Bit 7)
Default = 0
Function:
When the Freeze bit is set, the Freeze function allows modifications to the control port registers without changes taking effect until Freeze bit is cleared. To make multiple changes in the Control Port
registers take effect simultaneously, set the Freeze bit, make all register changes, then clear the
Freeze bit.
7.9
Master 1 Mask - Address 10h
7
M1_Ch8M
6
M1_Ch7M
5
M1_Ch6M
4
M1_Ch5M
3
M1_Ch4M
2
M1_Ch3M
1
M1_Ch2M
0
M1_Ch1M
Each bit in this register serves as a Master 1 mask for its corresponding channel.
If a mask bit is set to ‘1’, the corresponding channel is unmasked, meaning that it will be affected by the
Master 1 volume and muting controls.
If a mask bit is set to ‘0’, the corresponding channel is masked, meaning that it will not be affected by the
Master 1 volume and muting controls.
This register defaults to FFh (all channels unmasked).
7.10
Master 1 Volume - Address 11h
7
M1_Vol7
6
M1_Vol6
5
M1_Vol5
4
M1_Vol4
3
M1_Vol3
2
M1_Vol2
1
M1_Vol1
0
M1_Vol0
7.10.1 Master 1 Volume Control (Bits 7:0)
Default = 11010010
Function:
The Master 1 volume control register allows the user to simultaneously gain or attenuate all unmasked channels in 0.5 dB increments. The volume changes are implemented as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device Configuration 2 Address 0Ch” on page 34).
The value of the Master 1 volume control register is mapped to the desired 0.5 dB step Master 1 volume setting by the following equation:
Register Value = ( 2 × Desired Volume Setting in dB ) + 210
In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB
resolution volume setting down to ½ dB resolution.
It should be noted that input values outside the CS3318’s analog range of +22 dB to -96 dB are valid,
however, the volume of each channel will be limited to the CS3318’s analog range (see “Volume Limits” on page 20).
See Table 5 on page 31 for example register settings.
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CS3318
7.11
Master 1 Control - Address 12h
7
Reserved
7.11.1
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
M1_Mute
0
M1_Qtr
Master 1 Mute (Bit 1)
Default = 0
Function:
This bit controls the Master 1 mute state. When set, the Master 1 mute condition is active. When
cleared, the Master 1 mute condition is released.
See “Muting Controls” on page 21 for more information about the muting behavior of the CS3318.
7.11.2
Master 1 ¼ dB Control (Bit 0)
Default = 0
Function:
When set, ¼ dB of gain will be added to the Master 1 volume level.
See Table 6 on page 32 for an example of volume settings using the ¼ dB control.
7.12
Master 2 Mask - Address 13h
7
M2_Ch8M
6
M2_Ch7M
5
M2_Ch6M
4
M2_Ch5M
3
M2_Ch4M
2
M2_Ch3M
1
M2_Ch2M
0
M2_Ch1M
Each bit in this register serves as a Master 2 mask for its corresponding channel.
If a mask bit is set to ‘1’, the corresponding channel is unmasked, meaning that it will be affected by the
Master 2 volume and muting controls.
If a mask bit is set to ‘0’, the corresponding channel is masked, meaning that it will not be affected by the
Master 2 volume and muting controls.
This register defaults to FFh (all channels unmasked).
7.13
Master 2 Volume - Address 14h
7
M2_Vol7
6
M2_Vol6
5
M2_Vol5
4
M2_Vol4
3
M2_Vol3
2
M2_Vol2
1
M2_Vol1
0
M2_Vol0
7.13.1 Master 2 Volume Control (Bits 7:0)
Default = 11010010
Function:
The Master 2 volume control register allows the user to simultaneously gain or attenuate all unmasked channels from +22 dB to -96 dB in 0.5 dB increments. The volume changes are implemented
as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device
Configuration 2 - Address 0Ch” on page 34).
The value of the Master 2 volume control register is mapped to the desired 0.5 dB step Master 2 volume setting by the following equation:
Register Value = ( 2 × Desired Volume Setting in dB ) + 210
DS693F1
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CS3318
In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB
resolution volume setting down to ½ dB resolution.
It should be noted that input values outside the CS3318’s analog range of +22 dB to -96 dB are valid;
however, the volume of each channel will be limited to the CS3318’s analog range (see “Volume Limits” on page 20).
See Table 5 on page 31 for example register settings.
7.14
Master 2 Control - Address 15h
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
M2_Mute
0
M2_Qtr
7.14.1 Master 2 Mute (Bit 1)
Default = 0
Function:
This bit controls the Master 2 mute state. When set, the Master 1 mute condition is active. When
cleared, the Master 2 mute condition is released.
See “Muting Controls” on page 21 for more information about the muting behavior of the CS3318.
7.14.2 Master 2 ¼ dB Control (Bit 0)
Default = 0
Function:
When set, ¼ dB of gain will be added to the Master 2 volume level.
See Table 6 on page 32 for an example of volume settings using the ¼ dB control.
7.15
Master 3 Mask - Address 16h
7
M3_Ch8M
6
M3_Ch7M
5
M3_Ch6M
4
M3_Ch5M
3
M3_Ch4M
2
M3_Ch3M
1
M3_Ch2M
0
M3_Ch1M
Each bit in this register serves as a Master 3 mask for its corresponding channel.
If a mask bit is set to ‘1’, the corresponding channel is unmasked, meaning that it will be affected by the
Master 3 volume and muting controls.
If a mask bit is set to ‘0’, the corresponding channel is masked, meaning that it will not be affected by the
Master 3 volume and muting controls.
This register defaults to FFh (all channels unmasked).
7.16
Master 3 Volume - Address 17h
7
M3_Vol7
6
M3_Vol6
5
M3_Vol5
4
M3_Vol4
3
M3_Vol3
2
M3_Vol2
1
M3_Vol1
0
M3_Vol0
7.16.1 Master 3 Volume Control (Bits 7:0)
Default = 11010010
Function:
The Master 3 volume control register allows the user to simultaneously gain or attenuate all unmasked channels from +22 dB to -96 dB in 0.5 dB increments. The volume changes are implemented
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CS3318
as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device
Configuration 2 - Address 0Ch” on page 34).
The value of the Master 3 volume control register is mapped to the desired 0.5 dB step Master 3 volume setting by the following equation:
Register Value = ( 2 × Desired Volume Setting in dB ) + 210
In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB
resolution volume setting down to ½ dB resolution.
It should be noted that input values outside the CS3318’s analog range of +22 dB to -96 dB are valid,
however, the volume of each channel will be limited to the CS3318’s analog range (see “Volume Limits” on page 20).
See Table 5 on page 31 for example register settings.
7.17
Master 3 Control - Address 18h
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
M3_Mute
0
M3_Qtr
7.17.1 Master 3 Mute (Bit 1)
Default = 0
Function:
This bit controls the Master 3 mute state. When set, the Master 3 mute condition is active. When
cleared, the Master 3 mute condition is released.
See “Muting Controls” on page 21 for more information about the muting behavior of the CS3318.
7.17.2 Master 3 ¼ dB Control (Bit 0)
Default = 0
Function:
When set, ¼ dB of gain will be added to the Master 3 volume level.
See Table 6 on page 32 for an example of volume settings using the ¼ dB control.
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CS3318
7.18
Group 2 Chip Address 19h
7
G2_Addr6
6
G2_Addr5
5
G2_Addr4
4
G2_Addr3
3
G2_Addr2
2
G2_Addr1
1
G2_Addr0
0
EnG2Addr
7.18.1 Group 2 Chip Address (Bits 7:1)
SPI Mode Default = 1000000b
I²C Mode Default = See Table 4 on page 27.
Function:
These bits set the Group 2 chip address, and may be modified at any time. See “System Serial Control Configuration” on page 23 and “I²C/SPI Serial Control Formats” on page 27 for more information.
7.18.2 Enable Group 2 Address (Bit 0)
Default = 0
Function:
This bit controls the device’s recognition of the Group 2 address. When set, the device will respond
to serial communication when addressed with the Group 2 address. When cleared, the device will ignore all serial communication when addressed with the Group 2 address.
7.19
Group 1 Chip Address 1Ah
7
G1_Addr6
6
G1_Addr5
5
G1_Addr4
4
G1_Addr3
3
G1_Addr2
2
G1_Addr1
1
G1_Addr0
0
EnG1Addr
7.19.1 Group 1 Chip Address (Bits 7:1)
SPI Mode Default = 1000000b
I²C Mode Default = See Table 4 on page 27.
Function:
These bits set the Group 1 chip address, and may be modified at any time. See “System Serial Control Configuration” on page 23 and “I²C/SPI Serial Control Formats” on page 27 for more information.
7.19.2 Enable Group 1 Address (Bit 0)
Default = 0
Function:
This bit controls the device’s recognition of the Group 1 address. When set, the device will respond
to serial communication when addressed with the Group 1 address. When cleared, the device will ignore all serial communication when addressed with the Group 1 address.
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CS3318
7.20
Individual Chip Address 1Bh
7
Ind_Addr6
6
Ind_Addr5
5
Ind_Addr4
4
Ind_Addr3
3
Ind_Addr2
2
Ind_Addr1
1
Ind_Addr0
0
Enable
7.20.1 Individual Chip Address (Bits 7:1)
SPI Mode Default = 1000000b
I²C Mode Default = See Table 4 on page 27
Function:
These bits set the individual chip address, and may be modified at any time. See “System Serial Control Configuration” on page 23 and “I²C/SPI Serial Control Formats” on page 27 for more information.
7.20.2 Enable Next Device (Bit 0)
Default = 0
Function:
When set, the CS3318’s enable output pin (ENOut) will be driven high. When cleared, the CS3318’s
enable output pin (ENOut) will be driven low.
7.21
Chip ID - Address 1Ch
7
ID3
6
ID2
5
ID1
4
ID0
3
Rev3
2
Rev2
1
Rev1
0
Rev0
This is a Read-Only register.
7.21.1 Chip ID (Bits 7:4)
Default = 0110b
Function:
Chip ID code for the CS3318. Permanently set to 0110.
7.21.2 Chip Revision (Bits 3:0)
Default = xxxxb
Function:
Chip revision code for the CS3318. Encoded as shown in Table 10.
Chip Revision
Register Code
A0, B0
0000b
Table 10. Chip Revision Register Codes
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CS3318
8. PARAMETER DEFINITIONS
Dynamic Range
Full-scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the specified
bandwidth with the input grounded. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the device’s output with a fullscale signal applied to one channel adjacent to the channel under test, and no signal applied to all other
channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
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9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
MAX
MIN
0.055
0.063
--0.004
0.006
0.05
0.009
0.011
0.17
0.354
0.366
8.70
0.28
0.280
6.90
0.354
0.366
8.70
0.28
0.280
6.90
0.020
0.024
0.40
0.24
0.030
0.45
4°
7.000°
0.00°
*Controlling dimension is mm.
MILLIMETERS
NOM
MAX
1.40
1.60
0.10
0.15
0.22
0.27
9.0 BSC
9.30
7.0 BSC
7.10
9.0 BSC
9.30
7.0 BSC
7.10
0.50 BSC
0.60
0.60
0.75
4°
7.00°
*JEDEC Designation: MS022
10.THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters
Package Thermal Resistance (Note 1)
Allowable Junction Temperature
48-LQFP
Symbol
Min
Typ
Max
Units
θJA
θJC
-
48
15
-
125
°C/Watt
°C/Watt
°C
1. θJA is specified according to JEDEC specifications for multi-layer PCBs.
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CS3318
11.ORDERING INFORMATION
Product
CS3318
CDB3318
Description
Package
8-Channel
48-pin
Analog Volume Control
LQFP
CS3318 Evaluation Board
Pb-Free
Grade
Temp Range
YES
Commercial
-10° to +70° C
No
-
-
Container
Order #
Tray
CS3318-CQZ
Tape & Reel CS3318-CQZR
CDB3318
12.REVISION HISTORY
Release
A1
PP1
F1
Changes
Initial Release of Advance Datasheet
Initial Release of Preliminary Datasheet
– Updated THD+N shown on cover page.
– Updated the RL measurement condition for the Analog Characteristics table on page 8.
– Updated THD+N specification in the Analog Characteristics table on page 8
– Updated Supply Current specifications in the Analog Characteristics table on page 8.
– Updated Power Consumption specification in the Analog Characteristics table on page 8.
– Updated Input/Output Voltage Range specification in the Analog Characteristics table on page 8.
– Updated Output Noise specification in the Analog Characteristics table on page 8.
– Updated Chip Revision bit description shown on page 41.
Final Release
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
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DS693F1