CCLD-915 Model 9X14 mm SMD, 3.3V, LVDS Frequency Range: Frequency Stability: Temperature Range: (Option M) (Option X) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Load: 100 Ohms Logic: Output Voltage Levels Jitter: Disable Time Enable Time 12KHz to 20MHz Differential LVDS Clock Oscillator ee Fr ad HS t e L Ro plian m Co 162MHz to 250MHz ±25ppm to ±100ppm 0°C to 70°C -20°C to 70°C -40°C to 85°C -55°C to 120°C 3.3V ± 0.3V 35mA Typ, 47mA Max Differential LVDS 45/55% Max @ 50% Vdd 1ns Max @ 20% to 80% Vdd Connected between OUT and COUT Designed to meet today's requirements for 3.3V LVDS applications. The CCLD-915 is a very low noise, low jitter clock oscillator. Also available in 2.5V model. Available on tape and reel in quantities of 500ea. "0" = 1.10V Typical, 0.90V Min "1" = 1.45V Typical, 1.65V Max 200ns Max 200ns Max 1ps RMS Max <3ppm 1st/yr, 1ppm every year thereafter Aging: SUGGESTED PAD LAYOUT 0.560 (14.2) 0.360 (9.14) Bottom View 0.560 (14.2) CRYSTEK P/N Frequency Date Code 1 0.210 (5.3) 6 2 5 0.050 (1.27) 3 0.070 (1.77) 4 0.100 (2.54) 0.040 (1.01) 0.090 (2.28) 0.280 (7.11) 0.200 (5.08) Bypass Capacitor Recommended RECOMMENDED REFLOW SOLDERING PROFILE Crystek Part Number Guide Reflow ±5°C 235 CCLD-915 X - 25 - 250.000 185 150 Cooling 1-5°C/Sec 100 #1 #2 #3 #4 #5 Stability Indicator: #1 Crystek 9X14 SMD LVDS Osc. #2 Model 915 = 162MHz ~ 250MHz #3 Temp. Range: Blank = 0/70°C, M= -20/70°C, X= -40/85°C #4 Stability: (see Table 1) #5 Frequency in MHz: 3 or 6 decimal places Temperature (4°C/sec Max) 1 to 2 minutes 10 sec Max Time (seconds) 260°C Reflow Profile NOT recommended for this product Pad 1 2 3 4 5 6 Connection E/D N/C GND OUT COUT Vdd Table 2 Blank (std) 50 25 ± 100ppm ± 50ppm ± 25ppm Table 1 Example: CCLD-915X-25-250.000 = 3.3V, 45/55, -40/85°C, 25ppm, 250 MHz Tri-State Function E/D pin Output pin Open "1" level 0.7V Min "0" level 0.3V Max Active Active High Z Table 3 Specifications subject to change without notice. TD-031104 Rev.B