Differential LVDS Voltage Controlled Clock Oscillator ree dF S a Le oH ant R pli m Co CVLD-025 Model 5X7 mm SMD, 2.5V, LVDS Frequency Range: Temperature Range: 50MHz to 200MHz 0°C to 70°C Storage: Input Voltage: Control Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Pulling Range: Linearity: Logic: Terminated 100ohms Temp. 0°C to 70°C -45°C to 90°C 2.5V ± 0.125V 1.25V ± 1.25V 50mA Typ, 80mA Max Differential LVDS 40/60% Max @ 50% Vdd 1ns Max ±50ppm APR Min. (std) ± 10% Max (Offset 1.25V Typ.) "0" = 1.10 Typical "1" = 1.43 Typical Designed to meet today's requirements for 2.5V Differential LVDS applications. The CVLD-025 provides very low phase noise & jitter for demanding applications. Available on 16mm tape and reel in quantities of 1,000pcs.. 0.5psec Typ., 1psec RMS Max Jitter: 12KHz to 20MHz <5ppm 1st/yr, <2ppm every year thereafter Aging: SUGGESTED PAD LAYOUT Dimensions inches (mm) All dimensions are Max unless otherwise specified. .283 (7.20) P/N Freq DC .055 ±.003 (1.40 ±.08) .203 (5.15) .079 (2.0) .071 SQ (1.80) #1 #2 #3 #6 #5 #4 .148 (3.75) .040 ±.003 (1.0 ±.08) .200 ±.005 (5.08 ±.13) Bottom View Denotes pad 1 .200 (5.08) Bypass Capacitor Recommended TEMPERATURE RECOMMENDED REFLOW SOLDERING PROFILE Ramp-Up 3°C/Sec Max. 260°C Ramp-Down 6°C/Sec. 217°C Crystek Part Number Guide Critical Temperature Zone CVLD-025 - 50 - 155.520 #1 200°C #2 #3 #4 #5 Pulling (APR) Min. 150°C Preheat 180 Secs. Max. 8 Minutes Max. 90 Secs. Max. #1 Crystek 5x7 SMD PECL VCXO #2 Model 025 = 2.5V #3 Temp. Range: Blank = 0/70°C #4 Pulling: (see Table 1) #5 Frequency in MHz: 3 or 6 decimal places Blank 50 (std) ± 100ppm ± 50ppm Table 1 260°C for 10 Secs. Max. Example: CVLD-025-50-155.520 = 2.5V, 40.60, 0/70°C, 50ppm APR, 155.520 MHz NOTE: Reflow Profile with 240°C peak also acceptable. Pad Connection 1 2 3 4 5 6 Volt Cont. E/D GND OUT COUT Vdd Enable/Disable Function E/D pin Output pin Open "1" level 2.2V Min "0" level 0.4V Max Active Active High Z Specifications subject to change without notice. TD-070301 Rev.A