DR80390CPU
High Performance
8-bit Microcontroller
ver 3.10
OVERVIEW
CPU FEATURES
DR80390CPU is a high performance,
area optimized soft core of a single-chip 8-bit
embedded controller dedicated for operation
with fast (typically on-chip) and slow (off-chip)
memories. The core has been designed with a
special concern about low power consumption. Additionally an advanced power management unit makes DR80390CPU core perfect for portable equipment where low power
consumption is mandatory.
DR80390CPU soft core is 100% binarycompatible with the industry standard 80C390
& 8051 8-bit microcontroller. There are two
configurations of DR80390CPU: Harward
where external data and program buses are
separated, and von Neumann with common
program and external data bus. DR80390CPU
has RISC architecture 6.7 times faster compared to standard architecture and executes
65-200 million instructions per second. This
performance can also be exploited to great
advantage in low power applications where
the core can be clocked up to seven times
more slowly than the original implementation
for no performance penalty.
DR80390CPU is delivered with fully
automated testbench and complete set of
tests allowing easy package validation at each
stage of SoC design flow.
● 100% software compatible with industry
standard 80390 & 8051
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○ LARGE mode – 8051 instruction set
○ FLAT mode – 80390 instruction set
● RISC architecture enables to execute instructions 6.7 times faster compared to
standard 8051
● 12 times faster multiplication
● 9.6 times faster division
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 16M bytes of contiguous Program
Memory
● Up to 16M bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
● De-multiplexed Address/Data bus to allow
easy connection to memory
● Interface for additional Special Function
Registers
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● Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states
● Scan test ready
● 1.3 GHz virtual clock frequency in a 0.35u
technological process
CONFIGURATION
The following parameters of the DR80390CPU
core can be easy adjusted to requirements of
dedicated application and technology. Configuration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
PERIPHERALS
● DoCD™ debug unit
○ Processor execution control
• Memory style
- Harward
- von Neumann
• Program Memory type
- synchronous
- asynchronous
○ Run
○ Halt
•
○ Step into instruction
○ Skip instruction
Program Memory waitstates
• Program Memory writes
- used
- unused
• Internal Data Memory type
- synchronous
- asynchronous
○ Read-write all processor contents
○ Program Counter (PC)
○ Program Memory
•
○ Internal (direct) Data Memory
○ Special Function Registers (SFRs)
○ External Data Memory
○ Hardware execution breakpoints
External Data Memory
wait-states
subroutines
location
-
• Power Management Mode
- used
- unused
• Stop mode
- used
- unused
• DoCD debug unit
- used
- unused
○ Special Function Registers (SFRs)
○ External Data Memory
- used (0-7)
- unused
• Interrupts
○ Program Memory
○ Internal (direct) Data Memory
- used (0-7)
- unused
○ Hardware breakpoints activated at a certain
○ Program address (PC)
○ Address by any write into memory
DELIVERABLES
♦
○ Address by any read from memory
○ Address by write into memory a required data
○ Address by read from memory a required data
♦
○ Three wire communication interface
● Power Management Unit
○ Power management mode
♦
○ Switchback feature
○ Stop mode
● Interrupt Controller
○ 2 priority levels
○ 2 external interrupt sources
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
◊
◊
◊
♦
♦
♦
●
●
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are trademarks of their respective owners.
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
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●
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL Source
SYMBOL
clk
reset
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
prgwr
sfrdatai(7:0)
prgdatai(7:0)
xramdatai(7:0)
int0
int1
xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
xramwr
docddatai
docddatao
docdclk
stop
pmm
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
BLOCK DIAGRAM
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
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are trademarks of their respective owners.
clk
reset
prgdatai(7:0)
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
prgwr
Opcode
Decoder
ALU
Program
Memory
Interface
Control Unit
xramdatai(7:0)
xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
xramwr
External
Memory
Interface
Interrupt
Controller
int0
int1
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
Internal Data
Memory
Interface
Power
Management
Unit
stop
pmm
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
User SFR
Interface
DoCD™
Debug Unit
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docddatai
docddatao
docdclk
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
input
Global clock
reset
input
Global synchronous reset
ramdatai[7:0]
input
Data bus from Internal Data Memory
sfrdatai[7:0]
input
Data bus from user SFRs
prgdatai[7:0]
input
Input data bus from Program Memory
xramdatai[7:0]
input
Data bus from External Data Memory
int0
input
External interrupt 0 line
int1
input
External interrupt 1 line
docddatai
input
DoCD™ data input
ramdatao[7:0]
output
Data bus for Internal Data Memory
ramaddr[7:0]
output
Internal Data Memory address bus
ramoe
output
Internal Data Memory output enable
ramwe
output
Internal Data Memory write enable
sfrdatao[7:0]
output
Data bus for user SFRs
sfraddr[7:0]
output
User SFRs address bus
sfroe
output
User SFRs output enable
sfrwe
output
User SFRs write enable
prgaddr[23:0]
output
Program Memory address bus
prgdatao[7:0]
output
Output data bus for Program Memory
prgdataz
output
PRGDATA tri-state buffers control line
prgrd
output
Program Memory read
prgwr
output
Program Memory write
xramdatao[7:0]
output
Data bus for External Data Memory
xramdataz
output
XDATA tri-state buffers control line
xramaddr[23:0]
output
External Data Memory address bus
xramrd
output
External Data Memory read
xramwr
output
External Data Memory write
docddatao
output
DoCD™ data output
docdclk
output
DoCD™ clock line
pmm
output
Power management mode indicator
stop
output
Stop mode indicator
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execution of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
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are trademarks of their respective owners.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program
Memory can be also written. This feature allows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module. Program fetch cycle length
can be programmed by user. This feature is
called Program Memory Wait States, and allows core to work with different speed program
memories.
External Memory Interface – Contains memory access related registers such as Data
Pointer High (DPH0), Data Pointer Low
(DPL0), Data Page Pointer (DPP0), MOVX
@Ri address register (MXAX) and STRETCH
registers. It performs the memory addressing
and data transfers. Allows applications software to access up to 16 MB of external data
memory. The DPP0 register is used for segments swapping. STRETCH register allows
flexible timing management while accessing
different speed system devices by programming XRAMWR and XRAMRD pulse width
between 1 – 8 clock periods.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Registers interface controls access to the special
registers. It contains standard and used defined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct addressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Management Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
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microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit – it’s a real-time hardware debugger provides debugging capability
of a whole SoC system. In contrast to other onchip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. The DoCD™ system
includes three-wire interface and complete set
of tools to communicate and work with core in
real time debugging. It is built as scalable unit
and some features can be turned off to save
silicon and reduce power consumption. A special care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when debug option is no longer used.
PERFORMANCE
The following tables give a survey about the
Core area and performance in the ASICs Devices (all CPU features and peripherals have
been included):
Device
0.25u typical
0.25u typical
Optimization
area
speed
Fmax
100 MHz
250 MHz
Core performance in ASIC devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and their improvements
are shown in table below. An improvement was
computed as {80C51 clock periods} divided by
{DR80390CPU clock periods} required to execute an identical function. More details are
available in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
7,20
6,00
6,00
7,20
7,20
6,00
6,00
7,20
10,67
9,60
7,20
7,64
9,75
7,20
7,43
9,04
7,58
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following table gives a survey about the DR80390CPU
performance in terms of Dhrystone/sec and
VAX MIPS rating.
Device
Target
80C51
80C310
DR80390CPU
0.25u
Clock
Dhry/sec
frequency
(VAX MIPS)
12 MHz
268 (0.153)
33 MHz
1550 (0.882)
250 MHz 40125 (22.837)
Core performance in terms of Dhrystones
40125
45000
40000
35000
30000
25000
20000
15000
10000
268
5000
1550
0
80C51 (12MHz)
80C310 (33MHz)
DR80390CPU (90MHz)
Area utilized by the each unit of DR80390CPU
core in vendor specific technologies is summarized in table below.
Component
CPU*
Interrupt Controller
Power Management Unit
Total area
Area
[Gates]
[FFs]
5350
400
50
5800
240
40
5
285
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
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are trademarks of their respective owners.
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4
4
-
-
-
-
-
-
Fixed Point
Coprocessor
Floating Point
Coprocessor
1
2
SPI
I\O Ports
2
3
Master I2C Bus
Controller
Slave I2C Bus
Controller
UART
1
1
2
Watchdog
Timer/Counters
2
2
2
Compare/Capture
Data Pointers
2
5
15
Program Memory Wait
States
Interrupt levels
DR80390CPU 6.7 16M 256 256 16M
DR80390
6.7 16M 256 256 16M
DR80390XP
6.7 16M 256 256 16M
Interrupt sources
Internal Data Memory
space
External Data Memory
space
External Data Memory
Wait States
Power Management
Unit
Interface for
additional SFRs
Stack space size
Program Memory space
Design
Architecture speed
grade
The main features of each DR80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
DR80390 family of High Performance Microcontroller Cores
-
-
-
-
-
-
DR8051 family of High Performance Microcontroller Cores
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Fixed Point
Coprocessor
Floating Point
Coprocessor
4
4
SPI
1
2
Master I C Bus
Controller
Slave I2C Bus
Controller
I\O Ports
2
3
2
UART
1
1
2
Watchdog
Timer/Counters
2
2
2
Compare/Capture
Data Pointers
2
5
15
Program Memory Wait
States
Interrupt levels
Internal Data Memory
space
External Data Memory
space
External Data Memory
Wait States
Power Management
Unit
Interface for
additional SFRs
Stack space size
6.7 64k 256 256 16M
6.7 64k 256 256 16M
6.7 64k 256 256 16M
Interrupt sources
DR8051CPU
DR8051
DR8051XP
Program Memory space
Design
Architecture speed
grade
The main features of each DR8051 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
CONTACTS
For any modification or special request
please contact to Digital Core Design or local
distributors.
Headquarters:
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@ddccdd..ppll
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San Antonio, TX 78245, USA
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fax
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Distributors:
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