ELANTEC EL7556ACM

EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
Features
General Description
• EL7556C Pin Compatible
• Improved Temperature and
Voltage Ranges
• 6A Continuous Load Current
• Precision Internal 1% Reference
• 1.0V to 3.8V Output Voltage
• Internal Power MOSFETs
• >90% Efficiency
• Synchronous Switching
• Adjustable Slope Compensation
• Over Temperature Indicator
• Pulse by Pulse Current Limiting
• Operates up to 1MHz
• 1.5% Typical Output Accuracy
• Adjustable Oscillator w/Sync
• Remote Enable/Disable
• Intel P54 and P55 Compatible
• VCC2DET Interface
• Internal Soft Start
The EL7556AC is an adjustable synchronous DC:DC switching regulator optimized for a 5V input and 1.0-3.8V output. By combining
integrated NMOS power FETS with a fused-lead package the
EL7556AC can supply up to 6A continuous output current without the
use of external power devices or discrete heat sinks, thereby minimizing design effort and overall system cost.
Connection Diagram
Applications
•
•
•
•
•
•
On chip resistorless current sensing is used to achieve stable, highly
efficient, current-mode control. The EL7556AC also incorporates the
VCC2DET function to directly interface with the Intel P54 and P55
microprocessors. Depending on the state of VCC2DET the output
voltage is internally preset to 3.50V or a user adjustable voltage using
two external resistors. In both internal and external feedback modes
the active-high PWRGD output indicates when the regulator output is
within ±10% of the programmed voltage. An on-board sensor monitors die temperature (OT) for over-temperature conditions and can be
connected directly to OUTEN to provide automatic thermal shutdown.
Adjustable oscillator frequency and slope compensation allow added
flexibility in overall system design.
PC Motherboards
Local high power CPU supplies
5V to 1.0V DC-DC Conversion
Portable Electronics/Instruments
P54 and P55 Regulators
GTL+ Bus Power Supply
R4
R3
100Ω
150Ω
VIN
D3
1
C4
FB1
FB2 28
0.1µF
C7
2
CREF
3
CSLOPE
C2V 26
CP 27
4
COSC
VSS 25
R1
150pF
C8
220pF
D2
1µF
C11
68Ω
R6
R5
Ordering Information
D4
C5
5
VDD
VHI 24
6
VIN
LX 23
7
VSSP
LX 22
5Ω
C6
D1
0.22µF
68Ω
0.1µF
Part No
Temp. Range
EL7556ACM -40°C to +85°C
Package
Outline #
28-Lead SOIC
MDP0027
VIN
L1
2.5µH
C9
C12
8
VIN
LX 21
660µF
0.1µF
9
VSSP
LX 20
C10
10 VSSP
VSSP 19
1mF
11 VSSP
VSSP 18
12 VSSP
TEST 17
C3
VOUT
1µF
Connect to VSSP for
external feedback
13
VCC2DET
16
PWRGD
C3, C4, C5, C6, C7 C8 - ceramic
C5, C11 - ceramic or tantalum
C9 - Sprague 594D337X10010R2T 2X330µF
C10 - Sprague 594D337X10010R2T 3X330µF
L1 - Pulse Engineering, PE-53681
D1-D4: BAT54S fast diode
OT 15
EL7556AC
Manufactured under U.S. Patents No. 5,723,974 and No. 5,793,126
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2000 Elantec, Inc.
February 28, 2000
14 OUTEN
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
Absolute Maximum Ratings (T
= 25 °C)
Storage Temperature Range
Supply (V )
IN
Ambient Operating Temperature
-65°C to +150°C
6.0V
-40°C to +85°C
A
Output Pins
Operating Junction Temperature
Peak Output Current
-0.3V below GND, +0.3V above VDD
135°C
9A
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified
temperature and are pulsed tests, therefore: TJ = TC = TA.
Electrical Characteristics
VDD = VIN = 5V, COSC = 1nF, CSLOPE=470pF, TA=25°C unless otherwise specified.
Parameter
Description
Conditions
Min
Typ
Max
25
Units
General
IDD
VDD Supply Current
OUTEN=4V, FOSC=120kHz
11
IDDOFF
VDD Standby Current
OUTEN=0
0.1
IVIN
VIN No Load Current
OUTEN=0
3
5
VOUT1
Output Initial Accuracy
VCC2DET=4V, IL=3A(See Fig. 1)
3.450
3.500
3.550
V
VOUT2
Output Initial Accuracy
VCC2DET=0V, IL=3A R3=150Ω, R4=100Ω
(See Fig. 1)
2.450
2.500
2.550
V
VOUTLINE
Output line Regulation
VDD=5V, ±10%
-1
1
%
VOUTLOAD
Output Load Regulation
0A<ILOAD<6A, Relative to IL=3A. Continuous Mode of Operation (Fig.1)
-1
1
%
RSHORT
Short Circuit Load Resistance
IL=6A Prior to Continuous Application of
RSHORT. OUTEN Connected to OT.
100
9
A
-40°C<Ta<85°C
±1
%
mA
mA
mA
mΩ
II MAX
Current Limit
VOUTTC
Output Tempco
TOT
Over Temperature Threshold
135
°C
THYS
Over Temperature Hysteresis
40
°C
VPWRGD
Power Good Threshold Relative to Programmed
Output Voltage
VCC2SEL=4V, VOUT=3.50V
±6
±10
±14
%
4.15
V
VDDOFF
Minimum VDD for Shutdown
VDDON
Maximum VDD for Startup
VHYS
Input Hysteresis
0.5
V
M
Soft start slope
7
V/msec
DMAX
Maximum duty cycle
96
%
SS
3.15
VHYS=VDDON-VDDOFF
V
Controller - Inputs
IPUP
VCC2DET, OUTEN Pull Up Current
ICSLOPE
Cslope Charging Current
IFB1
FB1 Input Pull Up Current
ROT
Over Temperature Pull Up Resistance
VIH
VCC2DET, OUTEN Input High
VIL
VCC2DET, OUTEN Input Low
VOH PWGD
Powergood Drive High
ILoad=1mA
VOL PWGD
Powergood Drive Low
ILoad=-1mA
VCC2DET, OUTEN=0
10
14
18
23
28.5
34
2
OT=0V
30
40
µA
µA
µA
50
4
kΩ
V
.8
V
1.0
V
3.5
V
Controller - Reference
VREF
Reference Accuracy
VREFTC
Reference Voltage Tempco
VREFLOAD
Reference Load Regulation
IREF=0
1.247
1.260
1.273
50
0<ILOAD<100µA
2
0.5
V
ppm/ºC
0.5
%/ºC
Electrical Characteristics
VDD = VIN = 5V, COSC = 1nF, CSLOPE=470pF, TA=25°C unless otherwise specified.
Parameter
Description
Conditions
Min
Typ
Max
Units
7.1
7.7
8.3
V
Controller - Doubler
VC2V
Voltage Doubler Output
Vdd=5V, ILOAD=10mA
Controller - Oscillator
FRAMP
Oscillator Ramp Amplitude
IOSC CHG
Oscillator Charge Current
.2V<VOSC<1.4V
IOSC DIS
Oscillator Discharge Current
.2V<VOSC<1.4V
F
Oscillator initial accuracy
Minimum oscillator sync width
OSC
tsync
1.2
V
150
µA
5
100
120
mA
140
50
kHz
ns
Power - FET
ILEAK
LX Output Leakage to VSS
RDSON
Composite FET Resistance
RDSONTC
RDSON Tempco
0.1
t
FET break before make delay
High side FET minimum on time (LEB)
10
ns
140
ns
brm
tLEB
LX=0V
18
3
100
µA
30
mΩ
mΩ/ºC
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
Programmable CPU Power Supply Unit
Typical Performance Curves
Efficiency vs. ILOAD (VOUT =3.5V)
VDD=VIN=5.0V (±10%)
Efficiency vs. ILOAD (VDD=5.0V)
96%
94%
100%
TA=25°C
VDD=4.5V
95%
VOUT=3.5V
90%
90%
Efficiency
Efficiency
92%
88%
86%
84%
VDD=5.0V
VOUT=2.5V
85%
80%
VDD=5.5V
80%
0.5
1.5
2.5
3.5 4.5
IOUT (A)
5.5
70%
0.5
6.5
Line Regulation (CSLOPE=100pF)
1.5
2.5
3.5 4.5
IOUT(A)
5.5
6.0
Load Regulation (CSLOPE=100pF)
3.54
3.54
TA=25°C
3.53
TA=25°C
3.53
3.52
3.52
IOUT=0.5A
3.51
3.50
VOUT (V)
VOUT (V)
VOUT=1.0V
75%
82%
IOUT=3A
3.49
3.48
VIN=5.5V
3.51
VIN=5.0V
3.50
VIN=4.5V
3.49
3.48
IOUT=6A
3.47
3.46
4.5V
3.47
5.0V
VIN (V)
3.46
0.5
5.5V
3.0
IOUT (A)
6.0
Load Regulation vs. CSLOPE (VIN=5.0V)
IOUT=3A, +3A, -2.5A
Line Regulation vs. CSLOPE (IOUT=3A)
VDD=VIN=5.0V ±10%
0.6%
0.8%
TA=25°C
0.7%
TA=25°C
0.5%
0.6%
VOUT=3.5V
0.4%
0.5%
∆VOUT (±)
∆VOUT (±)
EL7556AC
EL7556AC
VOUT=3.5V
0.4%
VOUT=2.5V
0.3%
0.3%
VOUT=2.5V
0.2%
VOUT=1.0V
0.2%
0.1%
0.1%
0.0%
50
VOUT=1.0V
75
100
125
CSLOPE (pF)
150
0.0%
50
175
4
75
100
125
CSLOPE (pF)
150
175
Line Regulation vs. CSLOPE
VIN=VDD=5.0V ±10%
Load Regulation vs. CSLOPE
IOUT=3A, +3A, -2.5A
0.8%
0.8%
TA=25°C
0.7%
0.4%
0.3%
IOUT=.5A
0.2%
0.5%
0.3%
100
125
CSLOPE (pF)
75
150
0.0%
50
175
Deviation in VOUT
VOUT=1.0V
-0.5%
VOUT=2.5V
-1.5%
-2.0%
VOUT=3.5V
75
CSLOPE=100pF
COSC=220pF
0.5%
0.0%
-0.5%
Loop Gain Induced Error
-1.0%
-2.5%
-3.0%
50
175
TA=25°C
1.0%
0.5%
-1.0%
150
1.5%
TA=25°C
0.0%
100
125
CSLOPE (pF)
75
VOUT Variation vs. Programmed Output
Voltage (VIDEAL=(1+R3/R4))
VOUT vs. CSLOPE
(VIN=5.0V, ILOAD=.5A)
∆VOUT (±)
VIN=5.5V
0.1%
0.0%
50
1.0%
VIN=5.0V
0.4%
0.2%
0.1%
1.5%
VIN=4.5V
0.6%
IOUT=6A
0.5%
∆VOUT (±)
∆VOUT (±)
0.6%
TA=25°C
0.7%
100
125
CSLOPE (pF)
150
-1.5%
1.0
175
FOSC vs. COSC
1.5
2.0 2.5 3.0
VIDEAL (V)
3.5
4.0
FOSC vs. Temp
10000
520
510
TA=25°C
VDD=4.5V
500
FOSCkHz
FOSCkHz
1000
100
490
VDD=5.0V
480
VDD=5.5V
470
10
460
1
10
100
1000
CSLOPE (pF)
450
10000
5
0
20
40
60 80 100 120 140
Temp (°C)
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
Programmable CPU Power Supply Unit
I(VIN) vs. FOSC
I(VDD) + I(VIN) vs. FOSC
16
60
TA=25°C
OUTEN=VDD
50
IVIN (mA)
Iq (mA)
VDD=4.5V
20
10
10
8
VDD=5.0V
6
VDD=4.5V
4
2 Discontinuous Mode
Discontinuous Mode
Continuous Mode
0
200
400
600
FOSC (kHz)
800
0
200
1000
Continuous Mode
400
600
800
1000
FOSC (kHz)
IDD + IVIN vs. FOSC
I(VDD) vs. FOSC
2.0
50
45
40
35
30
25
20
15
10
5
0
TA=25°C
OUTEN=VDD
VDD=5.5V
VDD=5.5V
VDD=5.0V
IDD (mA) + IVIN
IDD (mA)
VDD=5.5V
12
VDD=5.0V
30
TA=25°C
OUTEN=VDD
14
VDD=5.5V
40
VDD=4.5V
200
400
600
FOSC (kHz)
800
VDD=4.5V
100
FOSC (kHz)
1000
Minimum Output Voltage vs. FOSC
Power On Reset
2.3
TA=25°C
OUTEN=VDD
2.1
Tj=120°C
VDD=5.5V
1.9
FOSC=500k
VOUT (V)
30
VDD=5.0V
1.5
1.0
10
1000
40
Iq(mA)
EL7556AC
EL7556AC
20
1.7
VDD=5.0V
1.5
1.3
VDD=4.5V
1.1
10
0.9
0
2.5
0.7
3.0
3.5
4.0
VDD(V)
4.5
200
5.0
6
400
600
FOSC (kHz)
800
1000
Maximum ILOAD vs. Temp
Theta JM vs. Cu Area
7556 Demo Board (31°C/W)
8.0
41
Board with no
Components
37
7.0
35
6.5
33
31
29
6.0
5.5
5.0
Board with Inductor
27
Still Air
4.5
25
0.00 1.00 2.00 3.00 4.00 5.00 6.00
Bare Cu Area (in2)
30
RDSON vs. Temp
36
34
32
30
28
26
24
22
20
0
25
50
75
Temp (°C)
100
OUTEN connected to OT
4.0
38
RDSON (m Ω)
100 LFM
7.5
ILOAD (A)
Theta JM (°C/W)
39
125
7
40
50
TA (°C)
60
70
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
Pin Description
(I=Input O=Output S=Supply)
Pin Number
Pin Name
Pin Type
Function
1
FB1
I
Voltage feedback pin for the buck regulator. Active when VCC2DET is logic low. Normally connected to external resistor divider between VOUT and GND. A 2µA pull-up current forces VOUT to VSS in the event that
FB1is floating and VCC2DET is inadvertently connected to GND.
2
CREF
I
Bandgap reference bypass capacitor. Typically 0.1µF to VSS.
3
CSLOPE
I
Slope compensation capacitor. Ramp width corresponds to LX duty cycle. CSLOPE to COSC ratio is normally
1:1.5.
4
COSC
I
Oscillator timing capacitor. FOSC(Hz) can be approximated by: FOSC(Hz)= 0.0001/COSC. COSC in Farads.
5
VDD
S
Power Supply for PWM control circuitry. Normally the same potential as VIN.
6
VIN
S
Power supply for the buck regulator. Connected to the drain of the high-side NMOS FET.
7
VSSP
S
Ground return for the buck regulator. Connected to the source of the low-side synchronous NMOS FET.
8
VIN
S
Same as pin 6.
9
VSSP
S
Same as pin 7.
10
VSSP
S
Same as pin 7.
11
VSSP
S
Same as pin 7.
12
VSSP
S
Same as pin 7.
13
VCC2DET
I
VCC2DET interface logic input. When driven to logic 1 VOUT=3.500V. When driven to logic 0 the PWM uses
FB1 to determine VOUT: VOUT=1.0V*(1+R3/R4).
14
OUTEN
I
The switching regulator output is enabled when logic 1. The reference voltage output operates whenever the
power supply is quAlified (VDD>VPOR) regardless of the state of this pin.
15
OT
O
Over temperature indicator. Normally high. Pulls low when die temperature exceeds 135°C, returns to the high
state when die temperature has cooled to 100°C.
16
PWRGD
O
Power good window comparator output. Logic 1 when regulator output is within ±10% of programmed voltage.
17
TEST
I
Test pin. Must be connected to VSSP in normal operation.
18
VSSP
S
Same as pin 7.
19
VSSP
S
Same as pin 7.
20
LX
O
Inductor drive pin. High current switching output whose average voltage equAls the regulator output voltage.
21
LX
O
Same as pin 20.
22
LX
O
Same as pin 20
23
LX
O
Same as pin 20
24
VHI
I
Gate drive to high-side driver. Bootstrapped from LX with a 0.1µF capacitor.
25
VSS
S
Ground return for the control circuitry.
26
C2V
I
Connected to voltage doubler output. Supplies gate drive to the low-side driver.
27
CP
O
Drives the negative side of charge pump capacitor at one-half the oscillator frequency FOSC.
28
FB2
I
Voltage feedback pin. Active when VCC2DET is logic 1. Internally preset to VOUT=3.5V.
8
Block Diagram
FB1, Pin1
FB2, Pin 28
PWRGD, Pin 16
CP, Pin 27
+
2-1 MUX
C2V, Pin 26
V2X
+
VHI, Pin 24
+
VCCDET, Pin 13
CSLOPE, Pin 3
VDD and VIN,
Pin 5,6,8
Current Sense
CREF, Pin 27
LEB TDELAY
1.26V
Σ
+
Current Limit
Q
OUTEN, Pin 14
+ PWM
9
+
LX, Pin 20-23
Q
S
VDD
RSS
CSS
+
S
+
R
R
FF
S
+
VDD
Zero Cross Detect
COSC, Pin 4
OT, Pin 15
Over Temp Sensor
VSS, Pin 25
EL7556AC
Programmable CPU Power Supply Unit
VSSP, Pin 9-12,
18-19
UVLO
EL7556AC
4V
R
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
Applications Information
the relatively large LC time constants found in power
supply applications generally results in low bandwidth
and poor transient response. By directly monitoring
changes in inductor current via a series sense resistor the
controller’s response time is not entirely limited by the
output LC filter and can react more quickly to changes in
line or load conditions. This feed-forward characteristic
also simplifies AC loop compensation since it adds a
zero to the overall loop response. Through proper selection of the current-feedback to voltage-feedback ratio,
the overall loop response will approach a one pole system. The resulting system offers several advantages over
traditional voltage control systems, including simpler
loop compensation, pulse by pulse current limiting,
rapid response to line variation and good load step
response.
Circuit Description
General
The EL7556AC is a fixed frequency, current mode controlled DC:DC converter with integrated N-channel
power MOSFETS and a high precision reference. The
device incorporates all of the active circuitry required to
implement a cost effective, user-programmable 6A synchronous buck converter suitable for use in CPU power
supplies. By combining fused-lead packaging technolo g y w i t h a n e f f i c i e n t s y n c h r o n o u s s w i t c h i ng
architecture, high power outputs (21W) can be realized
without the use of discrete external heat sinks.
Theory of Operation
The EL7556AC is composed of 7 major blocks:
The heart of the controller is a triple-input direct summing comparator which sums voltage feedback, current
feedback and slope compensating ramp signals together.
Slope compensation is required to prevent system instability which occurs in current-mode topologies
operating at duty-cycles greater than 50% and is also
used to define the open-loop gain of the overall system.
The compensation ramp amplitude is user adjustable and
is set using a single external capacitor (CSLOPE). Each
comparator input is weighted and determines the load
and line regulation characteristics of the system. Current
feedback is measured by sensing the inductor current
flowing through the high-side switch whenever it is conducting. At the beginning of each oscillator period the
high-side NMOS switch is turned on and CSLOPE
ramps positively from its reset state (VREF potential).
The comparator inputs are gated off for a minimum
period of time (LEB) after the high-side switch is turned
on to allow the system to settle. The Leading Edge
Blanking (LEB) period prevents the detection of erroneous voltages at the comparator inputs due to switching
noise. When programming low regulator output voltages
the LEB delay will limit the maximum operating frequency of the circuit since the LEB will result in a
minimum duty-cycle regardless of the PWM error voltage. This relationship is shown in the performance
curves. If the inductor current exceeds the maximum
current limit (ILMAX), a secondary over-current com-
1. PWM Controller
2. Output Voltage Mode Select
3. NMOS Power FETS and Drive Circuitry
4. Bandgap Reference
5. Oscillator
6. Temperature Sensor
7. Power Good and Power On Reset
PWM Controller
The EL7556AC regulates output voltage through the use
of current-mode controlled pulse width modulation. The
three main elements in a PWM controller are the feedback loop and reference, a pulse width modulator whose
duty cycle is controlled by the feedback error signal, and
a filter which averages the logic level modulator output.
In a step-down (buck) converter, the feedback loop
forces the time-averaged output of the modulator to
equal the desired output voltage. Unlike pure voltagemode control systems current-mode control utilizes dual
feedback loops to provide both output voltage and
inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output
voltage by adjusting the PWM duty-cycle in response to
changes in line or load conditions. Since the output voltage is equal to the time-average of the modulator output
10
and external components D1-D3 and C5-C6. The CP
output is a low resistance inverter driven at one-half the
oscillator frequency. This is used in conjunction with
D2-D3 to generate a 7.5V (typical) voltage on the C2V
pin which provides gate drive to the low-side NMOS
switch and associated level shifter. In order to use an
NMOS switch for the high-side drive it is necessary to
drive the gate voltage above the source voltage (LX).
This is accomplished by boot-strapping the VHI pin
above the C2V voltage with capacitor C6 and diode D1.
When the low-side switch is turned on the LX voltage is
close to GND potential and capacitor C6 is charged
through diodes D1-D3 to approximately 6.9V. At the
beginning of the next cycle the high side switch turns on
and the LX pin begins to rise from GND to VDD potential. As the LX pin rises the positive plate of capacitor
C6 follows and eventually reaches a value of approximately 11.2V, for VDD=5V. This voltage is then level
shifted and used to drive the gate of the high-side FET,
via the VHI pin.
parator will terminate the high-side switch. If ILMAX
has not been reached, the regulator output voltage is then
compared to the reference voltage VREF. The resultant
error voltage is summed with the current feedback and
slope compensation ramp. The high-side switch remains
on until all three comparator inputs have summed to
zero, at which time the high-side switch is turned off and
the low-side switch is turned on. In order to eliminate
cross-conduction of the high-side and low-side switches
a 10ns break-before-make delay is incorporated in the
switch driver circuitry. In the continuous mode of operation the low-side switch will remain on until the end of
the oscillator period. In order to improve the low current
efficiency of the EL7556AC, a zero-crossing comparator senses when the inductor transitions through zero.
Turning off the low-side switch at zero inductor current
prevents forward conduction through the internal clamping diodes (LX to VSSP) when the low-side switch turns
off, reducing power dissipation. The output enable
(OUTEN) input allows the regulator output to be disabled by an external logic control signal.
Reference
Output Voltage Mode Select
A 1% temperature compensated band gap reference is
integrated in the EL7556AC. The external CREF capacitor acts as the dominant pole of the amplifier and can be
increased in size to maximize transient noise rejection.
A value of 0.1uF is recommended.
The VCC2DET multiplexes the FB1 and FB2 pins to the
PWM controller. A logic 1 on VCC2DET selects the
FB2 input and forces the output voltage to the internally
programmed value of 3.50V. A logic zero on VCC2DET
selects FB1 and allows the output to be programmed
from 1.0 to 3.8V. In general:
Oscillator
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and
loop-gain are changed. This is shown in the performance
curves. (The output voltage is factory trimmed to minimize error at a 2.50V output). A 2uA pull-up current
from FB1 to VIN forces VOUT to GND in the event that
FB1 is not used and the VCC2DET is inadvertently toggled between the internal and external feedback mode of
operation.
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately
96%. Operating frequency can be adjusted through the
COSC pin or can be driven by an external clock source.
If the oscillator is driven by an external source, care
must be taken in the selection of CSLOPE. Since the
COSC and CSLOPE values determine the open loop
gain of the system, changes to COSC require corresponding changes to CSLOPE in order to maintain a
constant gain ratio. The recommended ratio of COSC to
CSLOPE is 1.5:1
NMOS Power FETS and Drive Circuitry
Temperature Sensor
The EL7556AC integrates low resistance (25mΩ)
NMOS FETS to achieve high efficiency at 6A. Gate
drive for both the high-side and low-side switches is
derived through a charge pump consisting of the CP pin
An internal temperature sensor continuously monitors
die temperature. In the event that die temperature
exceeds the thermal trip-point, the OT pin will output a
logic 0. The upper and lower trip points are set to 135 ºC
Vout=1.0V (1+R3/R4) Volt.
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EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
and 100 ºC respectively. To enable thermal shutdown
this pin should be tied directly to OUTEN. Use of this
feature is recommended during normal operation
with the application of air flow. For example, the addition of 100LFM reduces the thermal resistance by
approximately 15% and can extend the operating ambient to 77ºC (typical). Since the thermal performance of
the IC is heavily dependent on the board layout, the system designer should exercise care during the design
phase to ensure that the IC will operate under the worstcase environmental conditions.
Power Good and Power On Reset
During power up the output regulator will be disabled
until VIN reaches a value of approximately 4.0V.
Approximately 500mV of hysteresis is present to eliminate noise induced oscillations.
Under-voltage and over-voltage conditions on the regulator output are detected through an internal window
comparator. A logic 1 on the PWRGD output indicates
that regulated output voltage is within ±10% of the nominally programmed output voltage. Although small, the
typical values of the PWRGD threshold will vary with
changes to external feedback (and resultant loop gain) of
the system. This dependence is shown in the typical performance curves.
Thermal Management
The EL7556AC utilizes fused-lead packaging technology in conjunction with the system board layout to
achieve a lower thermal resistance than typically found
in standard 28 lead SOIC packages. By fusing multiple
leads to the die substrate thermal energy flows through a
thermally conductive path (metal) instead of thermally
resistive plastic. After conducting heat from the die to
the leads, heat transfer occurs by convection. If a sufficient amount of metal area is connected to the package
leads a junction-to-ambient resistance of 31ºC/W can be
achieved compared to 100 ºC/W found in standard packages. The general relationship between board area and
thermal resistance for this package is shown in the performance curves. It can be readily seen that the thermal
resistance approaches an asymptotic value of approximately 31ºC/W. Additional information can be found in
Application Note #8 (Measuring the Thermal Resistance
of Power Surface-Mount Packages), and Application
Note #13 (EL75XX Thermal Design Considerations).
If the thermal shutdown pin is connected to OUTEN the
IC will enter thermal shutdown when the maximum
junction temperature is reached. For a thermal shutdown
of 135ºC and power dissipation of 2.2W the ambient
temperature is limited to a maximum value of 67ºC (typical). The ambient temperature range can be extended
12
EL7556AC
EL7556AC
Programmable CPU Power Supply Unit
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
February 28, 2000
Elantec Semiconductor, Inc.
675 Trade Zone Blvd
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
European Office: +441-18-977-6020
Japan Technical Center: +81-45-682-5820
Internet: http://www.elantec.com
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Printed in U.S.A.