INTERSIL EL7558DCM

EL7558D
®
Data Sheet
March 27, 2003
Integrated Adjustable 8 Amp
Synchronous Switcher
Features
• Improved temperature and voltage ranges
The EL7558D is an adjustable
synchronous DC:DC switching
regulator optimized for a 5V input and
1.0V-3.8V output. By combining integrated NMOS power
FETS with a HSOP package the EL7558D can supply up to
8A continuous output current without the use of external
power devices or externally attached heat sinks, thereby
minimizing design effort and overall system cost.
• 8A continuous load current
• Precision internal 1% reference
• 1.0V to 3.8V output voltage
• Internal power MOSFETs
• >90% efficiency
• Synchronous switching
On-chip resistorless current sensing is used to achieve
stable, highly efficient, current-mode control. The EL7558D
also incorporates the VCC2DET function to directly interface
with the Intel P54 and P55 microprocessors. Depending on
the state of VCC2DET, the output voltage is internally preset
to 3.50V or a user-adjustable voltage using two external
resistors. In both internal and external feedback modes the
active-high PWRGD output indicates when the regulator
output is within ±10% of the programmed voltage. An onboard sensor monitors die temperature (OT) for overtemperature conditions and can be connected directly to
OUTEN to provide automatic thermal shutdown. Adjustable
oscillator frequency and slope compensation allow added
flexibility in overall system design.
• Adjustable slope compensation
• Over-temperature indicator
• Pulse-by-pulse current limiting
• Operates up to 1MHz
• 1.5% typical output accuracy
• Adjustable oscillator with sync
• Remote enable/disable
• Intel P54- and P55-compatible
• VCC2DET interface
• Internal soft-start
The EL7558D is available in the 28-pin HSOP package and
is specified for operation over the -40°C to +85°C
temperature range.
Applications
Pinout
• Local high power CPU supplies
• PC motherboards
• 5V to 1.0V DC:DC conversion
EL7558D
(28-PIN HSOP)
TOP VIEW
R4
• Portable electronics/instruments
• P54 and P55 regulators
R3
100Ω
FN7342
VIN
150Ω
• GTL+ Bus power supply
D3
C4
1
FB1
2
CREF
FB2 28
3
CSLOPE
0.1µF
C7
CP
27
C2V
26
C8
C5
R1
220pF
D2
1µF
Ordering Information
D4*
(Optional)
20Ω
330pF
4
COSC
5
VDD
VHI 24
6
VIN
LX
23
7
VSSP
LX
22
8
VIN
LX
21
VSS
25
R5
R6
5.1Ω
D1
PACKAGE
TAPE &
REEL
PKG. NO.
EL7558DCM
28-Pin HSOP
-
MDP0042
EL7558DCM-T13
28-Pin HSOP
13”
MDP0042
C11
0.22µF
C6
PART NUMBER
39.2Ω
0.1µF
VIN
C9
C12
660µF
1µF
C3
L1
2.5µH
VOUT
9
VSSP
LX
20
C10
10
VSSP
VSSP
19
1mF
11
VSSP
VSSP
18
12
VSSP
TEST
17
13
VCC2DET
16
PWRGD
14
OUTEN
1µF
Connect to VSSP for
external feedback
C12 = 1µF
C3, C4, C5, C6, C7 C8 - ceramic
C5, C11 - ceramic or tantalum
C9 - Sprague 293D337X96R3 2X330µF
C10 - Sprague 293D337X96R3 3X330µF
L1 - Pulse Engineering, PE-53681
D1 - D4: BAT54S fast diode
D4 Required for EL7558ACM only
OT
15
Manufactured under U.S. Patents No. 5,723,974 and No. 5,793,126
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL7558D
Absolute Maximum Ratings (TA = 25°C)
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Supply (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Output Pins . . . . . . . . . . . . . . .-0.3V below GND, +0.3V above VDD
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 135°C
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25°C unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
25
mA
GENERAL
IDD
VDD Supply Current
OUTEN = 4V, FOSC = 120kHz
11
IDDOFF
VDD Standby Current
OUTEN = 0
0.1
IVIN
VIN No Load Current
OUTEN = 0
3
5
mA
VOUT1
Output Initial Accuracy
VCC2DET = 4V, IL = 3A
3.450
3.500
3.550
V
VOUT2
Output Initial Accuracy
VCC2DET = 0V, IL = 3A R3 = 150Ω,
R4 = 100Ω
2.450
2.500
2.550
V
VOUTLINE
Output line Regulation
VDD = 5V, ±10%
-1
1
%
VOUTLOAD
Output Load Regulation
0A<ILOAD<6A, Relative to IL = 3A.
Continuous Mode of Operation
-1
1
%
RSHORT
Short Circuit Load Resistance
IL = 6A Prior to Continuous Application
of RSHORT. OUTEN Connected to OT.
II MAX
Current Limit
VOUTTC
Output Tempco
TOT
mA
100
mΩ
9
A
±1
%
Over Temperature Threshold
135
°C
THYS
Over Temperature Hysteresis
40
°C
VPWRGD
Power Good Threshold Relative to
Programmed Output Voltage
VDDOFF
Minimum VDD for Shutdown
VDDON
Maximum VDD for Startup
VHYS
Input Hysteresis
MSS
DMAX
-40°C<TA<85°C
VCC2SEL = 4V, VOUT = 3.50V
±6
±10
±14
3.15
V
4.15
VHYS = VDDON-VDDOFF
%
V
0.5
V
Soft start slope
7
V/ns
Maximum duty cycle
96
%
CONTROLLER - INPUTS
IPUP
VCC2DET, OUTEN Pull Up Current
ICSLOPE
Cslope Charging Current
IFB1
FB1 Input Pull Up Current
ROT
Over Temperature Pull Up Resistance
VIH
VCC2DET, OUTEN Input High
VIL
VCC2DET, OUTEN Input Low
VOH PWGD
Powergood Drive High
ILoad = 1mA
VOL PWGD
Powergood Drive Low
ILoad = -1mA
2
VCC2DET, OUTEN = 0
10
14
18
µA
23
28.5
34
µA
2
OT = 0V
30
40
µA
50
4
kΩ
V
.8
3.5
V
V
1.0
V
EL7558D
Electrical Specifications
PARAMETER
VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25°C unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
1.247
1.260
1.273
V
CONTROLLER - REFERENCE
VREF
Reference Accuracy
VREFTC
Reference Voltage Tempco
VREFLOAD
Reference Load Regulation
IREF = 0
50
0<ILOAD<100µA
0.5
VDD = 5V, ILOAD = 10mA
7.5
ppm/ºC
0.5
%/ºC
8.7
V
CONTROLLER - DOUBLER
VC2V
Voltage Doubler Output
8.1
CONTROLLER - OSCILLATOR
FRAMP
Oscillator Ramp Amplitude
IOSC CHG
Oscillator Charge Current
IOSC DIS
Oscillator Discharge Current
FOSC
Oscillator initial accuracy
tsync
Minimum oscillator sync width
1.2
V
0.2V<VOSC<1.4V
150
µA
0.2V<VOSC<1.4V
5
mA
105
125
145
50
kHz
ns
POWER - FET
ILEAK
LX Output Leakage to VSS
RDSON
Composite FET Resistance
RDSONTC
RDSON Tempco
0.1
mΩ/ºC
tBRM
FET break before make delay
10
ns
tLEB
High side FET minimum on time (LEB)
140
ns
3
LX = 0V
18
100
µA
30
mΩ
EL7558D
Typical Performance Curves
Efficiency vs ILOAD (VOUT=3.5V)
Efficiency vs ILOAD (VDD=5.0 V)
97
100
93
VDD=5V
91
VDD=5.5V
VOUT=3.5V
95
VDD=4.5V
Efficiency (%)
Efficiency (%)
95
89
87
90
VOUT=2.5V
85
VOUT=1V
80
75
TA=25°C
85
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
TA=25°C
70
0.5
8.0
1.5
2.5
3.5
IOUT (A)
4.5
5.5
6.5
7.5
8.0
IOUT (A)
Line Regulation (CSLOPE=150pF)
Load Regulation (CSLOPE=150pF)
3.54
3.54
TA=25°C
3.53
3.53
3.52
IOUT=0.5A
3.52
VIN=5.5V
VOUT (V)
VOUT (V)
3.51
3.51
IOUT=4A
3.50
VIN=5V
3.50
3.49
3.49
IOUT=8A
VIN=4.5V
3.48
3.48
3.47
3.47
4.5
3.46
0.5
5.0
5.5
TA=25°C
1
2
VIN (V)
4
5
6
7
8
IOUT (A)
Line Regulation vs CSLOPE (IOUT=3A)
VDD=VIN=5.0V ±10%
Load Regulation vs CSLOPE (VIN=5.0V)
IOUT=0.5 to 6A
0.8
0.6
TA=25°C
0.7
TA=25°C
0.5
0.6
VOUT=3.5V
0.4
VOUT=3.5V
0.5
0.4
∆VOUT (±) (%)
∆VOUT (±) (%)
3
VOUT=2.5V
0.3
VOUT=2.5V
0.3
0.2
0.2
VOUT=1V
0.1
0.1
VOUT=1V
0.0
0.0
50
75
100
125
CSLOPE (pF)
4
150
175
50
75
100
125
CSLOPE (pF)
150
175
EL7558D
Typical Performance Curves
(Continued)
Line Regulation vs CSLOPE
VIN=VDD=5.0V ±10%
Load Regulation vs CSLOPE
IOUT=0.5 to 6A
0.8
0.8
TA=25°C
0.7
0.6
0.5
∆VOUT (±) (%)
0.6
∆VOUT (±) (%)
TA=25°C
0.7
IOUT=0.5A
0.4
0.3
IOUT=6A
0.2
0.5
VIN=4.5A
0.4
VIN=5A
0.3
VIN=5.5A
0.2
0.1
0.1
0.0
50
75
100
125
150
0.0
50
175
75
100
CSLOPE (pF)
125
150
VOUT vs CSLOPE
(VIN=5.0V, ILOAD=.5A)
VOUT Variation vs Programmed Output
Voltage [VIDEAL=(1+R3/R4)]
1.5
1.5
TA=25°C
1.0
1.0
Deviation in VOUT (%)
VOUT=1V
0.5
∆VOUT (±) (%)
175
CSLOPE (pF)
0.0
-0.5
VOUT=2.5V
-1.0
-1.5
0.5
C
SL
C
OP
E=
10
0p
F
22
0p
F
OS
C=
0.0
-0.5
VOUT=3.5V
-2.0
-1.0
-2.5
TA=25°C
Loop Gain Induced Error
-3.0
50
75
100
125
150
-1.5
1.0
175
1.5
2.0
CSLOPE (pF)
2.5
3.0
3.5
4.0
VIDEAL (V)
FOSC vs COSC
FOSC vs Temperature
10000
520
TA=25°C
510
VDD=4.5V
500
FOSC(kHz)
FOSC(kHz)
1000
100
490
VDD=5.5V
480
470
10
VDD=5V
460
1
COSC=220pF
450
10
100
1000
COSC (pF)
5
100000
0
20
40
60
80
Temperature (°C)
100
120
140
EL7558D
Typical Performance Curves
(Continued)
IVDD + IVIN vs FOSC
IVIN vs FOSC
16
60
TA=25°C
OUTEN=VDD
50
TA=25°C
OUTEN=VDD
14
VDD=5.5V
VDD=5.5V
10
30
VDD=4.5V
IVIN (mA)
IVDD + IVIN (mA)
12
40
VDD=5V
VDD=5V
8
6
20
VDD=4.5V
4
10
2
Discontinuous Mode
Continuous Mode
Discontinuous Mode
0
Continuous Mode
0
FOSC (kHz)
FOSC (kHz)
IVDD vs FOSC
RDSON vs Temperature
38
50
TA=25°C
OUTEN=VDD
45
36
VDD=5.5V
40
34
VDD=5V
32
RDSON (m Ω)
IVDD (mA)
35
30
25
VDD=4.5V
20
15
30
28
26
24
10
5
22
0
20
0
25
FOSC (kHz)
50
75
100
125
4.5
5.0
Temperature (°C)
Power On Reset
IQ vs FOSC
40
2.0
TA=25°C
OUTEN=VDD
30
VDD=5V
Iq (mA)
IQ (mA)
VDD=5.5V
1.5
20
FOSC=500k
VDD=4.5V
10
1.0
10
100
FOSC (kHz)
6
1000
0
2.5
3.0
3.5
4.0
VDD (V)
EL7558D
Typical Performance Curves
(Continued)
Minimum Output Voltage vs FOSC
2.3
2.1
TJ=120°C
VDD=5.5V
1.9
VOUT (V)
1.7
VDD=5V
1.5
1.3
VDD=4.5V
1.1
0.9
0.7
200
400
600
800
1000
FOSC (kHz)
Pin Descriptions
I = INPUT, O = OUTPUT, S = SUPPLY
PIN NUMBER
PIN NAME
PIN
TYPE
1
FB1
I
FUNCTION
Voltage feedback pin for the buck regulator. Active when VCC2DET is logic low. Normally connected
to external resistor divider between VOUT and GND. A 2µA pull-up current forces VOUT to VSS in the
event that FB1is floating and VCC2DET is inadvertently connected to GND.
2
CREF
I
Bandgap reference bypass capacitor. Typically 0.1µF to VSS.
3
CSLOPE
I
Slope compensation capacitor. Ramp width corresponds to LX duty cycle. CSLOPE to COSC ratio is
normally 1:1.5.
4
COSC
I
Oscillator timing capacitor. FOSC (Hz) can be approximated by: FOSC (Hz) = 0.0001/COSC. COSC in
Farads.
5
VDD
S
Power Supply for PWM control circuitry. Normally the same potential as VIN.
6
VIN
S
Power supply for the buck regulator. Connected to the drain of the high-side NMOS FET.
7
VSSP
S
Ground return for the buck regulator. Connected to the source of the low-side synchronous NMOS
FET.
8
VIN
S
Same as pin 6.
9
VSSP
S
Same as pin 7.
10
VSSP
S
Same as pin 7.
11
VSSP
S
Same as pin 7.
12
VSSP
S
Same as pin 7.
13
VCC2DET
I
VCC2DET interface logic input. When driven to logic 1 VOUT = 3.500V. When driven to logic 0 the
PWM uses FB1 to determine VOUT: VOUT = 1.0V*(1+R3/R4).
14
OUTEN
I
The switching regulator output is enabled when logic 1. The reference voltage output operates
whenever the power supply is qualified (VDD>VPOR) regardless of the state of this pin.
15
OT
O
Over temperature indicator. Normally high. Pulls low when die temperature exceeds 135°C, returns to
the high state when die temperature has cooled to 100°C.
16
PWRGD
O
Power good window comparator output. Logic 1 when regulator output is within ±10% of programmed
voltage.
17
TEST
I
Test pin. Must be connected to VSSP in normal operation.
18
VSSP
S
Same as pin 7.
19
VSSP
S
Same as pin 7.
20
LX
O
Inductor drive pin. High current switching output whose average voltage equals the regulator output
voltage.
7
EL7558D
Pin Descriptions
(Continued)
I = INPUT, O = OUTPUT, S = SUPPLY
PIN NUMBER
PIN NAME
PIN
TYPE
21
LX
O
Same as pin 20.
22
LX
O
Same as pin 20.
23
LX
O
Same as pin 20.
FUNCTION
24
VHI
I
Gate drive to high-side driver. Bootstrapped from LX with a 0.1µF capacitor.
25
VSS
S
Ground return for the control circuitry.
26
C2V
I
Connected to voltage doubler output. Supplies gate drive to the low-side driver.
27
CP
O
Drives the negative side of charge pump capacitor at one-half the oscillator frequency FOSC.
28
FB2
I
Voltage feedback pin. Active when VCC2DET is logic 1. Internally preset to VOUT = 3.5V.
Block Diagram
PWRGD, Pin 16
CP, Pin 27
-
FB1, Pin1
2-1 MUX
FB2, Pin 28
+
C2V, Pin 26
V2X
-
VHI, Pin 24
+
-
VCCDET, Pin 13
VDD and VIN,
Pin 5,6,8
+
CSLOPE, Pin 3
Current Sense
CREF, Pin 27
LEB TDELAY
1.26V
+
Σ
Current Limit
Q
OUTEN, Pin 14
+
-
R
+ PWM
S
LX, Pin 20-23
Q
VDD
4V
RSS
VSSP, Pin 912, 18-19
UVLO
-
S
+
FF
R
S
-
CSS
+
VDD
Zero Cross Detect
COSC, Pin 4
-
R
+
OT, Pin 15
Over Temp Sensor
VSS, Pin 25
8
EL7558D
Applications Information
Circuit Description
General
The EL7558D is a fixed frequency, current mode controlled
DC:DC converter with integrated N-channel power
MOSFETS and a high precision reference. The device
incorporates all of the active circuitry required to implement
a cost effective, user-programmable 8A synchronous buck
converter suitable for use in CPU power supplies. By
combining HSOP packaging technology with an efficient
synchronous switching architecture, high power outputs
(30W) can be realized without the use of externally attached
heat sinks.
Theory of Operation
The EL7558D is composed of 7 major blocks:
1. PWM Controller
2. Output Voltage Mode Select
3. NMOS Power FETS and Drive Circuitry
4. Bandgap Reference
5. Oscillator
6. Temperature Sensor
7. Power Good and Power On Reset
PWM Controller
The EL7558D regulates output voltage through the use of
current-mode controlled pulse width modulation. The three
main elements in a PWM controller are the feedback loop
and reference, a pulse width modulator whose duty cycle is
controlled by the feedback error signal, and a filter which
averages the logic level modulator output. In a step-down
(buck) converter, the feedback loop forces the time-averaged
output of the modulator to equal the desired output voltage.
Unlike pure voltage-mode control systems current-mode
control utilizes dual feedback loops to provide both output
voltage and inductor current information to the controller.
The voltage loop minimizes DC and transient errors in the
output voltage by adjusting the PWM duty-cycle in response
to changes in line or load conditions. Since the output
voltage is equal to the time-average of the modulator output
the relatively large LC time constants found in power supply
applications generally results in low bandwidth and poor
transient response. By directly monitoring changes in
inductor current via a series sense resistor the controller’s
response time is not entirely limited by the output LC filter
and can react more quickly to changes in line or load
conditions. This feed-forward characteristic also simplifies
AC loop compensation since it adds a zero to the overall
loop response. Through proper selection of the currentfeedback to voltage-feedback ratio, the overall loop response
will approach a one pole system. The resulting system offers
several advantages over traditional voltage control systems,
including simpler loop compensation, pulse by pulse current
9
limiting, rapid response to line variation and good load step
response.
The heart of the controller is a triple-input direct summing
comparator which sums voltage feedback, current feedback
and slope compensating ramp signals together. Slope
compensation is required to prevent system instability which
occurs in current-mode topologies operating at duty-cycles
greater than 50% and is also used to define the open-loop
gain of the overall system. The compensation ramp
amplitude is user adjustable and is set using a single
external capacitor (CSLOPE). Each comparator input is
weighted and determines the load and line regulation
characteristics of the system. Current feedback is measured
by sensing the inductor current flowing through the high-side
switch whenever it is conducting. At the beginning of each
oscillator period the high-side NMOS switch is turned on and
CSLOPE ramps positively from its reset state (VREF
potential). The comparator inputs are gated off for a
minimum period of time (LEB) after the high-side switch is
turned on to allow the system to settle. The Leading Edge
Blanking (LEB) period prevents the detection of erroneous
voltages at the comparator inputs due to switching noise.
When programming low regulator output voltages the LEB
delay will limit the maximum operating frequency of the
circuit since the LEB will result in a minimum duty-cycle
regardless of the PWM error voltage. This relationship is
shown in the performance curves. If the inductor current
exceeds the maximum current limit (ILMAX), a secondary
over-current comparator will terminate the high-side switch.
If ILMAX has not been reached, the regulator output voltage
is then compared to the reference voltage VREF. The
resultant error voltage is summed with the current feedback
and slope compensation ramp. The high-side switch remains
on until all three comparator inputs have summed to zero, at
which time the high-side switch is turned off and the low-side
switch is turned on. In order to eliminate cross-conduction of
the high-side and low-side switches a 10ns break-beforemake delay is incorporated in the switch driver circuitry. In
the continuous mode of operation the low-side switch will
remain on until the end of the oscillator period. In order to
improve the low current efficiency of the EL7558D, a zerocrossing comparator senses when the inductor transitions
through zero. Turning off the low-side switch at zero inductor
current prevents forward conduction through the internal
clamping diodes (LX to VSSP) when the low-side switch
turns off, reducing power dissipation. The output enable
(OUTEN) input allows the regulator output to be disabled by
an external logic control signal.
Output Voltage Mode Select
The VCC2DET multiplexes the FB1 and FB2 pins to the
PWM controller. A logic 1 on VCC2DET selects the FB2
input and forces the output voltage to the internally
programmed value of 3.50V. A logic zero on VCC2DET
EL7558D
selects FB1 and allows the output to be programmed from
1.0 to 3.8V. In general:
R 

V OUT = 1.0V ×  1 + ------3- × Volt
R 4

However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loopgain are changed. This is shown in the performance curves.
(The output voltage is factory trimmed to minimize error at a
2.50V output). A 2µA pull-up current from FB1 to VIN forces
VOUT to GND in the event that FB1 is not used and the
VCC2DET is inadvertently toggled between the internal and
external feedback mode of operation.
NMOS Power FETS and Drive Circuitry
The EL7558D integrates low resistance (25mΩ) NMOS
FETS to achieve high efficiency at 8A. Gate drive for both
the high-side and low-side switches is derived through a
charge pump consisting of the CP pin and external
components D1-D3 and C5-C6. The CP output is a low
resistance inverter driven at one-half the oscillator frequency.
This is used in conjunction with D2-D3 to generate a 7.5V
(typical) voltage on the C2V pin which provides gate drive to
the low-side NMOS switch and associated level shifter. In
order to use an NMOS switch for the high-side drive it is
necessary to drive the gate voltage above the source voltage
(LX). This is accomplished by boot-strapping the VHI pin
above the C2V voltage with capacitor C6 and diode D1.
When the low-side switch is turned on the LX voltage is
close to GND potential and capacitor C6 is charged through
diodes D1-D3 to approximately 6.9V. At the beginning of the
next cycle the high side switch turns on and the LX pin
begins to rise from GND to VDD potential. As the LX pin
rises the positive plate of capacitor C6 follows and eventually
reaches a value of approximately 11.2V, for VDD=5V. This
voltage is then level shifted and used to drive the gate of the
high-side FET, via the VHI pin.
Reference
A 1% temperature compensated band gap reference is
integrated in the EL7558D. The external CREF capacitor
acts as the dominant pole of the amplifier and can be
increased in size to maximize transient noise rejection. A
value of 0.1uF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 96%.
Operating frequency can be adjusted through the COSC pin
or can be driven by an external clock source. If the oscillator
is driven by an external source, care must be taken in the
selection of CSLOPE. Since the COSC and CSLOPE values
determine the open loop gain of the system, changes to
COSC require corresponding changes to CSLOPE in order
to maintain a constant gain ratio. The recommended ratio of
COSC to CSLOPE is 1.5:1
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Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the OT pin will output a logic 0. The upper
and lower trip points are set to 135°C and 100°C
respectively. To enable thermal shutdown this pin should be
tied directly to OUTEN. Use of this feature is recommended
during normal operation.
Power Good and Power On Reset
During power up the output regulator will be disabled until
VIN reaches 4.0V. Approximately 500mV of hysteresis is
present to eliminate noise induced oscillations.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic 1 on the PWRGD output indicates that regulated
output voltage is within ±10% of the nominally programmed
output voltage. Although small, the typical values of the
PWRGD threshold will vary with changes to external
feedback (and resultant loop gain) of the system. This
dependence is shown in the typical performance curves.
Thermal Management
The EL7558D utilizes HSOP packaging technology in
conjunction with the system board layout to achieve a lower
thermal resistance than typically found in standard 28 lead
SOIC packages. By attaching the die directly to an exposed
metal slug embedded within the package body, thermal
energy flows through a thermally conductive path (metal)
instead of thermally resistive plastic. After conducting heat
from the die to the PCB, heat transfer occurs by convection.
If a significant amount of metal on the PCB is connected to
the exposed heat slug, a junction-to-ambient resistance of
31°C/W can be achieved compared to 100°C/W found in
standard packages. It can be readily seen that the thermal
resistance approaches an asymptotic value of approximately
31°C/W. Additional information can be found in Application
Note #8 (Measuring the Thermal Resistance of Power
Surface-Mount Packages), and Application Note #13
(EL75XX Thermal Design Considerations).
If the thermal shutdown pin is connected to OUTEN the IC
will enter thermal shutdown when the maximum junction
temperature is reached. For a thermal shutdown of 135°C
and power dissipation of 2.2W the ambient temperature is
limited to a maximum value of 67°C (typical). The ambient
temperature range can be extended with the application of
air flow. For example, the addition of 100LFM reduces the
thermal resistance by approximately 15% and can extend
the operating ambient to 77°C (typical). Since the thermal
performance of the IC is heavily dependent on the board
layout, the system designer should exercise care during the
design phase to ensure that the IC will operate under the
worst-case environmental conditions.
EL7558D
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