EM78P468N/L 8-Bit Microcontroller Product Specification DOC. VERSION 1.6 ELAN MICROELECTRONICS CORP. December 2007 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2004~2007 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan, ROC The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, TAIWAN 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] Elan Information Technology Group (U.S.A.) Shenzhen: Shanghai: Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 #23, Zone 115, Lane 572, Bibo Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 P.O. Box 601 Cupertino, CA 95015 U.S.A. Tel: +1 408 366-8225 Fax: +1 408 366-8225 Contents Contents 1 2 3 4 5 6 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Pin Assignment ......................................................................................................... 2 Block Diagram ........................................................................................................... 3 Pin Description.......................................................................................................... 4 Function Description ................................................................................................ 6 6.1 Operational Registers......................................................................................... 6 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 6.1.17 6.2 R0/IAR (Indirect Addressing Register) ................................................................6 R1/TCC (Timer Clock Counter) ...........................................................................6 R2/PC (Program Counter)...................................................................................6 R3/SR (Status Register) .....................................................................................8 R4/RSR (RAM Select Register) ..........................................................................9 R5/Port 5 (Port 5 I/O Data and Page of Register Select.....................................9 R6/Port 6 (Port 6 I/O Data Register) ...................................................................9 R7/Port 7 (Port 7 I/O Data Register) ...................................................................9 R8/Port 8 (Port 8 I/O Data Register) .................................................................10 R9/LCDCR (LCD Control Register)...................................................................10 RA/LCD_ADDR (LCD Address) ........................................................................11 RB/LCD_DB (LCD Data Buffer) ........................................................................11 RC/CNTER (Counter Enable Register).............................................................11 RD/SBPCR (System, Booster and PLL Control Register) ................................12 RE/IRCR (IR and Port 5 Setting Control Register) ...........................................13 RF/ISR (Interrupt Status Register) ....................................................................14 Address: 10h~3Fh; R10~R3F (General Purpose Register) ..............................14 Special Purpose Registers ............................................................................... 15 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12 6.2.13 6.2.14 6.2.15 6.2.16 A (Accumulator).................................................................................................15 IOC50/P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment Control Register)..15 IOC60/P6CR (Port 6 I/O Control Register) .......................................................16 IOC70/P7CR (Port 7 I/O Control Register) .......................................................16 IOC80/P8CR (Port 8 I/O Control Register) .......................................................16 IOC90/RAM_ADDR (128 Bytes RAM Address) ................................................16 IOCA0/RAM_DB (128 Bytes RAM Data Buffer)................................................16 IOCB0/CNT1PR (Counter 1 Preset Register)...................................................17 IOCC0/CNT2PR (Counter 2 Preset Register)...................................................17 IOCD0/HPWTPR (High-Pulse Width Timer Preset Register) ...........................17 IOCE0/LPWTPR (Low-Pulse Width Timer Preset Register) .............................18 IOCF0/IMR (Interrupt Mask Register) ...............................................................18 IOC61/WUCR (Wake-up and Sink Current of P5.7/IROUT Control Register) .18 IOC71/TCCCR (TCC Control Register) ............................................................19 IOC81/WDTCR (WDT Control Register)...........................................................20 IOC91/CNT12CR (Counters 1, 2 Control Register) ..........................................20 Product Specification (V1.6) 12.31.2007 • iii Contents 6.2.17 6.2.18 6.2.19 6.2.20 6.2.21 IOCA1/HLPWTCR (High/Low Pulse Width Timer Control Register)................21 IOCB1/P6PH (Port 6 Pull-high Control Register)..............................................22 IOCC1/P6OD (Port 6 Open Drain Control Register).........................................22 IOCD1/P8PH (Port 8 Pull High Control Register) .............................................22 IOCE1/P6PL (Port 6 Pull Low Control Register) ...............................................22 6.3 TCC and WDT Prescaler.................................................................................. 23 6.4 I/O Ports ........................................................................................................... 25 6.6 Oscillator .......................................................................................................... 30 6.6.1 6.6.2 6.6.3 6.6.4 6.7 Oscillator Modes................................................................................................30 Phase Lock Loop (PLL Mode)...........................................................................30 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................31 RC Oscillator Mode with Internal Capacitor ......................................................32 Power-on Considerations ................................................................................. 32 6.7.1 6.7.2 External Power-on Reset Circuit .......................................................................33 Residue-Voltage Protection...............................................................................33 6.8 Interrupt ............................................................................................................ 34 6.9 LCD Driver........................................................................................................ 35 6.9.1 6.9.2 6.9.3 6.9.4 R9/LCDCR (LCD Control Register)...................................................................35 RA/LCD_ADDR (LCD Address) ........................................................................36 RB/LCD_DB (LCD Data Buffer) ........................................................................36 RD/SBPCR (System, Booster and PLL Control Registers) ..............................37 6.10 Infrared Remote Control Application/PWM Waveform Generation.................. 41 6.11 Code Options ................................................................................................... 45 6.12 Instruction Set ................................................................................................. 46 7 8 9 6.13 Timing Diagram ................................................................................................ 49 Absolute Maximum Ratings ................................................................................... 50 Electrical Characteristic ......................................................................................... 50 8.1 DC Electrical Characteristics............................................................................ 50 8.2 AC Electrical Characteristics ............................................................................ 52 8.3 Device Characteristic ....................................................................................... 53 Application Circuit .................................................................................................. 65 APPENDIX A B C D E Package Type........................................................................................................... 66 Package Information............................................................................................... 67 EM78P468N/L Program Pin List ............................................................................. 72 ICE 468XA ................................................................................................................ 73 Quality Assurance and Reliability ......................................................................... 76 E.1 Address Trap Detect......................................................................................... 76 iv • Product Specification (V1.6) 12.31.2007 Contents Specification Revision History Doc. Version 1.0 1.1 1.2 Revision Description Initial version 1. Added DC curve vs. Temperature. 2. Removed the LVD function 1. Added LQFP Package Date 2004/04/10 2004/12/09 2005/03/15 1. Combined EM78P468N with EM78P468L Specification. 1.3 2. Deleted the wake-up function from Idle mode by TCC time out. 2006/05/05 3. Added power-on voltage detector in the Features section. 1. Modified the General Description, Features and Pin Assignment. 1.4 2. Added Green Product Information. 2007/01/11 3. Modified the Functional Block Diagram. 4. Added Appendix D Quality Assurance and Reliability. 1.5 Deleted all the packages for the EM78P468L 2007/02/15 1.6 Added QFP-64 Package EM78P468NEQ 2007/12/31 Product Specification (V1.6) 12.31.2007 •v Contents vi • Product Specification (V1.6) 12.31.2007 EM78P468N/L 8-Bit Microcontroller 1 General Description The EM78P468N/L is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. Integrated onto a single chip are on chip Watchdog Timer (WDT), Data RAM, ROM, programmable real time clock counter, internal/external interrupt, power down mode, LCD driver, infrared transmitter function, and tri-state I/O. The series has an on-chip 4K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). The EM78P468L provides multi-protection bits to prevent intrusion of user’s OTP memory code. Seven Code option bits are available to meet user’s requirements. Special 13 bits customer ID options are provided as well. With its enhanced OTP-ROM feature, the EM78P468N/L provides a convenient way of developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code. 2 Features CPU Configuration Peripheral Configuration • 4K×13 bits on-chip OTP-ROM • 8-bit real time clock/counter (TCC) • 144 bytes general purpose register • One infrared transmitter / PWM generator function • 128 bytes on-chip data RAM • 272 bytes SRAM • Four sets of 8 bits auto reload down-count timer can be used as interrupt sources • 8 level stacks for subroutine nesting • Power-on voltage detector provided (2.0±0.1V) for EM78P468N • Power-on voltage detector provided (1.7±0.1V) for EM78P468L I/O Port Configuration • Typically, 12 bi-directional tri-state I/O ports. • 16 bi-directional tri-state I/O ports shared with LCD segment output pin. • Up to 28 bi-directional tri-state I/O ports Operating Voltage and Temperature Range: • Commercial: 2.3V ~ 5.5 V. (at 0°C~+70°C) Industrial: 2.5V ~ 5.5 V. (at -40°C ~+85°C) EM78P468L • • Commercial: 2.1 V ~ 5.5 V. (at 0°C ~+70°C) Industrial: 2.3V ~ 5.5 V. (at -40°C ~+85°C) Operating Mode: • Normal mode: The CPU is operated on main oscillator frequency (Fm) • Green mode: The CPU is operated on sub-oscillator frequency (Fs) and main oscillator (Fm) is stopped • Idle mode: CPU idle, LCD display remains working • Sleep mode: The whole chip stops working ♦ Input port wake-up function (Port 6, Port 8). Works on Idle and Sleep mode. ♦ ♦ Operation speed: DC ~ 10MHz clock input Dual clock operation Oscillation Mode • High frequency oscillator can select among Crystal, RC, or PLL (phase lock loop) • Low frequency oscillator can select between Crystal or RC mode Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) Counter 1: independent down-count timer Counter 2, High Pulse Width Timer (HPWT), and Low Pulse Width Timer (LPWT) shared with IR function. ♦ Programmable free running on chip watchdog timer (WDT). This function can operate on Normal, Green and Idle mode. Eight Interrupt Sources: Three External and Five Internal • Internal interrupt source: TCC; Counters 1, 2; High/Low pulse width timer. • External interrupt source : INT0, INT1 and Pin change wake-up (Port 6 and Port 8) EM78P468N • ♦ ♦ LCD Circuit • Common driver pins: 4 • Segment driver pins: 32 • LCD Bias: 1/3, 1/2 bias • LCD Duty: 1/4, 1/3, 1/2 duty Package Type: • Dice form: 59 pins • QFP-64 pin: EM78P468NQxS/xJ (Body 14mm × 20mm) • LQFP-64 pin: EM78P468NAQxS/xJ (Body 7mm × 7mm) • LQFP-44 pin: EM78P468NBQxS/xJ (Body 10mm × 10mm) • QFP-44 pin: EM78P468NCQxS/xJ (Body 10mm × 10mm) • QFP-64 pin: EM78P468NEQxS/xJ (Body 14mm × 14mm) Note: Green products do not contain hazardous substances •1 EM78P468N/L 8-Bit Microcontroller Pin Assignment 4 2 4 1 4 0 3 9 3 8 3 7 3 6 P5.5/INT1 4 3 NC 4 4 P5.6/TCC 4 5 NC 4 6 P6.0 4 7 P5.7/IROUT P6.1 4 8 P6.2 3 3 P6.3 3 4 P6.4 3 5 P6.5 3 6 P6.6 3 7 P6.7 3 8 NC 3 9 SEG31/P8.7 4 0 P5.5/INT1 4 1 NC 4 2 P5.6/TCC 4 3 P6.0 P6.1 4 4 NC P6.2 4 5 P5.7/IROUT P6.3 4 6 P6.4 4 7 P6.7 4 8 P6.5 4 9 P6.6 NC 5 0 NC NC 5 1 SEG31/P8.7 SEG30/P8.6 (2) 64-Pin LQFP SEG29/P8.5 (1) 64-Pin QFP NC 3 3 5 3 4 3 3 SEG28/P8.4 52 32 P5.4/INT0 NC 49 32 P5.4/INT0 SEG27/P8.3 53 31 XOUT SEG30/P8.6 50 31 XOUT SEG26/P8.2 54 30 XIN SEG29/P8.5 51 30 XIN SEG25/P8.1 55 29 VDD SEG28/P8.4 52 29 VDD SEG24/P8.0 56 28 OSCO SEG27/P8.3 53 SEG23/P7.7 57 27 R-OSCI SEG26/P8.2 54 SEG22/P7.6 58 26 GND SEG25/P8.1 55 SEG21/P7.5 59 25 /RESET SEG24/P8.0 56 SEG20/P7.4 60 24 VLCD3 SEG19/P7.3 61 23 VLCD2 SEG23/P7.7 57 SEG18/P7.2 62 22 VA SEG22/P7.6 58 SEG17/P7.1 63 21 VB SEG21/P7.5 SEG16/P7.0 64 20 COM0 R-OSCI VB SEG19/P7.3 61 20 COM0 SEG18/P7.2 62 19 COM1 SEG17/P7.1 63 18 COM2 SEG16/P7.0 64 17 COM3 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 SEG 0 5 SEG 1 4 SEG 5 3 SEG 9 2 SEG10 Fig. 3-1 64-pin QFP 1 SEG 2 21 SEG 3 60 SEG 4 VA SEG20/P7.4 SEG 6 22 SEG 7 VLCD2 59 SEG 8 VLCD3 23 SEG11 24 SEG12 GND /RESET SEG13 1 9 OSCO 27 25 COM1 1 8 COM2 1 7 COM3 1 6 SEG 0 1 5 SEG 1 1 4 SEG 2 1 3 SEG 3 1 2 SEG 4 1 1 SEG 5 1 0 SEG 6 9 SEG 7 8 SEG 8 7 SEG 9 6 SEG10 5 SEG11 4 SEG12 3 SEG13 2 SEG14 SEG15 1 28 26 SEG14 QFP-64 EM78P468NAQ LQFP-64 EM78P468NEQ QFP-64 SEG15 EM78P468NQ Fig. 3-2 64-pin LQFP/QFP 2 3 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 P5.6/TCC 2 4 P6.0 P5.6/TCC 2 5 P5.7/IROUT P5.7/IROUT 2 6 P6.1 P6.0 2 7 P6.2 P6.1 2 8 P6.3 P6.2 2 9 P6.4 P6.3 3 0 P6.5 P6.4 3 1 P6.7 P6.5 3 2 P6.6 P6.6 3 3 SEG28/P8.4 P6.7 (4) 44-Pin QFP SEG28/P8.4 (3) 44-Pin LQFP 2 5 2 4 2 3 SEG27/P8.3 34 22 P5.5/INT1 SEG27/P8.3 34 22 P5.5/INT1 SEG26/P8.2 35 21 P5.4/INT0 SEG26/P8.2 35 21 P5.4/INT0 SEG25/P8.1 36 20 XOUT SEG25/P8.1 36 20 XOUT SEG24/P8.0 37 19 XIN SEG24/P8.0 37 SEG23/P7.7 38 18 VDD SEG23/P7.7 SEG22/P7.6 39 17 OSCO SEG21/P7.5 40 16 R-OSCI SEG20/P7.4 41 15 SEG19/P7.3 42 14 SEG18/P7.2 43 13 VLCD3 SEG17/P7.1 44 12 VLCD2 1 1 SEG14 SEG13 SEG12 SEG11 COM3 COM2 COM1 COM0 VB VA Fig. 3-3 44-pin LQFP GND SEG20/P7.4 41 15 GND /RESET SEG19/P7.3 42 14 /RESET SEG18/P7.2 43 13 VLCD3 SEG17/P7.1 44 12 VLCD2 QFP-44 1 2 3 4 5 6 7 8 9 1 0 1 1 VA 1 0 R-OSCI VB 9 OSCO 16 COM0 8 17 40 COM1 7 39 SEG21/P7.5 COM2 6 SEG22/P7.6 COM3 5 VDD SEG11 4 18 SEG12 3 XIN 38 SEG13 2 19 SEG14 1 SEG16/P7.0 LQFP-44 EM78P468NCQ SEG16/P7.0 EM78P468NBQ Fig. 3-4 44-pin QFP 2• Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Input Pin Output Pin Input/Output Pin Digital I/O Pin/LCD Output Pin LCD Output Pin 4 Block Diagram P8 P80 P81 P82 P83 P84 P85 P86 P87 ROM PC Instruction Register 8-level stack (13-bit) Crystal Oscillation Generation P7 P70 P71 P72 P73 P74 P75 P76 P77 PLL Instruction Decoder Rese t LCD WDT PWM1/IR (Timer 1,2) Mux. ALU TCC CNTR 1 P6 P60 P61 P62 P63 P64 P65 P66 P67 RC CNTR 2 R4 PWM TCC CNTR1 CNTR2 RAM ACC R3 (Status Reg.) Interrupt Control Register P5 P50 P51 P52 P53 P54 P55 P56 P57 Interrupt Circuit Ext INT Fig. 4 System Block Diagram Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) •3 EM78P468N/L 8-Bit Microcontroller 5 Pin Description Table 1 (a) Pin Description for Package of QFP64 and LQFP64 Symbol Type Function 1-bit General purpose input/output pin/external interrupt. INT0 interrupt source can be set to falling or rising edge by IOC71 register Bit 7 (INT_EDGE). Wakes up from sleep mode and idle mode when the pin status changes. 1-bit General purpose input/output pin/external interrupt. Interrupt source is a falling edge signal. Wakes up from sleep mode and idle mode when the pin status changes. P5.4/INT0 32 I/O P5.5/INT1 33 I/O P5.6/TCC 34 I/O P5.7/IROUT 37 I/O P6.0~P6.7 38~45 I/O COM3~0 17~20 O SEG0~SEG15 16~1 O SEG16/P7.0 ~ SEG23/P7.7 64 ~ 57 O/(I/O) LCD segment output pin. Can be shared with general purpose I/O pin SEG24/P8.0 ~ SEG30/P8.6 SEG31/P8.7 56 ~ 50 46 O/(I/O) LCD segment output pin. Can be shared with general I/O pin. For general purpose I/O use, can wake up from sleep mode and idle mode when the pin status changes. For general purpose I/O use, supports pull-high function. VB 21 O Connect capacitors for LCD bias voltage. VA 22 O Connect capacitors for LCD bias voltage. VLCD2 23 O One of LCD bias voltage. VLCD3 24 O /RESET 25 I R-OSCI 27 I One of LCD bias voltage. General-purpose Input only Low active. If it remains at logic low, the device will be reset. In Crystal mode: crystal input In RC mode: resistor pull high. In PLL mode: connect 0.01μF capacitance to GND Connect 0.01μF capacitor to GND and code option select PLL mode when high oscillator is not use OSCO 28 O Xin 30 I Xout 31 o 35~36 47~49 − No connection VDD 29 I GND 26 I Power supply System ground pin NC 4• Pin No. 1-bit General purpose input/output pin/external counter input. This pin works in normal/green/idle mode. 1-bit General purpose input/output pin/IR/PWM mode output pin. This pin is capable of sinking 20mA/5V. 8-bit General purpose input/output pins. Pull-high, pull-low and open drain function supported. All pins can wake up from sleep and idle modes when the pin status changes LCD common output pin. LCD segment output pin. In Crystal mode: crystal input In RC mode: instruction clock output In Crystal mode: Input pin for sub-oscillator. Connect to a 32.768kHz crystal. In Crystal mode: Connect to a 32.768kHz crystal. In RC mode: instruction clock output Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Table 2 (b) Pin Description for Package of QFP44 and LQFP44 Symbol Pin No. Type P5.4/INT0 21 I/O P5.5/INT1 22 I/O P5.6/TCC 23 I/O P5.7/IROUT 24 I/O 25~32 I/O P6.0~P6.7 COM3~0 6~9 O SEG11~SEG14 5~2 O SEG16/P7.0 SEG17/P7.1 ~ SEG23/P7.7 1 44 ~ 38 O/(I/O) SEG24/P8.0 ~ SEG31/P8.4 37 ~ 33 O/(I/O) VB 10 O VA 11 O VLCD2 12 O VLCD3 13 O /RESET 14 I Function 1-bit General purpose input/output pin/external interrupt. The INT0 interrupt source can be set to falling or rising edge by IOC71 register Bit 7 (INT_EDGE). Wakes up from sleep mode and idle mode when the pin status changes. 1-bit General purpose input/output pin/external interrupt. The Interrupt source is a falling edge signal. Wakes up from sleep mode and idle mode when the pin status changes. 1-bit General purpose input/output pin/external counter input. This pin works in normal/green/idle mode. 1-bit General purpose input/output pin/IR/PWM mode output pin This pin is capable of sinking 20mA/5V. 8-bit General purpose input/output pins Pull-high, pull-low and open drain function supported. All pins can wake up from sleep and idle modes when the pin status changes. LCD common output pin. LCD segment output pin. LCD segment output pin. Can be shared with general purpose I/O pin LCD segment output pin. Can be shared with general I/O pin For general purpose I/O use, can wake up from sleep mode and idle mode when the pin status changes. For general purposes I/O use, supports pull-high function. Connect capacitors for LCD bias voltage. Connect capacitors for LCD bias voltage. One of LCD bias voltage. One of LCD bias voltage. General-purpose Input only Low active. If it remains at logic low, the device will be reset. In Crystal mode: crystal input In RC mode: resistor pull high. In PLL mode: connect 0.01μF capacitance to GND Connect 0.01μF capacitor to GND and code option select PLL mode when high oscillator is not use In Crystal mode: crystal input In RC mode: instruction clock output In Crystal mode: Input pin for sub-oscillator. Connect to a 32.768kHz crystal. R-OSCI 16 I OSCO 17 O Xin 19 I Xout 20 o In Crystal mode: Connect to a 32.768kHz crystal. In RC mode: instruction clock output VDD 18 I Power supply GND 15 I System ground pin Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) •5 EM78P468N/L 8-Bit Microcontroller 6 Function Description 6.1 Operational Registers 6.1.1 R0/IAR (Indirect Addressing Register) (Address: 00h) R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a register, actually accesses the data pointed by the RAM Select Register (R4). 6.1.2 R1/TCC (Timer Clock Counter) (Address: 01h) The Timer Clock Counter is incremented by an external signal edge applied to TCC, or by the instruction cycle clock. It is written and read by the program as any other register. 6.1.3 R2/PC (Program Counter) (Address: 02h) 6• The structure of R2 is depicted in Fig. 6-1, Program Counter Organization. The configuration structure generates 4K×13 bits on-chip ROM addresses to the relative programming instruction codes. The contents of R2 are all set to "0"s when a Reset condition occurs. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows the PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of the stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged. The most significant bits (A10~A11) will be loaded with the content of PS0~PS1 in the Status register (R3) upon execution of a "JMP" or "CALL" instruction. Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller R3 PC A11 00 PAGE0 0000~03FF 01 PAGE1 0400~07FF A10 A9 A8 CALL RET RETL RETI 10 PAGE2 0800~0BFF A7 ~ STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 Reset v ector 000H TCC ov erf low interrupt v ector 003H Exteral INT0 pin interrupt v ector 006H Exteral INT1 pin interrupt v ector 009H Counter 1 underf low interrupt v ector 00CH Counter 2 underf low interrupt v ector 00FH high pulse width timer underf low interrupt v ector 012H low pulse width timer underf low interrupt v ector 015H Port 6,Port8 pin change wake-up interrupt v ector 018H STACK LEVEL 7 STACK LEVEL 8 On-Chip Programmemory User Memory Space STACK LEVEL 3 11 PAGE3 0C00~0FFF A0 FFFH Fig 6-1 Program Counter Organization ADDRESS 0 0 IAR (Indirect Addressing Register) 0 1 TCC (Time Clock Counter) 0 2 PC (Program Counter) 0 3 SR (Status Register) 0 4 RSR (RAM select register) 0 5 PORT5 (Port 5 & IOCPAGE Control) 0 6 PORT6 (Port6 I/O data register) 0 7 PORT7 (Port7 I/O data register) 0 8 PORT8 (Port8 I/O data register) 0 9 LCDCR (LCD control register) 0 A LCD_ADDR (LCD address) 0 B LCD_DB (LCD data buffer) 0 C CNTER (Counter enable register) 0 D SBPCR (System, Booster , PLL control) 0 E IRCR (IR, Pin of IR;INT0/1;TCC control) 0 F ISR (interrupt status register) R5 bit 0 -> 0 control register page 0 R5 bit 0 -> 1 control register page 1 P5CR (Port5 I/O & LCD segment control) P6CR (Port6 I/O control register) WUCR (Wake up & P5.7 sink current) P7CR (Port7 I/O control register) TCCCR (TCC & INT0 control register) P8CR (Port8 I/O control register) WDTCR (WDT control register) RAM_ADDR (128 byte RAM address) CNT12CR (Counter 1,2 control register) RAM_DB (128 byte RAM data buffer) HLPWTCR (high/low pulse width timer control) CNT1PR (Counter 1 preset register) P6PH (Port 6 pull-high control register) CNT2PR (Counter 2 preset register) P6OD (Port 6 open drain control register) HPWTPR (High-pulse width timer preset) P8PH (Port 8 pull-high control register) LPWTPR (Low-pulse width timer preset) P6PL (Port 6 pull-low control register) IMR (interrupt mask register) 10 | 1F 16 byte common register LCD RAM 4*32 bits 20 | 3F bank 0 ~ bank 3 32 byte common register 128 byte data RAM Fig. 6-2 Data Memory Configuration Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) •7 EM78P468N/L 8-Bit Microcontroller 6.1.4 R3/SR (Status Register) (Address: 03h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − PS1 PS0 T P Z DC C Bit 7: Not used Bits 6 ~ 5 (PS1 ~ 0): Page select bits PS1 PS0 ROM Page (Address) 0 0 Page 0 (000H ~ 3FFH) 0 1 Page 1 (400H ~ 7FFH) 1 0 Page 2 (800H ~ BFFH) 1 1 Page 3 (C00H ~ FFFH) PS0~PS1 are used to select a ROM page. User can use the PAGE instruction (e.g. PAGE 1) or set PS1~PS0 bits to change the ROM page. When executing a "JMP", "CALL", or other instructions which causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine was called, regardless of the current setting of PS0~PS1 bits. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands or during power up and reset to 0 by WDT timeout. Event T P Remark WDT wake up from sleep mode 0 0 − WDT time out (not sleep mode) 0 1 − /RESET wake up from sleep 1 0 − Power up 1 1 − Low pulse on /RESET 1 1 ×: don't care Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 2 (Z): Zero flag Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 8• Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.1.5 R4/RSR (RAM Select Register) (Address: 04h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBS1 RBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 Bits 7 ~ 6 (RBS1 ~ RBS0): determine which bank is activated among the four banks. See the data memory configuration in Fig. 6-2. Use the BANK instruction (e.g. BABK 1) to change banks. Bits 5 ~ 0 (RSR5 ~ RSR0): used to select up to 64 registers (Address: 00~3F) in indirect addressing mode. If no indirect addressing is used, the RSR can be used as an 8-bit general purpose read/writer register. 6.1.6 R5/Port 5 (Port 5 I/O Data and Page of Register Select (Address: 05h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R57 R56 R55 R54 − − − IOCPAGE Bits 7~4: Four bits I/O registers of Port 5 User can use the IOC50 register to define each bit either as input or output. Bits 3~1: Not used Bit 0 (IOCPAGE): change IOC5 ~ IOCF to another page IOCPAGE = “0” : Page 0 (select register of IOC 50 to IOC F0) IOCPAGE = “1” : Page 1 (select register of IOC 61 to IOC E1) 6.1.7 R6/Port 6 (Port 6 I/O Data Register) (Address: 06h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R67 R66 R65 R64 R63 R62 R61 R60 Bits 7~0: 8-bit I/O registers of Port 6 User can use the IOC60 register to define each bit either as input or output. 6.1.8 R7/Port 7 (Port 7 I/O Data Register) (Address: 07h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R77 R76 R75 R74 R73 R72 R71 R70 Bits 7~0: 8-bit I/O registers of Port 7 User can use the IOC70 register to define each bit either as input or output. Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) •9 EM78P468N/L 8-Bit Microcontroller 6.1.9 R8/Port 8 (Port 8 I/O Data Register) (Address: 08h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R87 R86 R85 R84 R83 R82 R81 R80 Bits 7~0: 8-bit I/O registers of Port 8 User can use IOC80 register to define each bit either as input or output. 6.1.10 R9/LCDCR (LCD Control Register) (Address: 09h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BS DS1 DS0 LCDEN -- LCDTYPE LCDF1 LCDF0 Bit 7 (BS): LCD bias select bit, BS = “0”: 1/2 bias BS = “1”: 1/3 bias Bit 6 ~ 5 (DS1 ~ DS0): LCD duty select DS1 DS0 LCD Duty 0 0 1/2 duty 0 1 1/3 duty 1 × 1/4 duty Bit 4 (LCDEN): LCD enable bit LCDEN = “0”: LCD circuit disabled. All common/segment outputs are set to ground (GND) level. LCDEN = “1”: LCD circuit enabled. Bit 3: Not used Bit 2 (LCDTYPE): LCD drive waveform type select bit LCDTYPE = “0” : A type waveform LCDTYPE = “1” : B type waveform Bits 1 ~ 0 (LCDF1 ~ LCDF0): LCD frame frequency control bits LCDF1 LCD Frame Frequency (e.g. Fs=32.768kHz) LCDF0 1/2 Duty 1/3 Duty 1/4 Duty 0 0 Fs/(256×2)=64.0 Fs/(172×3)=63.5 Fs/(128×4)=64.0 0 1 Fs/(280×2)=58.5 Fs/(188×3)=58.0 Fs/(140×4)=58.5 1 0 Fs/(304×2)=53.9 Fs/(204×3)=53.5 Fs/(152×4)=53.9 1 1 Fs/(232×2)=70.6 Fs/(156×3)=70.0 Fs/(116×4)=70.6 Note: Fs: sub-oscillator frequency 10 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.1.11 RA/LCD_ADDR (LCD Address) (Address: 0Ah) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0 Bits 7~5: Not used, fixed to “0” Bits 4~0 (LCDA4 ~ LCDA0): LCD RAM addresses RA (LCD Address) Bits 7 ~4 RB (LCD Data Buffer) Bit 3 Bit 2 Bit 1 Bit 0 (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0) Segment 00H − − − − − SEG0 01H − − − − − SEG1 02H − − − − − SEG2 1DH − − − − − SEG29 1EH − − − − − SEG30 SEG31 | | | 1FH − − − − − Common × COM3 COM2 COM1 COM0 6.1.12 RB/LCD_DB (LCD Data Buffer) (Address: 0Bh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − LCD_D3 LCD_D2 LCD_D1 LCD_D0 Bit 1 Bit 0 CNT2EN CNT1EN Bits 7~4: Not used Bits 3~0 (LCD_D3 ~ LCD_D0) : LCD RAM data transfer register 6.1.13 RC/CNTER (Counter Enable Register) (Address: 0Ch) Bit 7 Bit 6 Bit 5 Bit 4 − − − − Bit 3 Bit 2 LPWTEN HPWTEN Bits 7, 5: Not used, must be fixed to “0” Bits 6, 4: Not used Bit 3 (LPWTEN): low pulse width timer enable bit LPWTEN = “0” : Disable LPWT. Stop counting operation. LPWTEN = “1” : Enable LPWT. Start counting operation. Bit 2 (HPWTEN): high pulse width timer enable bit HPWTEN = “0” : Disable HPWT. Stop counting operation. HPWTEN = “1” : Enable HPWT. Start counting operation. Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 11 EM78P468N/L 8-Bit Microcontroller Bit 1 (CNT2EN): Counter 2 enable bit CNT2EN = “0” : Disable Counter 2. Stop counting operation. CNT2EN = “1” : Enable Counter 2. Start counting operation. Bit 0 (CNT1EN): Counter 1 enable bit CNT1EN = “0” : Disable Counter 1. Stop counting operation. CNT1EN = “1” : Enable Counter 1. Start counting operation. 6.1.14 RD/SBPCR (System, Booster and PLL Control Register) (Address: 0Dh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − CLK2 CLK1 CLK0 IDLE BF1 BF0 CPUS Bit 7: Not used Bits 6 ~ 4 (CLK2 ~ CLK0): main clock selection bits for PLL mode (code option select) CLK2 CLK1 CLK0 Main clock Example Fs=32.768K 0 0 0 Fs×130 4.26 MHz 0 0 1 Fs×65 2.13 MHz 0 1 0 Fs×65/2 1.065 MHz 0 1 1 Fs×65/4 532 kHz 1 × × Fs×244 8 MHz Bit 3 (IDLE): Idle mode enable bit. This bit will determine the intended mode of the SLEP instruction. Idle = ”0”+SLEP instruction → Sleep mode Idle = ”1”+SLEP instruction → Idle mode * NOP instruction must be added after SLEP instruction. Example : Idle mode : Idle bit = “1” +SLEP instruction + NOP instruction Sleep mode : Idle bit = “0” +SLEP instruction + NOP instruction Bits 2, 1 (BF1, 0): LCD booster frequency select bit to adjust VLCD 2, 3 driving. BF1 BF0 Booster Frequency 0 0 Fs 0 1 Fs/4 1 0 Fs/8 1 1 Fs/16 Bit 0 (CPUS): CPU oscillator source select, When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped. CPUS = “0”: sub-oscillator (Fs) CPUS = “1”: main oscillator (Fm) 12 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller CPU Operation Mode Code option HLFS=1 Normal Mode Code option HLFS=0 fm:oscillation fs:oscillation it must delay a little times for the main oscillation stable w hile your system timing control is conscientious RESET CPU: using fosc CPUS="0" CPUS="1" SLEEP Mode IDLE="0" SLEP IDLE="1" SLEP Green Mode Fm:stop Fs: stop fm:stop fs:oscillation Wake up CPU: stop IDLE Mode fm:stop fs:oscillation w ake up CPU: using fs CPU: stop The w ake up time from idle to green mode is 16*1/fs The w ake up time from sleep to green mode is approximately sub-oscillator setup time +18ms+16*1/fs Fig. 6-3 CPU Operation Mode 6.1.15 RE/IRCR (IR and Port 5 Setting Control Register) (Address: 0Eh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRE HF LGP − IROUTE TCCE EINT1 EINT0 Bit 7 (IRE): Infrared Remote Enable bit IRE = “0” : Disable the IR/PWM function. The state of P5.7/IROUT pin is determined by Bit 7 of IOC 50 if it is for IROUT. IRE = “1” : Enable IR or PWM function. Bit 6 (HF): High carry frequency HF = “0” : For PWM application, disable the H/W modulator function. The IROUT waveform is generated according to high-pulse and low-pulse time as determined by the respective high pulse and low pulse width timers. Counter 2 is an independent auto reload timer. HF = “1” : For IR application mode, enable the H/W modulator function, the low time sections of the generated pulse is modulated with the Fcarrier frequency. The Fcarrier frequency is provided by Counter 2. Bit 5 (LGP): IROUT for of low pulse width timer LGP = “0” : The high-pulse width timer register and low-pulse width timer is valid. LGP = “1” : The high-pulse width timer register is ignored. So the IROUT waveform is dependent on the low-pulse width timer register only. Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 13 EM78P468N/L 8-Bit Microcontroller Bit 4: Not used Bit 3 (IROUTE): Define the function of P5.7/IROUT pin. IROUTE = “0” : for bi-directional general I/O pin. IROUTE = “1” : for IR or PWM output pin, the control bit of P5.7 (Bit 7 of IOC50) must be set to “0” Bit 2 (TCCE): Define the function of P5.6/TCC pin. TCCE = “0” : for bi-directional general I/O pin. TCCE = “1” : for external input pin of TCC, the control bit of P5.6 (Bit 6 of IOC50) must be set to “1” Bit 1 (EINT1): Define the function of P5.5/INT1 pin. EINT1 = “0” : for bi-directional general I/O pin. EINT1 = “1” : for external interrupt pin of INT1, the control bit of P5.5 (Bit 5 of IOC50) must be set to “1” Bit 0 (EINT0) : Define the function of P5.4/INT0 pin. EINT0 = “0” : for bi-directional general I/O pin. EINT0 = “1” : for external interrupt pin of INT0, the control bit of P5.4 (Bit 4 of IOC50) must be set to “1” 6.1.16 RF/ISR (Interrupt Status Register) (Address: 0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICIF LPWTF HPWTF CNT2F CNT1F INT1F INT0F TCIF These bits are set to “1” when interrupt occurs respectively. Bit 7 (ICIF): Port 6, Port 8, input status changed interrupt flag. Set when Port 6, Port 8 input changes. Bit 6 (LPWTF): interrupt flag of the internal low-pulse width timer underflow. Bit 5 (HPWTF): interrupt flag of the internal high-pulse width timer underflow. Bit 4 (CNT2F): interrupt flag of the internal Counter 2 underflow. Bit 3 (CNT1F): interrupt flag of the internal Counter 1 underflow. Bit 2 (INT1F): external INT1 pin interrupt flag. Bit 1 (INT0F): external INT0 pin interrupt flag. Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows. 6.1.17 Address: 10h~3Fh; R10~R3F (General Purpose Register) R10~R31F and R20~R3F (Banks 0~3) are general purpose registers. 14 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.2 Special Purpose Registers 6.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. Registers of IOC Page 0 (IOC50 ~ IOCF0, Bit 0 of R5 = “0”) 6.2.2 IOC50/P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment Control Register) (Address: 05h, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC57 IOC56 IOC55 IOC54 P8HS P8LS P7HS P7LS Bits 7~4 (IOC57~54): Port 5 I/O direction control register IOC5x = “0”: set the relative P5.x I/O pins as output IOC5x = “1”: set the relative P5.x I/O pin into high impedance (input pin) Bit 3 (P8HS): Switch to high nibble I/O of Port 8 or to LCD segment output while sharing pins with SEGxx/P8.x pins. P8HS = “0”: select high nibble of Port 8 as normal P8.4~P8.7 P8HS = “1”: select LCD segment output as SEG 28~SEG 31 output Bit 2 (P8LS): Switch to low nibble I/O of Port 8 or to LCD segment output while sharing pins with SEGxx/P8.x pins P8LS = “0”: select low nibble of Port 8 as normal P8.0~P8.3 P8LS = “1”: select LCD Segment output as SEG 24~SEG 27 output Bit 1 (P7HS): Switch to high nibble I/O of Port 7 or to LCD segment output while sharing pins with SEGxx/P7.x pins P7HS = “0”: select high nibble of Port 7 as normal P7.4~P7.7 P7HS = “1”: select LCD Segment output as SEG 20~SEG 23 output Bit 0 (P7LS): Switch to low nibble I/O of Port 7 or to LCD segment output while sharing pins with SEGxx/P7.x pins P7LS = “0”: select low nibble of Port 7 as normal P7.0~P7.3 P7LS = “1”: select LCD segment output as SEG 16~SEG 19 output Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 15 EM78P468N/L 8-Bit Microcontroller 6.2.3 IOC60/P6CR (Port 6 I/O Control Register) (Address: 06h, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 Bit 7 (IOC67) ~ Bit 0(IOC60): Port 6 I/O direction control register IOC6x =”0”: set the relative Port 6.x I/O pins as output IOC6x =”1”: set the relative Port 6.x I/O pin into high impedance (input pin) 6.2.4 IOC70/P7CR (Port 7 I/O Control Register) (Address: 07h, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70 Bit 7 (IOC77) ~ Bit 0 (IOC70): Port 7 I/O direction control register IOC7x = “0”: set the relative Port 7.x I/O pins as output IOC7x = “1”: set the relative Port 7.x I/O pin into high impedance (input pin) 6.2.5 IOC80/P8CR (Port 8 I/O Control Register) (Address: 08h, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80 Bit 7 (IOC 87) ~ Bit 0 (IOC 80): Port 8 I/O direction control register IOC8x = “0”: set the relative Port 8.x I/O pins as output IOC8x = “1”: set the relative Port 8.x I/O pin into high impedance (input pin) 6.2.6 IOC90/RAM_ADDR (128 Bytes RAM Address) (Address: 09h, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0 Bit 7: Not used, fixed at “0” Bits 6~0: 128 bytes RAM address 6.2.7 IOCA0/RAM_DB (128 Bytes RAM Data Buffer) (Address: 0Ah, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 Bits 7~0: 128 bytes RAM data transfer register 16 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.2.8 IOCB0/CNT1PR (Counter 1 Preset Register) (Address: 0Bh, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 ~ Bit 0: These are Counter 1 buffers which user can read and write. Counter 1 is an 8-bit down-count timer with 8-bit prescaler used to preset the counter and read the preset value. The prescaler is set by the IOC91 register. After an interrupt, it will auto reload the preset value. 6.2.9 IOCC0/CNT2PR (Counter 2 Preset Register) (Address: 0Ch, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 ~ Bit 0: These are Counter 2 buffers which user can read and write. Counter 2 is an 8-bit down-count timer with 8-bit prescaler used to preset the counter and read the preset value. The prescaler is set by IOC91 register. After an interrupt, it will reload the preset value. When IR output is enabled, this control register can obtain carrier frequency output. If the Counter 2 clock source is equal to FT , then Carrier frequency (Fcarrier) = FT 2 * (preset _ value + 1) * prescaler 6.2.10 IOCD0/HPWTPR (High-Pulse Width Timer Preset Register) (Address: 0Dh, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 ~ Bit 0: These are high-pulse width timer buffers which user can read and write. High-pulse width timer preset register is an eight-bit down-counter with 8-bit prescaler used as IOCD0 to preset the counter and read the preset value. The prescaler is set by the IOCA1 register. After an interrupt, it will reload the preset value. For PWM or IR application, this control register is set as high pulse width. If the high-pulse width timer clock source is FT , then High pulse time = Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) prescaler * (preset _ value + 1) FT • 17 EM78P468N/L 8-Bit Microcontroller 6.2.11 IOCE0/LPWTPR (Low-Pulse Width Timer Preset Register) (Address: 0Eh, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 ~ Bit 0: All are low-pulse width timer buffer that user can read and write. Low-pulse width timer preset is an eight-bit down-counter with 8-bit prescaler that is used as IOCE0 to preset the counter and read preset value. The prescaler is set by IOCA1 register. After an interrupt, it will reload the preset value. For PWM or IR application, this control register is set as low pulse width. If the low-pulse width timer clock source is FT , then Low pulse time = prescaler * (preset _ value + 1) FT 6.2.12 IOCF0/IMR (Interrupt Mask Register) (Address: 0Fh, Bit 0 of R5 = “0”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICIE LPWTE HPWTE CNT2E CNT1E INT1E INT0E TCIE Bit 7 ~ Bit 0: interrupt enable bit. Enable the respective interrupt source. 0: disable interrupt 1: enable interrupt IOCF0 register is readable and writable. Registers of IOC Page 1 (IOC61 ~ IOCE1, Bit 0 of R5 = “1”) 6.2.13 IOC61/WUCR (Wake-up and Sink Current of P5.7/IROUT Control Register) (Address: 06h, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IROCS -- -- -- /WUE8H /WUE8L /WUE6H /WUE6L Bit 7: IROCS: IROUT/Port 5.7 output sink current set IROCS P5.7/IROUT Sink Current VDD=5V VDD=3V 0 10 mA 6 mA 1 20 mA 12 mA Bits 6, 5, 4: Not used Bit 3 (/WUE8H): 0/1→ enable/disable P8.4~P8.7 pin change wake-up function 18 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Bit 2 (/WUE8L): 0/1 → enable/disable P8.0~P8.3 pin change wake-up function Bit 1 (/WUE6H): 0/1 → enable/disable P6.4~P6.7 pin change wake-up function Bit 0 (/WUE6L): 0/1 → enable/disable P6.0~P6.3 pin change wake-up function * Port 6 and Port 8 must not be set as input floating when wake-up function is enabled. “Enable” is the initial state of wake-up function. 6.2.14 IOC71/TCCCR (TCC Control Register) (Address: 07h, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INT_EDGE INT TS TE PSRE TCCP2 TCCP1 TCCP0 Bit 7 (INT_EDGE): INT_EDGE = “0”: Interrupt on the rising edge of P5.4/INT0 pin INT_EDGE = “1”: Interrupt on the falling edge of P5.4/INT0 pin Bit 6 (INT): INT enable flag, this bit is read only INT = “0”: interrupt masked by DISI or hardware interrupt INT = “1”: interrupt enabled by ENI/RETI instructions Bit 5 (TS): TCC signal source TS = “0”: internal instruction cycle clock TS = “1”: transition on TCC pin, TCC period > internal instruction clock period Bit 4 (TE): TCC signal edge TE = “0”: incremented by TCC pin rising edge TE = “1”: incremented by TCC pin falling edge Bits 3~0 (PSRE, TCCP2 ~ TCCP0): TCC prescaler bits. PSRE TCCP2 TCCP1 TCCP0 TCC Rate 0 × × × 1:1 1 0 0 0 1:2 1 0 0 1 1:4 1 0 1 0 1:8 1 0 1 1 1:16 1 1 0 0 1:32 1 1 0 1 1:64 1 1 1 0 1:128 1 1 1 1 1:256 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 19 EM78P468N/L 8-Bit Microcontroller 6.2.15 IOC81/WDTCR (WDT Control Register) (Address: 08h, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − WDTE WDTP2 WDTP1 WDTP0 Bits 7 ~ 4: Not used Bit 3 (WDTE): Watchdog timer enable. This control bit is used to enable the Watchdog timer, WDTE = “0”: Disable WDT function WDTE = “1”: enable WDT function Bits 2 ~ 0 (WDTP2 ~ WDTP0): Watchdog Timer prescaler bits. The WDT clock source is sub-oscillation frequency. WDTP2 WDTP1 WDTP0 WDT Rate 0 0 0 1:1 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 6.2.16 IOC91/CNT12CR (Counters 1, 2 Control Register) (Address: 09h, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CNT2S CNT2P2 CNT2P1 CNT2P0 CNT1S CNT1P2 CNT1P1 CNT1P0 Bit 7(CNT2S): Counter 2 clock source select “0”: Fs (Fs: sub-oscillator clock) “1”: Fm (Fm: main-oscillator clock) Bits 6~4 (CNT2P2 ~ CNT2P 0): Counter 2 prescaler select bits 20 • CNT2P2 CNT2P1 CNT1P0 Counter 2 Scale 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Bit 3 (CNT1S): Counter 1 clock source select “0”: Fs (Fs: sub-oscillator clock) “1”: Fm (Fm: main-oscillator clock) Bits 2~0 (CNT1P2 ~ CNT1P20): Counter 1 prescaler select bits CNT1P2 CNT1P1 CNT1P0 Counter 1 Scale 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 6.2.17 IOCA1/HLPWTCR (High/Low Pulse Width Timer Control Register) (Address: 0Ah, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LPWTS LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0 Bit 7 (LPWTS): low-pulse width timer clock source select “0”: Fs (Fs: sub-oscillator clock) “1”: Fm (Fm: main-oscillator clock) Bits 6~4 (LPWTP2~ LPWTP0): low-pulse width timer prescaler select bits LPWTP2 0 0 0 0 1 1 1 1 LPWTP1 0 0 1 1 0 0 1 1 LPWTP0 0 1 0 1 0 1 0 1 Low-pulse Width Timer Scale 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Bit 3 (HPWTS): high-pulse width timer clock source select “0”: Fs (Fs: sub-oscillator clock) “1”: Fm (Fm: main-oscillator clock) Bits 2~0 (HPWTP2~ HPWTP0): high-pulse width timer prescaler select bits HPWTP2 0 0 0 0 1 1 1 1 HPWTP1 0 0 1 1 0 0 1 1 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) HPWTP0 0 1 0 1 0 1 0 1 High-pulse Width Timer Scale 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 • 21 EM78P468N/L 8-Bit Microcontroller 6.2.18 IOCB1/P6PH (Port 6 Pull-high Control Register) Address: 0Bh, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PH67 PH66 PH65 PH64 PH63 PH62 PH61 PH60 Bit 7 ~ Bit 0 (PH67 ~ PH60): The enable bits of Port 6 pull high function. PH6x = “0”: disable pin of P6.x internal pull-high resistor function PH6x = “1”: enable pin of P6.x internal pull-high resistor function 6.2.19 IOCC1/P6OD (Port 6 Open Drain Control Register) (Address: 0Ch, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OP67 OP66 OP65 OP64 OP63 OP62 OP61 OP60 Bit 7 ~ Bit 0: The enable bits of Port 6 open drain function. OD6x = “0”: disable pin of P6.x open drain function OD6x = “1”: enable pin of P6.x open drain function 6.2.20 IOCD1/P8PH (Port 8 Pull High Control Register) (Address: 0Dh, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PH87 PH86 PH85 PH84 PH83 PH82 PH81 PH80 Bit 7 ~ Bit 0: The enable bits of PORT 8 pull-high function. PH8x = “0”: disable pin of P8.x internal pull-high resistor function PH8x = “1”: enable pin of P8.x pull-high resistor function 6.2.21 IOCE1/P6PL (Port 6 Pull Low Control Register) (Address: 0Eh, Bit 0 of R5 = “1”) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PL67 PL66 PL65 PL64 PL63 PL62 PL61 PL60 Bit 7 ~ Bit 0: The enable bits of Port 6 pull low function. PL6x = “0”: disable pin of P6.x internal pull-low resistor function PL6x = “1”: enable pin of P6.x internal pull-low resistor function 22 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.3 TCC and WDT Prescaler Two 8-bit counters are available as prescalers for the TCC (Time Clock Counter) and WDT (Watchdog Timer). The TCCP2~TCCP0 bits of the IOC71 register are used to determine the ratio of the TCC prescaler. Likewise, the WDTP2~WDTP0 bits of the IOC81 register are used to determine the WDT prescaler. The TCC prescaler (TCCP2~TCCP0) is cleared by the instructions each time they are written into TCC, while the WDT prescaler is cleared by the “WDTC” and “SLEP” instructions. Fig.7 depicts the circuit diagram of TCC and WDT. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be selected by internal instruction clock or external signal input (edge selectable from the TCC control register). If the TCC signal source is from the internal instruction clock, the TCC will be incremented by 1 at every instruction cycle (without prescaler). If the TCC signal source is from an external clock input, the TCC will be incremented by 1 at every falling edge or rising edge of the TCC pin. The Watchdog Timer is a free running on sub-oscillator. The WDT will keep on running even after the oscillator driver has been turned off. During Normal mode, Green mode, or Idle mode operation, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the Normal mode and Green mode by software programming. Refer to WDTE bit of IOC81 register. The WDT time-out period is equal to (prescaler × 256 / (Fs/2)). Data Bus TCC (R1) Instruction Clock = Fosc /2 Fosc: CPU operate frequency TCC Pin MUX Prescaler PSRE TCCP2~0 (IOC71) (IOC71) TE (IOC71) 8 to 1 MUX TCCoverflow interrupt TS (IOC71) Fig. 6-4(a) Block Diagram of TCC WDT 8 bit counter WDTE (IOC81) 8 to 1 MUX Prescaler WDT Time out WDTP2~0 (IOC81) Fs/2 (Fs:Sub oscillator) Fig. 6-4(b) Block Diagram of WDT Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 23 EM78P468N/L 8-Bit Microcontroller WDT Setting Flowchart START N Use WDT function ? Y Enable WDT function : set bit 7 of Code option Word 0 to "0" Setting WDT prescaler (IOC81 register) Disable WDT function : set bit 7 of Code option Word 0 to "1" WDTtime= prescaler*256/Fs Fs: sub-oscillator frequency Enable WDT (bit 3 of IOC81) END TCC Setting Flowchart START from External Input TCC clock source? External/ instruction cycle from Instruction Cycle *set clock source from external TCC pin (set bit 4 of IOC71 to "1") *choose TCC clock source from instruction cycle (set bit 4 of IOC71 to "0") *set P5.6/TCC for TCC input Pin ( set bit 2 of RE to "1" and set bit 6 of IOC 50 to "1") *choose TCC prescaler (set by bit 0 to bit 3 of IOC71) *choose TCC pin operation edge (set by bit 4 of IOC71) *choose TCC prescaler (set by bit 0 to bit 3 of IOC71) * Enable TCC interrupt Mask (set bit 0 of IOCF0 to "1") *Clear TCC interrupt Flag (set bit 0 of RF to "0") Enable TCC to start count (use ENI instruction) END 24 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.4 I/O Ports The I/O registers, (Port 5, Port 6, Port 7 and Port 8), are bi-directional tri-state I/O ports. Port 6 and Port 8 are pulled-high internally by software; Port 6 is also pulled-low internally by software. Furthermore, Port 6 has its open-drain output also through software. Port 6 and Port 8 features an input status changed interrupt (or wake-up) function and is pulled-high by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC50 ~ IOC80). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits are shown in Fig. 6-5. Note: Open-drain, pull-high, and pull down are not shown in the figure. Fig. 6-5 The Circuit of I/O Port and I/O Control Register for Port 5 ~ 8 6.5 Reset and Wake-up A reset can be activated by POR (Power-on Reset) WDT timeout. (if enabled) /RESET pin goes to low Note: The reset circuit is always enabled. It will reset the CPU at 1.9V. Once a reset occurs, the following functions are performed The oscillator is running, or will be started The program counter (R2/PC) is set to all "0" All I/O port pins are configured as input mode (high-impedance state) The TCC/Watchdog timer and prescaler are cleared When power is on, the Bits 5 and 6 of R3 and the upper two bits of R4 are cleared. Bits of the IOC71 register are set to all "1" except for Bit 6 (INT flag) For other registers, see Table 2 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 25 EM78P468N/L 8-Bit Microcontroller Table 2 Summary of Registers Initialized Values Address 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x06 26 • Name Reset Type Bit 7 Bit 6 Bit Name IOC57 IOC56 Power-on 1 1 IOC50 /RESET & WDT 1 1 (P5CR) Wake-up from P P Pin Change Bit Name IOC67 IOC66 Power-on 1 1 IOC60 /RESET & WDT 1 1 (P6CR) Wake-up from P P Pin Change Bit Name IOC77 IOC76 Power-on 1 1 IOC70 /RESET & WDT 1 1 (P7CR) Wake-up from P P Pin Change Bit Name IOC87 IOC86 Power-on 1 1 IOC80 /RESET & WDT 1 1 (P8CR) Wake-up from P P Pin Change Bit Name X RAM_A6 Power-on 0 0 IOC90 /RESET & WDT 0 0 (RAM_ADDR) Wake-up from P P Pin Change RAM_D7 RAM_D6 Bit Name Power-on U U IOCA0 /RESET & WDT P P (RAM_DB) Wake-Up from P P Pin Change Bit Name Bit 7 Bit 6 Power-on 0 0 IOCB0 /RESET & WDT 0 0 (CNT1PR) Wake-up from P P Pin Change Bit Name Bit 7 Bit 6 Power-on 0 0 IOCC0 /RESET & WDT 0 0 (CNT2PR) Wake-up from P P Pin Change Bit Name Bit 7 Bit 6 Power-on 0 0 IOCD0 /RESET & WDT 0 0 (HPWTPR) Wake-up from P P Pin Change Bit Name Bit 7 Bit 6 Power-on 0 0 IOCE0 /RESET & WDT 0 0 (LPWTPR) Wake-up from P P Pin Change Bit Name ICIE LPWTE Power-on 0 0 IOCF0 /RESET & WDT 0 0 (IMR) Wake-up from P P Pin Change Bit Name IROCS X Power-on 0 U IOC61 /RESET & WDT 0 U (WUCR) Wake-up from P U Pin Change Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC55 1 1 IOC54 1 1 P8HS 0 0 P8LS 0 0 P7HS 0 0 P7LS 0 0 P P P P P P IOC65 1 1 IOC64 1 1 IOC63 1 1 IOC62 1 1 IOC61 1 1 IOC60 1 1 P P P P P P IOC75 1 1 IOC74 1 1 IOC73 1 1 IOC72 1 1 IOC71 1 1 IOC70 1 1 P P P P P P IOC85 1 1 IOC84 1 1 IOC83 1 1 IOC82 1 1 IOC81 1 1 IOC80 1 1 P P P P P P RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 U P U P U P U P U P U P P P P P P P Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 P P P P P P Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 P P P P P P Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 P P P P P P Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 P P HPWTE CNT2E 0 0 0 0 P P X U U X U U U U P P P P CNT1E 0 0 INT1E 0 0 INT0E 0 0 TCIE 0 0 P P P P /WUE8H /WUE8L /WUE6H /WUE6L 0 0 0 0 0 0 0 0 P P P P Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Address 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x00 0x01 0x02 0x03 0x04 Name Reset Type Bit Name Power-on IOC71 (TCCCR) /RESET & WDT Wake-up from Pin Change Bit Name Power-on IOC81 (WDTCR) /RESET &WDT Wake-up from Pin Change Bit Name Power-on IOC91 /RESET & WDT (CNT12CR) Wake-up from Pin Change Bit Name Power-on IOCA1 /RESET & WDT (HLPWTCR) Wake-up from Pin Change Bit Name Power-on IOCB1 /RESET & WDT (P6PH) Wake-up from Pin Change Bit Name Power-on IOCC1 /RESET & WDT (P6OD) Wake-up from Pin Change Bit Name Power-on IOCD1 /RESET & WDT (P8PH) Wake-up from Pin Change Bit Name Power-on IOCE1 /RESET & WDT (P6PL) Wake-up from Pin Change Bit Name Power-on R0 /RESET & WDT (IAR) Wake-up from Pin Change Bit Name Power-on R1 /RESET & WDT (TCC) Wake-up from Pin Change Bit Name Power-on R2 /RESET & WDT (PC) Wake-up from Pin Change Bit Name Power-on R3 /RESET & WDT (SR) Wake-up from Pin Change Bit Name Power-on R4 /RESET & WDT (RSR) Wake-up from Pin Change Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INT_EDGE 1 1 INT 0 0 TS 1 1 TE 1 1 PSRE 1 1 TCCP2 1 1 TCCP1 1 1 TCCP0 1 1 P P P P P P P P X U U X U U X U U X U U WDTE 0 0 U U U P U CNT2S 0 0 P P P CNT2P2 CNT2P1 CNT2P0 CNT1S CNT1P2 CNT1P1 CNT1P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P LPWTS 0 0 WDTP2 WDTP1 WDTP0 1 1 1 1 1 1 P P P P P P LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P PH67 0 0 PH66 0 0 PH65 0 0 PH64 0 0 PH63 0 0 PH62 0 0 PH61 0 0 PH60 0 0 P P P P P P P P OP67 0 0 OP66 0 0 OP65 0 0 OP64 0 0 OP63 0 0 OP62 0 0 OP61 0 0 OP60 0 0 P P P P P P P P PH87 0 0 PH86 0 0 PH85 0 0 PH84 0 0 PH83 0 0 PH82 0 0 PH81 0 0 PH80 0 0 P P P P P P P P PL67 0 0 PL66 0 0 PL65 0 0 PL64 0 0 PL63 0 0 PL62 0 0 PL61 0 0 PL60 0 0 P P P P P P P P Bit 7 U P Bit 6 U P Bit 5 U P Bit 4 U P Bit 3 U P Bit 2 U P Bit 1 U P Bit 0 U P P P P P P P P P Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 P P P P P P P P Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 Jump to address 0x0018 or continue to execute next instruction X U U PS1 0 0 PS0 0 0 T 1 t P 1 t Z U P DC U P C U P U P P t t P P P Bank 1 0 0 Bank 0 0 0 − U P − U P − U P − U P − U P − U P P P P P P P P P Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 27 EM78P468N/L 8-Bit Microcontroller Address 0x05 0x06 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 ~ 0x3F Name Reset Type Bit Name Power-on R5 /RESET & WDT (Port 5) Wake-up from Pin Change Bit Name Power-on R6 /RESET & WDT (Port 6) Wake-up from Pin Change Bit Name Power-on R7 /RESET & WDT (Port 7) Wake-up from Pin Change Bit Name Power-on R8 /RESET & WDT (Port 8) Wake-up from Pin Change Bit Name Power-on R9 /RESET & WDT (LCDCR) Wake-up from Pin Change Bit Name Power-on RA /RESET & WDT (LCD_ADDR) Wake-up from Pin Change Bit Name Power-on RB /RESET & WDT (LCD_DB) Wake-up from Pin Change Bit Name Power-on RC /RESET & WDT (CNTER) Wake-up from Pin Change Bit Name Power-on RD /RESET & WDT (SBPCR) Wake-up from Pin Change Bit Name Power-on RE /RESET & WDT (IRCR) Wake-up from Pin Change Bit Name Power-on RF /RESET & WDT (ISR) Wake-up from Pin Change Bit Name Power-on R10~R3F /RESET & WDT Wake-up from Pin Change Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R57 1 1 R56 1 1 R55 1 1 R54 1 1 X U U X U U X U U IOCPAGE 0 0 P P P P U U U P R67 1 1 R66 1 1 R65 1 1 R64 1 1 R63 1 1 R62 1 1 R61 1 1 R60 1 1 P P P P P P P P R77 1 1 R76 1 1 R75 1 1 R74 1 1 R73 1 1 R62 1 1 R71 1 1 R70 1 1 P P P P P P P P R87 1 1 R86 1 1 R85 1 1 R84 1 1 R83 1 1 R82 1 1 R81 1 1 R80 1 1 P P P P P P P P BS 1 1 DS1 1 1 DS0 0 0 LCDEN 0 0 X U U LCDTYPE 0 0 LCDF1 0 0 LCDF0 0 0 P P P P U P P P X 0 0 X 0 0 X 0 0 LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0 0 0 0 0 0 0 0 0 0 0 P P P P X U U X U U X U U X U U U U U U X 0 0 X 1 1 X 0 0 X 0 0 P P P P LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0 U P U P U P U P P P P P LPWTEN HPWTEN CNT2EN CNT1EN 0 0 0 0 0 0 0 0 P P 0 P P P P P X U U CLK2 0 0 CLK1 0 0 CLK0 0 0 IDLE 1 1 BF1 0 0 BF0 0 0 CPUS *1 *1 U P P P P P P P IRE 0 0 HF 0 0 LGP 0 0 X U U IROUTE 0 0 TCCE 0 0 EINT1 0 0 EINT0 0 0 P P U P ICIF 0 0 LPWTF HPWTF CNT2F 0 0 0 0 0 0 P P P P CNT1F 0 0 INT1F 0 0 INT0F 0 0 TCIF 0 0 N P P P P P P P Bit 7 U P Bit 6 U P Bit 5 U P Bit 4 U P Bit 3 U P Bit 2 U P Bit 1 U P Bit 0 U P P P P P P P P P Note: This bit is equal to the Code Option HLFS bit data Legend: “×” = not used 28 • “P” = previous value before reset “−” = Not defined “t” = check R3 register explanation “u” = unknown or don’t care “N” = Monitors interrupt operation status Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows: Wake-up Signal TCC time out IOCF0 Bit 0=1 Sleep Mode Idle Mode × × Green Mode Normal Mode Interrupt Interrupt INT0 pin IOCF0 Bit 1=1 Wake-up + interrupt + next instruction Wake-up + interrupt + next instruction Interrupt Interrupt INT1 pin IOCF0 Bit 2=1 Wake-up + interrupt + next instruction Wake-up + interrupt + next instruction Interrupt Interrupt Counter 1 IOCF0 Bit 3=1 × Wake-up + interrupt + next instruction Interrupt Interrupt Counter 2 IOCF0 Bit 4=1 × Wake-up + interrupt + next instruction Interrupt Interrupt High-pulse timer IOCF0 Bit 5=1 × Wake-up + interrupt + next instruction Interrupt Interrupt Low-pulse timer IOCF0 Bit 6=1 × Wake-up + interrupt + next instruction Interrupt Interrupt Port 6, Port 8 Wake-up (input status change wake-up) + next instruction Bit 7 of IOCF0 = “0” Wake-up + next instruction × × Port 6, Port 8 Wake-up (input status + interrupt change wake-up) + next instruction Bit 7 of IOCF0 = “1” Wake-up + interrupt + next instruction × × RESET RESET WDT time out × Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) RESET • 29 EM78P468N/L 8-Bit Microcontroller 6.6 Oscillator 6.6.1 Oscillator Modes The EM78P468N/EM78P468L can operate in three different oscillator modes: a.) Main oscillator (R-OSCI, OSCO), such as RC oscillator with external resistor and Internal capacitor mode (ERIC) b.) Crystal oscillator mode c.) PLL operation mode (R-OSCI connected to 0.01μF capacitor to Ground). User can select which mode by programming FMMD1 and FMMD0 in the Code Options Register. The sub-oscillator can be operated in Crystal mode and ERIC mode. Table 3 below shows how these three modes are defined. Table 3 Oscillator Modes as defined by FSMD, FMMD1, FMMD0. FSMD FMMD1 FMMD0 Main Clock Sub-clock 0 0 0 RC type (ERIC) RC type (ERIC) 0 0 1 Crystal type RC type (ERIC) 0 1 × PLL type RC type (ERIC) 1 0 0 RC type (ERIC) Crystal type 1 0 1 Crystal type Crystal type 1 1 × PLL type Crystal type Table 4 Summary of maximum operating speeds Conditions Two clocks VDD Fxt Max. (MHz) 2.3 4 3.0 8 5.0 10 6.6.2 Phase Lock Loop (PLL Mode) When operate on PLL mode, the High frequency determined by sub-oscillator. We can choose RD register to change high oscillator frequency. The relation between high frequency (Fm) and sub-oscillator is shown as below table: Fig. 6-6 PLL Mode Circuit 30 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Bits 6~4 (CLK2~0) of RD: main clock selection bits for PLL mode (code option select) CLK2 CLK1 CLK0 0 0 0 0 1 0 0 1 1 × 0 1 0 1 × Main clock Example Fs=32.768kHz Fs × 130 Fs × 65 Fs × 65/2 Fs × 65/4 Fs × 244 4.26 MHz 2.13 MHz 1.065 MHz 532kHz 8 MHz 6.6.3 Crystal Oscillator/Ceramic Resonators (Crystal) This LSI can be driven by an external clock signal through the R-OSCI pin as shown in Fig. 6-7 below. In most applications, the R-OSCI pin and the OSCO pin can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-8 depicts such circuit. Table 5 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode. R-OSCI EM78P468N OSCO Fig. 6-7 External Clock Input Circuit Fig. 6-8 Circuit for Crystal/Resonator Table 5 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Source Oscillator Type Frequency C1 (pF) C2 (pF) Ceramic Resonators 455kHz 2.0 MHz 100~150 20~40 100~150 20~40 4.0MHz 455kHz 1.0MHz 2.0MHz 10~30 20~40 15~30 15 10~30 20~150 15~30 15 4.0MHz 32.768kHz 15 25 15 25 Main oscillator Crystal Oscillator Sub-oscillator Crystal Oscillator Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 31 EM78P468N/L 8-Bit Microcontroller 6.6.4 RC Oscillator Mode with Internal Capacitor If both precision and cost are taken into consideration, this LSI also offers a special oscillation mode, which has an on-chip internal capacitor and an external resistor connected to VDD. The internal capacitor functions as temperature compensator. In order to obtain more accurate frequency, a precise resistor is recommended. VDD Rext R-OSCI or Xin EM78P468N Fig. 6-9 Circuit for Internal C Oscillator Mode Table 6 RC Oscillator Frequencies Pin R-OSCI Xin Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C 51k 2.2221 MHz 2.1972 MHz 100k 1.1345 MHz 1.1203 MHz 300k 381.36kHz 374.77kHz 2.2M 32.768kHz 32.768kHz Note: Measured from QFP packages with frequency drift of about ±30%. Values are provided for design reference only. 6.7 Power-on Considerations Any microcontroller (as with this LSI) is not warranted to start operating properly before the power supply stabilizes in a steady state. This LSI has an on-chip Power-on Reset (POR) with detection level range as shown on the table below. The circuitry eliminates the extra external reset circuit but will work well only if the VDD rises quickly enough (50 ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems. Power-on voltage detector provided 32 • IC Voltage Range EM78P468N 1.9V to 2.1V EM78P468L 1.6V to 1.8V Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.7.1 External Power-on Reset Circuit This circuit implements an external RC to produce a reset pulse (see Fig. 6-10). The pulse width (time constant) should be kept long enough to allow VDD to reach minimum operation voltage. This circuit is used when the power supply rise time is slow. Because the current leakage from the /RESET pin is ±5μA, it is recommended that R should not be greater than 40K. In this way, the voltage at Pin /RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET. Fig. 6-10 External Power-on Reset Circuit 6.7.2 Residue-Voltage Protection When battery is replaced, device power (VDD) is disconnected but residue-voltage remains. The residue-voltage may trips below minimum VDD, but above zero. This condition may cause poor power on reset. Fig. 6-11 and Fig. 6-12 show how to build a residue-voltage protection circuit Fig. 6-11 Residue Voltage Protection Circuit 1 Fig. 6-12 Residue Voltage Protection Circuit 2 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 33 EM78P468N/L 8-Bit Microcontroller 6.8 Interrupt This LSI has eight interrupt sources as listed below: TCC overflow interrupt. External interrupt P5.4/INT0 pin External interrupt P5.5/INT1 pin Counter 1 underflow interrupt Counter 2 underflow interrupt High-pulse width timer underflow interrupt Low-pulse width timer underflow interrupt Port 6, Port 8 input status change wake-up This IC has internal interrupts which are falling edge triggered or as follows: TCC timer overflow interrupt Four 8-bits down counter/timer underflow interrupt If these interrupt sources change signal from high to low, the RF register will generate a “1” flag to the corresponding register if the IOCF0 register is enabled. RF is the interrupt status register. It records the interrupt request in flag bit. IOCF0 is the interrupt mask register. Global interrupt is enabled by ENI instruction and disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetch from address 0003H~0018H according to interrupt source. With this LSI, each individual interrupt source has its own interrupt vector as depicted in Table 3. Before the interrupt subroutine is executed, the contents of the ACC and the R3 register are initially saved by the hardware. After the interrupt service routine is completed, the ACC and R3 are restored. The existing interrupt service routine does not allow other interrupt service routine to be executed. Hence, if other interrupts occur while an existing interrupt service routine is being executed, the hardware will save the later interrupts. Only after the existing interrupt service routine is completed that the next interrupt service routine is executed. Interrupt Source ENI / DISI ACC Interrupt STACKACC Occurs R3 STACKR3 RETI Fig. 6-13 Interrupt Back-up Diagram 34 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Table 3 Interrupt Vector Interrupt Vector Interrupt Status 0003H TCC overflow interrupt. 0006H External interrupt P5.4/INT0 pin 0009H External interrupt P5.5/INT1 pin 000CH Counter 1 underflow interrupt 000FH Counter 2 underflow interrupt 0012H High-pulse width timer underflow interrupt 0015H Low-pulse width timer underflow interrupt 0018H Port 6, Port 8 input status change wake up 6.9 LCD Driver This LSI can drive an LCD of up to 32 segments and 4 commons that can drive a total of 4×32 dots. The LCD block is made up of an LCD driver, display RAM, segment output pins, common output pins, and LCD operating power supply pins. This circuit works on normal mode, green mode and idle mode. The LCD duty; bias; the number of segment; the number of common and frame frequency are determined by the LCD controller register. The basic structure contains a timing control that uses a subsystem clock to generate the proper timing for different duty and display accesses. The R9 register is a command register for the LCD driver which includes LCD enable/disable, bias (1/2 and 1/3), duty (1/2, 1/3, 1/4), and LCD frame frequency control. The register RA is an LCD contrast and LCD RAM address control register. The register RB is an LCD RAM data buffer. LCD booster circuit can change the operation frequency to improve VLCD2 and VLCD3 drive capability. The control register is described as follows. 6.9.1 R9/LCDCR (LCD Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BS DS1 DS0 LCDEN − LCDTYPE LCDF1 LCDF0 Bit 7 (BS): LCD bias select bit, 0/1=> (1/2 bias) / (1/3 bias) Bits 6 ~ 5 (DS1 ~ DS0): LCD duty select DS1 DS0 LCD Duty 0 0 1/2 duty 0 1 1/3 duty 1 × 1/4 duty Bit 4 (LCDEN): LCD enable bit “0”: disable the LCD circuit “1”: enable the LCD circuit Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 35 EM78P468N/L 8-Bit Microcontroller When the LCD function is disabled, all common/segment output is set to ground (GND) level Bit 3: Not used Bit 2 (LCDTYPE): LCD drive waveform type select bit LCDTYPE = “0”: “A” type waveform LCDTYPE = “1”: “B” type waveform Bits 1 ~ 0 (LCDF1 ~ LCDF0): LCD frame frequency control bits LCDF1 LCDF0 0 LCD Frame Frequency (e.g. Fs=32.768kHz) 1/2 Duty 1/3 Duty 1/4 Duty 0 Fs/(256×2)=64.0 Fs/(172×3)=63.5 Fs/(128×4)=64.0 0 1 Fs/(280×2)=58.5 Fs/(188×3)=58.0 Fs/(140×4)=58.5 1 0 Fs/(304×2)=53.9 Fs/(204×3)=53.5 Fs/(152×4)=53.9 1 1 Fs/(232×2)=70.6 Fs/(156×3)=70.0 Fs/(116×4)=70.6 Note: Fs: sub-oscillator frequency 6.9.2 RA/LCD_ADDR (LCD Address) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0 Bits 7 ~ 5: Not used, fixed to “0” Bits 4 ~ 0 (LCDA4 ~ LCDA0): LCD RAM address RA (LCD Address) Bits 7 ~4 RB (LCD Data Buffer) Bit 3 Bit 2 Bit 1 Bit 0 (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0) Segment 00H − − − − − SEG0 01H − − − − − SEG1 02H − − − − − SEG2 | | | 1DH − − − − − SEG29 1EH − − − − − SEG30 1FH − − − − − SEG31 Common X COM3 COM2 COM1 COM0 6.9.3 RB/LCD_DB (LCD Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0 Bits 7 ~ 4: Not used Bit 3 ~ 0 (LCD_D3 ~ LCD_D0): LCD RAM data transfer registers 36 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.9.4 RD/SBPCR (System, Booster and PLL Control Registers) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − CLK2 CLK1 CLK0 IDLE BF1 BF0 CPUS Bit 2 ~ 1 (BF1 ~ 0): LCD booster frequency select bits BF1 BF0 Booster Frequency 0 0 Fs 0 1 Fs/4 1 0 Fs/8 1 1 Fs/16 The initial setting flowchart for LCD function IC RESET occur *Set Port 7 snd Port 8 for general I/O or LCD segment (IOC50) *it must be set to output port w hen the pin of port 7 and the pin of port 8 for LCD segemnt (IOC70 and IOC80) Set LCD Type, duty, bias, LCD frame frequency (R9) Set LCD Booster Frequency (RD) Clear all LCD RAM (RA and RB) Enable LCD function (R9) Use LCD address and LCD data buffer to implment user's applications. (RA and RB) END Fig.6-14 The Initial Setting Flowchart for LCD Function Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 37 EM78P468N/L 8-Bit Microcontroller Boosting circuits connection for LCD voltage VDD VLCD2(2*VDD/3) VA VB VLCD3(1*VDD/3) GND External circuit for 1/3 Bias VDD VLCD2(VDD/2) VA VB VLCD3(VDD/2) GND External circuit for 1/2 Bias Fig. 6-15 Charge Bump Circuit Connection (Cext=0.1μf ) 38 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 1 frame 1 frame VDD COM 0 VLCD2,3 VDD COM 0 VLCD2,3 GND GND VDD COM 1 VLCD2,3 VDD COM 1 VLCD2,3 GND GND VDD SEG N VLCD2,3 VDD SEG N VLCD2,3 GND GND VDD VDD VLCD2,3 GND SEG N - COM0 ON -VLCD2,3 VLCD2,3 SEG N - COM0 GND ON -VLCD2,3 -VDD -VDD VDD VDD VLCD2,3 SEG N - COM1 VLCD2,3 SEG N - COM1 GND OFF GND OFF -VLCD2,3 1/2 bias, 1/2 duty A type -VLCD2,3 -VDD 1/2 bias, 1/2 duty B type -VDD Fig. 6-16 LCD Waveform for 1/2 Bias, 1/2 Duty 1frame 1frame VDD VDD COM 0 VLCD2,3 VLCD2,3 COM 0 GND GND VDD VDD COM 1 VLCD2,3 COM 1 VLCD2,3 GND GND VDD VDD COM 2 VLCD2,3 COM 2 VLCD2,3 GND GND VDD VDD VLCD2,3 SEG N SEG N VLCD2,3 GND GND VDD VDD VLCD2,3 VLCD2,3 GND SEG N - COM0 ON -VLCD2,3 SEG N - COM0 GND ON -VLCD2,3 -VDD -VDD VDD VDD VLCD2,3 VLCD2,3 GND SEG N - COM1 OFF -VLCD2,3 1/2 bias, 1/3 duty A type -VDD SEG N - COM1 GND OFF -VLCD2,3 1/2 bias, 1/3 duty B type -VDD Fig. 6-17 LCD Waveform for 1/2 Bias, 1/3 Duty Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 39 EM78P468N/L 8-Bit Microcontroller 1 frame 1 frame VDD VDD VLCD2 VLCD2 COM 0 COM 0 VLCD3 VLCD3 GND GND VDD VDD VLCD2 VLCD2 COM 1 COM 1 VLCD3 VLCD3 GND GND VDD VDD VLCD2 COM 2 COM 2 VLCD2 VLCD3 VLCD3 GND GND VDD VDD VLCD2 VLCD2 SEG N SEG N VLCD3 VLCD3 GND GND VDD VDD SEG N - COM0 VLCD3 SEG N - COM0 VLCD3 GND GND ON ON -VLCD3 -VLCD3 -VDD -VDD VDD VDD VLCD3 SEG N - COM1 VLCD3 SEG N - COM1 GND GND OFF OFF -VLCD3 -VLCD3 1/3 bias, 1/3 duty A type -VDD 1/3 bias, 1/3 duty B type -VDD Fig. 6-18 LCD Waveform for 1/3 Bias, 1/3 Duty 1 frame 1 frame VDD VDD VLCD2 COM 0 VLCD2 COM 0 VLCD3 VLCD3 GND GND VDD VDD VLCD2 COM 1 VLCD2 COM 1 VLCD3 VLCD3 GND GND VDD COM 2 VLCD2 VDD COM 2 VLCD2 VLCD3 VLCD3 GND GND VDD VDD VLCD2 VLCD2 SEG N SEG N VLCD3 VLCD3 GND GND VDD SEG N COM0 VLCD3 VDD SEG N COM0 VLCD3 GND ON GND ON -VLCD3 -VLCD3 -VDD -VDD VDD SEG N COM1 VLCD3 VDD SEG N COM1 VLCD3 GND OFF GND OFF -VLCD3 1/3 bias, 1/4 duty A type -VDD -VLCD3 1/3 bias, 1/4 duty B type -VDD Fig. 6-19 LCD Waveform for 1/3 Bias, 1/4 Duty 40 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.10 Infrared Remote Control Application/PWM Waveform Generation This LSI can output infrared carrier in user-friendly or in PWM standard waveform. The IR and PWM waveform generated functions include an 8-bit down count timer/counter, high-pulse width timer, low-pulse width timer, and IR control register. The IR system block diagram is shown in Fig. 6-20. The IROUT pin waveform is determined by IR control register (RE), IOC90 (Counters 1 and 2 control register), IOCA0 (high-pulse width timer, low-pulse width timer control register), IOCC0 (Counter 2 preset), IOCD0 (high-pulse width timer preset register), and IOCE0 (low-pulse width timer preset register). Details on Fcarrier, high-pulse time, and low pulse time are explained as follows: If Counter 2 clock source is FT (this clock source can be set by IOC91), then F carrier = FT 2 × (1 + decimal of C ounter 2 preset value ( IOCC 0 )) × prescaler If the high-pulse width timer clock source is FT (this clock source can be set by IOCA1), then T high pulse time = prescaler × (1 + decimal of high pulse width timer value ( IOCD 0 )) FT If the low-pulse width timer clock source is FT (this clock source can be set by IOCA1); Tlow pulse time = prescaler × (1 + decimal of low pulse width timer value ( IOCE 0 )) FT Pre-s caler (IOCA 1) Fs High-Pulse Width Timer (IOCD0) Fm Low -Puls e Width Timer ( IOCE0) 8 A uto-reload buf f er Pre-s caler (IOC A 1) 8 A uto-reload buf f er 8 Pre-s caler (IOC91) 8 bit dow n counter 8 8 bit dow n c ounter 8 Fcarrier H/W Modulator Circuit 8 bit dow n c ounter IROUTpin 8 A uto-reload buf f er 8 HF LGP IRE 8 Counter 2 (IOCC0) Fm: main oscillator frequency RE register Fs: sub-oscillator frequency Fig. 6-20 IR/PWM System Block Diagram Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 41 EM78P468N/L 8-Bit Microcontroller The IROUT output waveform is further explained in the following figures: Fig. 6-21 LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in low-pulse width time. Fig. 6-22 LGP=0, HF=0, the IROUT waveform cannot modulate Fcarrier waveform when in low-pulse width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This mode can produce standard PWM waveform. Fig. 6-23 LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in low-pulse width time. When IRE goes from high to low, the output waveform of IROUT will keep on transmitting until high-pulse width timer interrupt occurs. Fig. 6-24 LGP=0, HF=0, the IROUT waveform can not modulate Fcarrier waveform when in low-pulse width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This mode can produce standard PWM waveform. When IRE goes from high to low, the output waveform of IROUT will keep on transmitting till high-pulse width timer interrupt occurs. Fig.6-25 LGP=1, when this bit is set to high level, the high-pulse width timer is ignored. So IROUT waveform output from low-pulse width timer is established. Fcarrier low-pulse width high-pulse width high-pulse width low-pulse width HF start IRE IROUT Fig. 6-21 LGP=0, IROUT Pin Output Waveform Fcarrier low-pulse width high-pulse width high-pulse width low-pulse width HF start IRE IROUT Fig. 6-22 LGP=0, IROUT Pin Output Waveform 42 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Fcarrier low-pulse width high-pulse width low-pulse width high-pulse width HF start IRE IR disable IROUT Always high-level Fig. 6-23 LGP=0, IROUT Pin Output Waveform Fcarrier low-pulse width high-pulse width low-pulse width high-pulse width HF start IRE IR disable IROUT Always high-level Fig. 6-24 LGP=0, IROUT Pin Output Waveform Fcarrier low-pulse width Low-pulse width low-pulse width high-pulse width HF start IRE IR disable IROUT Always high-level Fig. 6-25 LGP=1, IROUT Pin Output Waveform Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 43 EM78P468N/L 8-Bit Microcontroller IR/PWM Function Enable Flowchart Start Start SET P5.7 to Output state (IOC 50) SET P5.7 for IR/PWM Function Output Pin (RE) SET P5.7 to Output state (IOC 50) SET P5.7 for IR/PWM Function Output Pin (RE) SET Counter 2 clock source and prescaler (IOC91) SET High pulse width timer, Low pulse width timer clock source and prescaler (IOCA1) SET Counter 2 (IOC0), High pulse width timer (IOD0) , Low pulse width timer (IOCE0) preset value SET High pulse width timer, Low pulse width timer clock source and prescaler (IOCA1) High pulse width timer (IOD0), Low pulse width timer (IOCE0) preset value Enable IR (RE) HF="0", and IRE="1" Enable IR (RE) HF="1", and IRE="1" Enable HPWT and LPWT Interrupt Set IOCF0 and ENI instruction Enable Counter 2, High pulse width timer and Low pulse width timer (RC) END (a) IR application Enable HPWT and LPWT Interrupt Set IOCF0 and ENI instruction Enable high pulse width timer and Low pulse width Timer (RC) END (b) PWM application Fig. 6-26 IR/PWM Function Enable Flowchart 44 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.11 Code Options The EM78P468N/L has one Code Option word that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: Word 1 of code options is for customer ID code application. Word 1 Bit 12~Bit 0 Word 0 of Code Options is for IC function setting. The following are the settings for OTP IC programming: Word 0 Bits12~10 1 Bit 9 Bit 8 Bit 7 CYES HLFS ENWDTB Bit 6 FSMD Bit 5 Bit 4 FMMD1 FMMD0 Bit 3 Bit 2 Bit 1 Bit 0 HLP PR2 PR1 PR0 Bits 12 ~ 10: Not used. These bits are set to “1” all the time. Bit 9 (CYES): Cycle select for JMP and CALL instructions CYES = “0”: only one instruction cycle (JMP or CALL) can be executed CYES = “1”: two instructions cycles (JMP and CALL) can be executed Bit 8 (HLFS): main or sub-oscillator select HLFS = “0”: CPU is set to select sub-oscillator when reset occurs. HLFS = “1”: CPU is set to select main-oscillator when reset occurs. Bit 7 (ENWDTB): Watchdog timer enable/disable bit. ENWDTB = “0”: Enable watchdog timer. ENWDTB = “1”: Disable watchdog timer. Bit 6 (FSMD): sub-oscillator type selection. Bits 5, 4 (FMMD1, 0): Main Oscillator Type Selection FSMD FMMD1 FMMD0 0 0 0 RC type RC type 0 0 1 Crystal type RC type 0 1 × PLL type RC type 1 0 0 RC type Crystal type 1 0 1 Crystal type Crystal type 1 × PLL type Crystal type 1 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) Main Oscillator Type Sub Oscillator Type • 45 EM78P468N/L 8-Bit Microcontroller Bit 3 (HLP): Power consumption selection. If the system usually runs in green mode, it must be set to low power consumption to help support the energy saving issue. It is recommended that low power consumption mode is selected. HLP = “0”: Low power consumption mode HLP = “1”: High power consumption mode Bits 2~0 (PR2~PR0): Protect Bit PR2~PR0 are protection bits. Each protect status is as follows: PR2 PR1 PR0 Protect 0 0 0 Enable 1 1 1 Disable 6.12 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", & "RETI" instructions, or the conditional skip instructions ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be true. Also execute within two instruction cycles the instructions that are written to the program counter. Additionally, the instruction set offers the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. 46 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Convention: R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation. k = 8 or 10-bit constant or literal value Binary Instruction Hex Mnemonic 0 0 0000 0000 0000 0000 0000 0001 0000 0001 NOP DAA 0 0000 0000 0011 0003 SLEP 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0100 rrrr 0000 0001 0010 0004 000r 0010 0011 0012 WDTC IOW ENI DISI RET 0 0000 0001 0011 0013 RETI rrrr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr IOR MOV CLRA CLR SUB SUB DECA DEC OR OR AND AND XOR XOR ADD ADD MOV MOV COMA COM INCA INC DJZA DJZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) Operation R R R, A R A, R, R R A, R, A, R, A, R, A, R, A, R, R R R R R R R A R A R A R A R A R R No Operation Decimal Adjust A 0 → WDT, Stop oscillator 0 → WDT A → IOCR Enable Interrupt Disable Interrupt [Top of Stack] → PC [Top of Stack] → PC, Enable Interrupt IOCR → A A→R 0→A 0→R R-A → A R-A → R R-1 → A R-1 → R A∨R→A A∨R→R A&R→A A&R→R A⊕R→A A⊕R→R A+R→A A+R→R R→A R→R /R → A /R → R R+1 → A R+1 → R R-1 → A, skip if zero R-1 → R, skip if zero Status Affected None C T, P T, P None1 None None None None None1 None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None • 47 EM78P468N/L 8-Bit Microcontroller Binary Instruction Hex Mnemonic Operation 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr 06rr RLC R 0 0111 00rr rrrr 07rr SWAPA R 0 0 0 0 0 0 0 0111 0111 0111 100b 101b 110b 111b 01rr 10rr 11rr bbrr bbrr bbrr bbrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx SWAP JZA JZ BC BS JBC JBS R R R R, R, R, R, 1 00kk kkkk kkkk 1kkk CALL k 1 1 1 1 1 01kk 1000 1001 1010 1011 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1kkk 18kk 19kk 1Akk 1Bkk JMP MOV OR AND XOR k A, A, A, A, 1 1100 kkkk kkkk 1Ckk RETL k 1 1 1 1 1101 1111 1110 1110 kkkk kkkk 1000 1001 1Dkk 1Fkk 1E8k 1E9k SUB ADD PAGE BANK A, k A, k k k kkkk kkkk kkkk kkkk b b b b k k k k Status Affected R(n) → A(n-1), C R(0) → C, C → A(7) R(n) → R(n-1), C R(0) → C, C → R(7) R(n) → A(n+1), C R(7) → C, C → A(0) R(n) → R(n+1), C R(7) → (C), C → (R(0) R(0-3) → ( A(4-7), None R(4-7) → ( A(0-3) R(0-3) → ( R(4-7) None R+1 → A, skip if zero None R+1 → R, skip if zero None 0→ ( R(b) None 1→ ( R(b) None if R(b)=0, skip None if R(b)=1, skip None PC+1 → [SP], None (Page, k) → (PC) (Page, k) → (PC) None k→A None Avk→A Z A&k→A Z A⊕k→A Z k → A, [Top of Stack] → None PC k-A → A Z, C, DC k+A → A Z, C, DC K->R3(5:6) None K->R4(7:6) None 1 Note: This instruction is applicable to IOC50~IOF0, IOC61~IOCE1. 48 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 6.13 Timing Diagram AC Test Input/Output Waveform 2.4 2.0 0.8 TEST POINTS 2.0 0.8 0.4 AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Tim ing m easurem ents are m ade at 2.0V for logic "1",and 0.8V for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc Ttrf 90% Port (n+1) 10% Ttrr 90% 10% Tiod Port (n) *n = 0 , 2 , 4 , 6 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 49 EM78P468N/L 8-Bit Microcontroller 7 Absolute Maximum Ratings Items Symbol Condition VDD Input voltage Output voltage Unit Min. Max. − GND-0.3 +7.0 V VI Port 5 ~ Port 8 GND-0.3 VDD+0.3 V VO Port 5 ~ Port 8 GND-0.3 VDD+0.3 V Operation temperature TOPR − -40 85 °C Storage temperature TSTG − -65 150 °C Power consumption PD − − 500 mW Operating Frequency − − 32.768K 10M Hz Supply voltage 8 Rating Electrical Characteristic 8.1 DC Electrical Characteristics Ta= -40°C ~85 °C, VDD= 5.0V, GND= 0V Symbol FXT Condition Min. Typ. Max. Unit Crystal: VDD to 5V Two cycles with two clocks 32.768 8M 10M kHz Sub-oscillator Two cycles with two clocks − 32.768 − kHz External R, Internal C for Sub-oscillator R: 300KΩ, internal capacitance 270 384 500 kHz External R, Internal C for Sub-oscillator R: 2.2MΩ, internal capacitance 22.9 32.768 42.6 kHz Input Leakage Current for Input pins VIN = VDD, GND -1 0 1 μA VIH1 Input High Threshold Voltage (Schmitt Trigger) Ports 5, 6, 7, 8 2.0 − − V VIL1 Input High Threshold Voltage (Schmitt Trigger) Ports 5, 6, 7, 8 − − 0.8 V VIHT1 Input High Threshold Voltage (Schmitt Trigger) /RESET 2.0 − − V VILT1 Input Low Threshold Voltage /RESET (Schmitt Trigger) − − 0.8 V VIHT2 Input High Threshold Voltage (Schmitt Trigger) 2.0 − − V VILT2 Input Low Threshold Voltage TCC, INT0, INT1 (Schmitt Trigger) − − 0.8 V IOH1 Output High Voltage (Ports 5~8) VOH = 2.4V, IROCS=”0” -10 − − mA IOL1 Output Low Voltage (Ports 5~8) VOL = 0.4V, IROCS=”0” − − 10 mA IOH1 Output high voltage (P5.7/IROUT pin) VOH = 2.4V, IROCS=”1” -20 − − mA IOL2 Output Low Voltage (P5.7/IR OUT pin) VOL = 0.4V, IROCS=”1” − − 20 mA Fs ERIC IIL 50 • Parameter TCC, INT0, INT1 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Symbol Parameter Condition Min. Typ. Max. Unit IPH Pull-high current Pull-high active, input pin at GND -55 -75 -95 μA IPL Pull-low current Pull-low active, input pin at VDD 55 75 95 μA Sleep mode current All input and I/O pins at VDD, Output pin floating, WDT disabled − 0.5 1.5 μA Idle mode current /RESET= 'High', CPU OFF, Sub-oscillator clock (32.768kHz) ON, output pin floating, LCD enabled, no load − 14 18 μA ICC2 Green mode current /RESET= 'High', CPU ON, Sub-oscillator clock (32.768kHz), Output pin floating, WDT enabled, LCD enabled − 22 30 μA ICC3 Normal mode /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), Output pin floating − 2.2 3 mA ICC4 Normal mode /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), Output pin floating − 3.1 4 mA Min. Typ. ISB ICC1 Ta= -40°C ~85 °C, VDD= 3.0V, GND= 0V Symbol FXT Parameter Condition Max. Unit Crystal: VDD to 5V Two cycles with two clocks 32.768 8M 10M kHz Sub-oscillator Two cycles with two clocks − 32.768 − kHz External R, Internal C for Sub-oscillator R: 300KΩ, internal capacitance 270 384 500 kHz External R, Internal C for Sub-oscillator R: 2.2MΩ, internal capacitance 22.9 32.768 42.6 kHz Input Leakage Current for Input pins VIN = VDD, GND -1 0 1 μA VIH1 Input High Threshold Voltage (Schmitt Trigger) Ports 5, 6, 7, 8 1.8 − − V VIL1 Input High Threshold Voltage (Schmitt Trigger) Ports 5, 6, 7, 8 − − 0.6 V VIHT1 Input High Threshold Voltage (Schmitt Trigger) /RESET 1.8 − − V VILT1 Input Low Threshold Voltage (Schmitt Trigger) /RESET − − 0.6 V VIHT2 Input High Threshold Voltage (Schmitt Trigger) TCC, INT0, INT1 1.8 − − V VILT2 Input Low Threshold Voltage (Schmitt Trigger) TCC, INT0, INT1 − − 0.6 V IOH1 Output High Voltage (Ports 5~8) VOH = 2.4V, IROCS=”0” -1.8 − − mA IOL1 Output Low Voltage (Ports 5~8) VOL = 0.4V, IROCS=”0” − − 6 mA Fs ERIC IIL Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 51 EM78P468N/L 8-Bit Microcontroller Symbol Parameter Condition Min. Typ. Max. Unit IOH1 Output high voltage (P5.7/IROUT pin) VOH = 2.4V, IROCS=”1” -3.5 − − mA IOL2 Output Low Voltage (P5.7/IR OUT pin) VOL = 0.4V, IROCS=”1” − − 12 mA IPH Pull-high current Pull-high active, input pin at GND -16 -23 -30 μA IPL Pull-low current Pull-low active, input pin at VDD 16 23 30 μA ISB Sleep mode current All input and I/O pins at VDD, Output pin floating, WDT disabled − 0.1 1 μA Idle mode current /RESET= 'High', CPU OFF, Sub-oscillator clock (32.768kHz) ON, output pin floating, LCD enabled, no load − 4 8 μA ICC2 Green mode current /RESET= 'High', CPU ON, Sub-oscillator clock (32.768kHz), Output pin floating, WDT enabled, LCD enabled − 10 20 μA ICC3 Normal mode /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), Output pin floating − 0.73 1.2 mA ICC1 8.2 AC Electrical Characteristics Ta=- 40°C ~ 85 °C, VDD=5V±5%, GND=0V Symbol Parameter Conditions Min Typ Max Unit Dclk Input CLK duty cycle − 45 50 55 % Tins Instruction cycle time (CLKS="0") Crystal type 100 − DC ns RC type 500 − DC ns Ttcc TCC input period − (Tins+20)/N* − − ns Tdrh Device reset hold time Ta = 25°C 11.3 16.2 21.6 ms Trst /RESET pulse width Ta = 25°C 2000 − − ns Twdt Watchdog timer period Ta = 25°C 11.3 16.2 21.6 ms Tset Input pin setup time − − 0 − ns Thold Input pin hold time − − 20 − ns Tdelay Output pin delay time Cload=20pF − 50 − ns * N= selected prescaler ratio 52 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 8.3 Device Characteristic The graphs provided in the following pages were derived based on a limited number of samples and are shown here for reference only. The device characteristics illustrated herein are not guaranteed for its accuracy. In some graphs, the data may be out of the specified warranted operating range. Vih/Vil (/RESET pins with schmitt inverter) 2.5 Vih Max. (-40℃ to +85℃) Vih Typ. (+25℃) Vih/Vil (Volt) 2 Vih Min. (-40℃ to +85℃) 1.5 1 Vil Max. (-40℃ to +85℃) Vil Typ. (+25℃) 0.5 Vil Min. (-40℃ to +85℃) 0 2 2.5 3 3.5 4 4.5 5 5.5 Vdd (Volt) Fig. 8-1 Vih, Vil of /RESET Pin vs. VDD Vih/Vil (Port 5, Port 6 All Input pins with schmitt trigger) 2.5 Vih Max. (-40℃ to +85℃) Vih Vil (Volt) 2 Vih Typ. (+25℃) Vih Min. (-40℃ to +85℃) 1.5 1 Vil Max. (-40℃ to +85℃) 0.5 Vil Typ. (+25℃) Vil Min. (-40℃ to +85℃) 0 2 2.5 3 3.5 4 4.5 5 5.5 Vdd (Volt) Fig. 8-2 Vih, Vil of Port 5 and Port 6 vs. VDD Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 53 EM78P468N/L 8-Bit Microcontroller Vih/Vil (Port 7, Port 8 All Input pins with schmitt inverter) 2.5 Vih Max. (-40℃ to +85℃) Vih Typ. (+25℃) 2 Vih Vil (Volt) Vih Min. (-40℃ to +85℃) 1.5 1 Vil Max. (-40℃ to +85℃) Vil Typ. (+25℃) 0.5 Vil Min. (-40℃ to +85℃) 0 2 2.5 3 3.5 4 4.5 5 5.5 Vdd (Volt) Fig. 8-3 Vih, Vil of Port 7 and Port 8 vs. VDD P5.7 Voh/Ioh (VDD=3V, IROCS="0") P5.7 Voh/Ioh (VDD=5V, IROCS="0") 0 0 -5 -2 -10 Min : +85℃ Ioh (mA) Ioh (mA) Min : +85℃ Typ : +25℃ -15 -4 Typ : +25℃ -6 Max : -40℃ Max : -40℃ -8 -20 -10 -25 0 1 2 3 Voh (Volt) 4 5 0 0.5 1 1.5 2 2.5 3 Voh (Volt) Fig. 8-4 Port 5.7 Voh vs. Ioh, [ VDD=3V, 5V, IROCS (Bit 7 of IOC61) =” 0 ” ] 54 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller P5.7 Voh/Ioh (VDD=5V, IROCS="1") P5.7 Voh/Ioh (VDD=3V, IROCS="1") 0 0 -2 -10 -4 -20 -30 Min : +85℃ Min : +85℃ Ioh (mA) Ioh (mA) -6 Typ : +25℃ -8 Typ : +25℃ -10 -12 -40 Max : -40℃ -14 Max : -40℃ -16 -18 -50 0 1 2 3 4 0 5 0.5 1 1.5 2 2.5 3 Voh (Volt) Voh (Volt) P5.4~6, PORT 6~8 Voh/Ioh (VDD=5V) P5.4~6, PORT 6~8 Voh/Ioh (VDD=3V) 0 0 -5 -2 -10 Min : +85 ℃ -15 -20 Ioh (mA) Ioh (mA) Fig. 8-5 Port 5.7 Voh vs. Ioh, [ VDD=3V, 5V, IROCS (Bit 7 of IOC61) =” 1 ” ] Typ : +25℃ -4 Min : +85℃ Typ : +25℃ -6 Max : -40℃ Max : -40℃ -8 -10 -25 0 1 2 3 4 5 Voh (Volt) 0 0.5 1 1.5 2 2.5 3 Voh (Volt) Fig. 8-6 Port 6, Port 7 and Port 8 Voh vs. Ioh [ VDD=3V, 5V ] Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 55 EM78P468N/L 8-Bit Microcontroller 80 P5.7 Voh/Ioh (VDD=5V, IROCS="0") P5.7 Voh/Ioh (VDD=3V, IROCS="0") 35 Max : -40℃ Max : -40℃ 70 30 60 Typ : +25℃ Typ : +25℃ 25 40 Ioh (mA) Ioh (mA) 50 Min : +85℃ 20 15 Min : +85℃ 30 10 20 5 10 0 0 0 1 2 3 4 0 5 0.5 1 1.5 2 2.5 3 Voh (Volt) Voh (Volt) Fig. 8-7 Port 5.7 Vol vs. Iol, [ VDD=3V, 5V, IROCS (Bit 7 of IOC61) =” 0 ” ] P5.7 Voh/Ioh (VDD=3V, IROCS="1") P5.7 Voh/Ioh (VDD=5V, IROCS="1") 70 160 Max : -40℃ Max : -40℃ 140 60 Typ : +25℃ 120 50 Typ : +25℃ 80 Ioh (mA) Ioh (mA) 100 Min : +85℃ 40 30 Min : +85℃ 60 20 40 10 20 0 0 0 1 2 3 Voh (Volt) 4 5 0 0.5 1 1.5 2 2.5 3 Voh (Volt) Fig. 8-8 Port 5.7 Vol vs. Iol, [ VDD=3V, 5V, IROCS (Bit 7 of IOC61) =” 1 ” ] 56 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller P5.4~5.6, PORT 6, 7, 8 Voh/Ioh (VDD=5V) P5.4~5.6, PORT 6, 7, 8 Voh/Ioh (VDD=3V) 90 40 Max : -40℃ 80 70 30 Typ : +25℃ 60 Max : -40℃ 35 Typ : +25℃ Ioh (mA) Ioh (mA) 25 50 40 Min : +85℃ 20 15 Min : +85℃ 30 10 20 5 10 0 0 0 1 2 3 4 5 0 0.5 Voh (Volt) 1 1.5 2 2.5 3 Voh (Volt) Fig. 8-9 Port 6, Port 7 and Port 8 Vol vs. Iol [ VDD=3V, 5V ] Setup time from Power ON Reset 35 30 setup time (mS) 25 20 15 10 5 0 2 3 4 5 6 VDD (Volt) Fig. 8-10 WDT Time-out Period vs. VDD, with prescaler set to 1:1 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 57 EM78P468N/L 8-Bit Microcontroller Typical RC OSC Frequency (R-OSCI Pin) 2.4 35 2.1 Typical RC OSC Frequency (Xin Pin) R = 51 K 34 Frequency (K Hz) Frequency (M Hz) 1.8 1.5 1.2 R = 100 K 0.9 33 R = 2.2 M 32 0.6 31 0.3 R = 300 K 0 30 2 2.5 3 3.5 4 VDD (Volt) 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD (Volt) Fig. 8-11 Typical ERIC OSC Frequency vs. VDD (Temperature at 25°C) Fig. 8-12 Typical ERIC OSC Frequency vs. Temperature (R-OSCI Pin) 58 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Fig. 8-13 Typical ERIC OSC Frequency vs. Temperature (Xin Pin) There are four conditions or modes for the Operating Current ICC1 to ICC4. These conditions are as follows: ISB (Sleep Mode): Fm and Fs is stop, all function are off. ICC1 (Idle Mode): Fm Stop and Fs=32kHz, two clocks, CPU off, LCD enable and WDT Enable. ICC2 (Green Mode): Fm Stop and Fs=32kHz, two clocks, CPU running on Fs frequency, LCD enable and WDT Enable ICC3 (Normal Mode): Fm=4M Hz and Fs=32kHz, two clocks, CPU running on Fm frequency, LCD enable and WDT Enable Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 59 EM78P468N/L 8-Bit Microcontroller Typical ICC3 vs. Temerature 2 1.6 Current (mA) VDD=5V 1.2 0.8 VDD=3V 0.4 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-14 Typical Power Consumption on Normal Mode Operation (Fm=4MHz) Maximum ICC3 vs. Temerature 2.8 2.4 VDD=5V Current (mA) 2 1.6 1.2 0.8 VDD=3V 0.4 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-15 Maximum Power Consumption on Normal Mode Operation (Fm=4MHz) 60 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Typical ICC2 vs. Temerature 30 25 Current (uA) VDD=5V 20 15 10 VDD=3V 5 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-16 Typical Power Consumption on Green Mode Operation Maximum ICC2 vs. Temerature 35 30 Current (uA) 25 VDD=5V 20 15 10 VDD=3V 5 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-17 Maximum Power Consumption on Green Mode Operation Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 61 EM78P468N/L 8-Bit Microcontroller Typical ICC1 vs. Temerature 20 Current (uA) 15 VDD=5V 10 5 VDD=3V 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-18 Typical Power Consumption on Idle Mode Operation Maximum ICC1 vs. Temerature 25 Current (uA) 20 VDD=5V 15 10 VDD=3V 5 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-19 Maximum Power Consumption on Idle Mode Operation 62 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller Typical ISB vs. Temerature 1 Current (uA) 0.8 VDD=5V 0.6 0.4 0.2 VDD=3V 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-20 Typical Power Consumption on Sleep Mode Operation Maximun ISB vs. Temerature 1.2 Current (uA) 0.9 VDD=5V 0.6 0.3 VDD=3V 0 -40 -20 0 25 50 70 85 Temperature (℃ ) Fig. 8-21 Maximum Power Consumption on Sleep Mode Operation Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 63 EM78P468N/L 8-Bit Microcontroller Fig. 8-22 Operating Voltage under Temperature Range of 0°C to 70°C Fig. 8-23 Operating Voltage under Temperature Range of -40°C to +85°C 64 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller 9 Application Circuit EM78P468N COM0 | COM3 LCD PANEL VDD SEG0 | SEG31 IROUT P6.7 P6.6 P6.5 P6.4 P6.3 1 2 3 4 P6.2 5 6 7 8 P6.1 9 A B C P6.0 D E F G Fig. 9-1 IROUT Control External BJT Circuit to Drive Infrared Emitting Diodes EM78P468N COM0 | COM3 LCD PANEL VDD SEG0 | SEG31 IROUT P6.7 P6.6 P6.5 P6.4 P6.3 1 2 3 4 P6.2 5 6 7 8 P6.1 9 A B C P6.0 D E F G Fig. 9-2 IROUT Direct Drive Infrared Emitting Diodes Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 65 EM78P468N/L 8-Bit Microcontroller APPENDIX A Package Type Name Package Type Pin Count Package Size EM78P468LH Dice 59 − EM78P468NQ QFP 64 14 mm × 20 mm EM78P468NQS/NQJ QFP 64 14 mm × 20 mm EM78P468NAQ LQFP 64 7 mm × 7 mm EM78P468NAQS/NAQJ LQFP 64 7 mm × 7 mm EM78P468NBQ LQFP 44 10 mm × 10 mm EM78P468NBQS/NBQJ LQFP 44 10 mm × 10 mm EM78P468NCQ QFP 44 10 mm × 10 mm EM78P468NCQS/NCQJ QFP 44 10 mm × 10 mm EM78P468NEQ QFP 64 14 mm × 14 mm EM78P468NEQS/NEQJ QFP 64 14 mm × 14 mm Note: Green products do not contain hazardous substances. These are compatible with the third edition of Sony SS-00259 standard. The Pb content should be less than 100ppm, and should meet Sony specifications or requirements. Part No. Electroplate type Pure Tin Ingredient (%) Sn:100% Melting point (°C) 66 • EM78P468NxS/xJ 232°C Electrical resistivity (μΩ-cm) 11.4 Hardness (hv) 8~10 Elongation (%) >50% Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller B Package Information QFP – 64 A1 Symbal A A1 A2 D D1 E E1 θ c L L1 b e Min Normal Max 3.40 一 一 一 2.72 3.05 25.00 BASIC 20.00 BASIC 19.00 BASIC 14.00 BASIC 0° 7° 3. 5 0.11 0.15 0.23 1.15 1.3 1.45 2.50 REF 0.35 0.50 0. 4 1.00 BSC 一 0.25 2.55 TITLE: QFP-64 L(14*20 MM) FOOTPRINT 5.0mm PACKAGE OUTLINE DIMENSION File : QFP 64L Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 67 EM78P468N/L 8-Bit Microcontroller QFP – 64 68 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller LQFP – 64 DETAIL " A " D D1 E L E1 L1 64 1 e Symbal A A1 A2 D D1 E E1 e c c1 b b1 L L1 Min 0.05 1.35 8.90 6.90 8.90 6.900 θ 0° Normal 1.40 9.00 7.00 9.00 7.00 0.4 BSC 0.18 0.16 0.60 1.00 REF. 3.5° 0.09 0.09 0.13 0.13 0.45 Max 1.60 0.15 1.45 9.10 7.10 9.10 7.100 0.20 0.16 0.23 0.19 0.75 7° A2 A b TITLE: LQFP 64L ( 7*7 MM ) FOOTPRINT 2.0 mm PACKAGE OUTLINE DIMENSION A1 File : DETAIL " B " c1 c LQFP 64L Edtion: A Unit : mm Scale: Free b b1 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) Material: Sheet:1 of 1 • 69 EM78P468N/L 8-Bit Microcontroller LQFP – 44 c Symbal A A1 A2 b c E1 E L L1 e Min Normal 0.050 1.350 0.300 0.090 1.400 0.370 0 3.5 Max 1.600 0.150 1.450 0.450 0.200 12.00 BASIC 10.00 BASIC 0.450 0.600 0.750 1.0(BASIC) 0.8(BASIC) θ 7 TITLE: LQFP-44L(10*10 MM) FOOTPRINT 2.0mm PACKAGE OUTLINE DIMENSION File : LQFP44 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 70 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller QFP – 44 c Symbal A A1 A2 b c E1 E L L1 e Min 0.15 1.80 13.00 9.90 0.73 1.50 θ Normal 2.00 0.30(TYP) 0.15(TYP) 13.20 10.00 0.88 1.60 0.80(TYP) Max 2.70 0.50 2.20 13.40 10.10 1.03 1.70 0 7 TITLE: QFP-44L(10*10 MM) FOOTPRINT 3.2mm PACKAGE OUTLINE DIMENSION File : QFP44 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 71 EM78P468N/L 8-Bit Microcontroller C EM78P468N/L Program Pin List DWRT is used to program the EM78P468N/L IC’s. The connector of DWTR are select by CON4 (EM78P451), and the software is selected by EM78P468N/L. L/QFP-64 L/QFP-44 Pin Number Pin Number /RESET 25 14 ACLK P54/INT0 32 21 DINCLK P55/INT1 33 22 DATAIN P56/TCC 34 23 /PGMB P60 38 25 /OEB P61 39 26 VDD VDD 29 18 GND GND 26 15 Program Pin Name IC Pin Name VPP Wiring diagram is for ELAN DWTR 72 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) EM78P468N/L 8-Bit Microcontroller D ICE 468XA D.1 ICE 468XA Oscillator Circuit (JP 5) Mode 1: Main oscillator: Crystal mode, Sub oscillator: Crystal mode Crystal GND Xin Xout GND VDD Xin Suboscillator GND R-OSCI OSCO GND VDD R-OSCI Mainoscillator JP 5 Crystal Mode 2: Main oscillator: PLL mode, Sub oscillator: Crystal mode Crystal GND Xin Xout GND VDD Xin Suboscillator GND R-OSCI OSCO GND VDD R-OSCI Mainoscillator JP 5 PLL Mode 3: Main oscillator: RC mode, Sub oscillator: Crystal Crystal GND Xin Xout GND VDD Xin Suboscillator GND R-OSCI OSCO GND VDD R-OSCI Mainoscillator JP 5 RC Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) • 73 EM78P468N/L 8-Bit Microcontroller Mode 4: Main oscillator: Crystal mode, Sub oscillator: RC mode RC GND Xin Xout GND VDD Xin Suboscillator GND R-OSCI OSCO GND VDD R-OSCI Mainoscillator JP 5 Crystal Mode 5: Main oscillator: PLL mode, Sub oscillator: RC mode RC GND Xin Xout GND VDD Xin Suboscillator GND R-OSCI OSCO GND VDD R-OSCI Mainoscillator JP 5 PLL Mode 6: Main oscillator: RC mode, Sub oscillator: RC mode RC GND Xin Xout GND VDD Xin Suboscillator GND R-OSCI OSCO GND VDD R-OSCI Mainoscillator JP 5 RC 74 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) VB Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice) COM0 COM2 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16/P7.0 SEG18/P7.2 SEG20/P7.4 SEG22/P7.6 SEG24/P8.0 SEG26/P8.2 SEG28/P8.4 SEG30/P8.6 P6.7 P6.5 P6.3 P6.1 P5.7/IROUT P5.5/INT1 Xout VDD R-OSCI /RESET VLCD2 VA COM1 COM3 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17/P7.1 SEG19/P7.3 SEG21/P7.5 SEG23/P7.7 SEG25/P8.1 SEG27/P8.3 SEG29/P8.5 SEG31/P8.7 P6.6 P6.4 P6.2 P6.0 P5.6/TCC P5.4/INT0 Xin OSCO GND VLCD3 8-Bit Microcontroller EM78P468N/L D.2 ICE 468XA Output Pin Assignment (JP 3) JP 3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 • 75 EM78P468N/L 8-Bit Microcontroller E Quality Assurance and Reliability Test Category Solderability Pre-condition Test Conditions Remarks Solder temperature=245±5°C, for 5 seconds up to the stopper using a rosin-type flux Step 1: TCT, 65°C (15mins)~150°C (15mins), 10 cycles Step 2: Bake at 125°C, TD (endurance)=24 hrs Step 3: Soak at 30°C/60%，TD (endurance)=192 hrs Step 4: IR flow 3 cycles (Pkg thickness ≥ 2.5mm or 3 Pkg volume ≥ 350mm ----225±5°C) – For SMD IC (such as SOP, QFP, SOJ, etc) (Pkg thickness ≤ 2.5mm or 3 Pkg volume ≤ 350mm ----240±5°C) Temperature cycle test -65°C (15mins)~150°C (15mins), 200 cycles – Pressure cooker test TA =121°C, RH=100%, pressure=2 atm, TD (endurance)= 96 hrs – High temperature / High humidity test TA=85°C , RH=85%，TD (endurance) = 168 , 500 hrs – High-temperature storage life TA=150°C, TD (endurance) = 500, 1000 hrs – High-temperature operating life TA=125°C, VCC = Max. operating voltage, TD (endurance) = 168, 500, 1000 hrs – Latch-up TA=25°C, VCC = Max. operating voltage, 150mA/20V – ESD (HBM) TA=25°C, ≥ ± 3KV IP_ND,OP_ND,IO_ND IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD ESD (MM) TA=25°C, ≥ IP_PS,OP_PS,IO_PS ± 300V VDD-VSS(+),VDD_VSS (-) Mode E.1 Address Trap Detect An address trap detect is one of the MCU embedded fail-safe functions that detects MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a certain section of ROM, an internal recovery circuit is auto started. If a noise-caused address error is detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will then continue to execute the next program. 76 • Product Specification (V1.6) 12.31.2007 (This specification is subject to change without further notice)