PH86P489A 8-Bit Microcontroller with OTP ROM Product Specification DOC. VERSION 1.3 ELAN MICROELECTRONICS CORP. Feburary 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Elan Information Technology Group Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220 Europe: Shenzhen: Shanghai: Elan Microelectronics Corp. (Europe) Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai Corporation, Ltd. Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600 Contents Contents 1 2 3 4 GENERAL DESCRIPTION ......................................................................................... 1 FEATURES ................................................................................................................. 1 PIN ASSIGNMENT ..................................................................................................... 3 FUNCTION DESCRIPTION ........................................................................................ 6 4.1 Operational Registers......................................................................................... 7 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.2 R0 (Indirect Addressing Register) .......................................................................7 R1 (Time Clock /Counter)....................................................................................7 R2 (Program Counter) & Stack ...........................................................................7 R3 (Status Register) ..........................................................................................10 R4 (RAM Select Register).................................................................................10 R5~R7 (Port 5 ~ Port7) .....................................................................................10 R8~R1F and R20~R3E (General Purpose Register)........................................10 R3F (Interrupt Status Register) .........................................................................11 Special Purpose Registers ............................................................................... 11 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 A (Accumulator).................................................................................................11 CONT (Control Register)...................................................................................11 IOC5 ~ IOC7 (I/O Port Control Register) ..........................................................12 IOCB (Wake-up Control Register for Port6)......................................................12 IOCE (WDT Control Register) ...........................................................................13 IOCF (Interrupt Mask Register).........................................................................14 4.3 TCC/WDT & Prescaler ..................................................................................... 15 4.4 I/O Ports ........................................................................................................... 16 4.5 RESET and Wake-up ....................................................................................... 17 4.5.1 4.5.2 RESET ..............................................................................................................17 The Status of RST, T, and P of STATUS Register .............................................21 4.6 Interrupt ............................................................................................................ 22 4.7 Oscillator .......................................................................................................... 23 4.7.1 4.7.2 4.7.3 4.8 CODE Option Register ..................................................................................... 26 4.8.1 4.8.2 4.9 Oscillator Modes................................................................................................23 Crystal Oscillator/Ceramic Resonators(XTAL) ..................................................24 External RC Oscillator Mode.............................................................................25 Code Option Register (Word 0).........................................................................26 Customer ID Register (Word 1).........................................................................28 Power On Considerations ................................................................................ 28 4.10 External Power On Reset Circuit...................................................................... 28 4.11 Residue-Voltage Protection .............................................................................. 29 4.12 Instruction Set .................................................................................................. 30 4.13 Timing Diagram ................................................................................................ 33 Product Specification (V1.3) 02.10.2006 • iii Contents 5 6 ABSOLUTE MAXIMUM RATINGS ........................................................................... 34 DC ELECTRICAL CHARACTERISTICS .................................................................. 34 6.1 DC Electrical Characteristic.............................................................................. 34 6.2 AC Electrical Characteristic.............................................................................. 35 6.3 Device Characteristic ....................................................................................... 36 APPENDIX A B Package Types......................................................................................................... 50 Package Information............................................................................................... 50 Specification Revision History iv • Doc. Version Revision Description Date 1.0 Initial version 10/29/2004 1.1 Add four kinds of package type 03/30/2005 1.2 Add 28-skinny DIP package type 11/28/2005 1.3 Add new 28 pinassignment 02/10/2006 Product Specification (V1.3) 02.10.2006 PH86P489A 8-Bit Microcontroller with OTP ROM 1 GENERAL DESCRIPTION PH86P489A is an 8-bit microprocessor with low-power and high-speed CMOS technology and high noise immunity. It is equipped with 4K*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits to prevent user’s code in the OTP memory from being intruded. Seven OPTION bits are also available to meet user’s requirements. With its OTP-ROM feature, the PH86P489A is able to offer a convenient way of developing and verifying user’s programs. Moreover, user can take advantage of ELAN Writer to easily program his development code. 2 FEATURES Operating voltage range: 2.5V~5.5V. Operating temperature range: -40°C~85°C. Operating frequency rang( base on 2 clocks) • Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V. • RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V. Low power consumption: • Less then 2.2 mA at 5V/4MHz • Typically 35 μA, at 3V/32KHz • Typically 2 μA, during sleep mode 4K × 13 bits on chip ROM Three protection bits to prevent intrusion of OTP memory codes One configuration register to accommodate user’s requirements 148× 8 bits on chip registers(SRAM, general purpose register) 3 bi-directional I/O ports 5 level stacks for subroutine nesting 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Two clocks per instruction cycle Power down (SLEEP) mode Two available interruptions • TCC overflow interrupt • External interrupt Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) •1 PH86P489A 8-Bit Microcontroller with OTP ROM Programmable free running watchdog timer 10 programmable pull-high pins 2 programmable open-drain pins 2 programmable R-option pins Package types: • • • • • • • • • • • • • • • 2• 20 pin DIP 300mil :PH86P489ADP 20 pin SOP 300mil :PH86P489ADM 24 pin Skinny DIP 300mil :PH86P489ACK 24 pin SOP 300mil :PH86P489ACM 28 pin DIP 600mil :PH86P489AAP 28 pin DIP 600mil :PH86P489AEP 28 pin skinny DIP 300mil :PH86P489AAK 28 pin skinny DIP 300mil :PH86P489AEK 28 pin skinny DIP 400mil :PH86P489AFK 28 pin skinny DIP 400mil :PH86P489AGK 28 pin SOP 300mil :PH86P489AAM 28 pin SSOP 209mil :PH86P489AAS 32 pin DIP 600mil :PH86P489ABP 32 pin SOP 450mil :PH86P489ABWM 32 pin skinny DIP 400mil :PH86P489ABK 99.9% single instruction cycle commands The transient point of system frequency between HXT and LXT is around 400KHz Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 3 PIN ASSIGNMENT TCC 1 VDD 2 NC 3 Vss 4 Fig. 1 Pin Assignment Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) •3 PH86P489A 8-Bit Microcontroller with OTP ROM Table 1 PH86P489AAP, PH86P489AAM and PH86P489AAK Pin Description Symbol Pin No. Type VDD 2 - OSCI 27 I OSCO 26 I/O TCC 1 I /RESET 28 I P50~P53 6~9 I/O P60~P67 10~17 I/O P70~P77 18~25 I/O Function ■ Power supply. ■ ■ ■ ■ ■ ■ XTAL type: Crystal input terminal or external clock input pin. RC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin) must be tied to VDD or VSS if not in use. ■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. ■ P50~P53 are bi-directional I/O pins. ■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by software control. ■ P70~P77 are bi-directional I/O pins. ■ P74~P75 can be pulled-high internally by software control. ■ P76~P77 can have open-drain output by software control. ■ P70 and P71 can also be defined as the R-option pins. /INT 5 I ■ External interrupt pin triggered by falling edge. VSS 4 - ■ Ground. NC 3 - ■ No connection. Table 2 PH86P489AAS Pin Description Symbol Pin No. Type VDD 3 - OSCI 27 I OSCO 26 I/O TCC 2 I /RESET 28 I P50~P53 5~8 I/O 9~13, P60~P67 15~17 I/O P70~P77 18~25 I/O Function ■ Power supply. ■ ■ ■ ■ ■ ■ XTAL type: Crystal input terminal or external clock input pin. RC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin) must be tied to VDD or VSS if not in use. ■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. ■ P50~P53 are bi-directional I/O pins. ■ P60~P67 are bi-directional I/O pins. These can be pulled –high internally by software control. ■ P70~P77 are bi-directional I/O pins. ■ P74~P75 can be pulled –high internally by software control. ■ P76~P77 can have open-drain output by software control. ■ P70 and P71 can also be defined as the R-option pins. /INT 4 I ■ External interrupt pin triggered by falling edge. VSS 1,14 - ■ Ground. 4• Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Table 3 PH86P489ABP and PH86P489AWM Pin Description Symbol Pin No. Type Function VDD 4 - OSCI 29 I OSCO 28 I/O TCC 3 I /RESET 30 I P50~P57 8~11,2~1, 32~31 I/O P60~P67 12~19 I/O P70~P77 20~27 I/O /INT 7 I ■ External interrupt pin triggered by falling edge. VSS 6 - ■ Ground. NC 5 - ■ No connection. ■ Power supply. ■ ■ ■ ■ ■ ■ XTAL type: Crystal input terminal or external clock input pin. RC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. ■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will keep in reset condition. ■ P50~P57 are bi-directional I/O pins. ■ P60~P67 are bi-directional I/O pins. These can be pulled –high internally by software control. ■ P70~P77 are bi-directional I/O pins. ■ P74~P75 can be pulled-high internally by software control. ■ P76~P77 can have open-drain output by software control. ■ P70 and P71 can also be defined as the R-option pins. Table 4 PH86P489ACK and PH86P489ACM Pin Description Symbol Pin No. Type Function VDD 3 - OSCI 23 I OSCO 22 I/O TCC 2 I /RESET 24 I P50~P54 6~9,1 I/O P60~P67 10~17 I/O P74~P77 18~21 I/O /INT 5 I ■ External interrupt pin triggered by falling edge. VSS 4 - ■ Ground. NC 3 - ■ No connection. ■ Power supply. ■ ■ ■ ■ ■ ■ XTAL type: Crystal input terminal or external clock input pin. RC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin) must be tied to VDD or VSS if not in use. ■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. ■ P50~P54 are bi-directional I/O pins. ■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by software control. ■ P74~P77 are bi-directional I/O pins. ■ P74~P75 can be pulled-high internally by software control. ■ P76~P77 can have open-drain output by software control. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) •5 PH86P489A 8-Bit Microcontroller with OTP ROM Table 5 PH86P489ADK and PH86P489ADM Pin Description Symbol Pin No. Type VDD 3 - OSCI 19 I OSCO 18 I/O TCC 2 I /RESET 20 I P50~P54 6~9,1 I/O 10 I/O 11~17 I/O P60 P71~P77 Function ■ Power supply. ■ ■ ■ ■ ■ ■ XTAL type: Crystal input terminal or external clock input pin. RC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin) must be tied to VDD or VSS if not in use. ■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. ■ P50~P54 are bi-directional I/O pins. ■ P60 are bi-directional I/O pins. This can be pulled-high internally by software control. ■ P74~P77 are bi-directional I/O pins. ■ P74~P75 can be pulled-high internally by software control. ■ P76~P77 can have open-drain output by software control. ■ P71 can also be defined as the R-option pins. /INT 5 I ■ External interrupt pin triggered by falling edge. VSS 4 - ■ Ground. NC 3 - ■ No connection. Table 6 PH86P489AEP and PH86P489AEK Pin Description Symbol Pin No. Type VDD 3 - OSCI 27 I OSCO 26 I/O /RESET 28 I Function ■ Power supply. ■ ■ ■ ■ ■ ■ XTAL type: Crystal input terminal or external clock input pin. RC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. P50~P55 6~9,2~1 I/O P60~P67 10~17 I/O P70~P77 18~25 I/O /INT 5 I ■ External interrupt pin triggered by falling edge. VSS 4 - ■ Ground. 6• ■ P50~P55 are bi-directional I/O pins. ■ P60~P67 are bi-directional I/O pins. This can be pulled-high internally by software control. ■ P74~P77 are bi-directional I/O pins. ■ P74~P75 can be pulled-high internally by software control. ■ P76~P77 can have open-drain output by software control. ■ P71 and P71 can also be defined as the R-option pins. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 4 FUNCTION DESCRIPTION OSCI /R E S E T OSCO TCC /IN T W D T T im e r STACK 1 P C O s c illa to r/T im in g STACK 2 C o n tro l STACK 3 P re s c a le STACK 5 W DT T im -e o u t In te rru p t C o n tro l R 1 (T C C ) In s tru c tio n R e g is te r ALU In s tru c tio n D ecoder RAM S le e p & W ake C o n tro l STACK 4 ROM r R3 ACC R4 DATA & CO NTRO L BUS IO C 5 R5 IO C 6 R6 PPPPPPPP 55555555 0 1 2 3 45 6 7 PPPPPPPP 66666666 0 1 2 3 45 6 7 IO C 7 R7 PPPPPPPP 77777777 0 1 2 3 45 6 7 Fig. 2 Functional Block Diagram Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) •7 PH86P489A 8-Bit Microcontroller with OTP ROM 4.1 Operational Registers 4.1.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function is to act as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 4.1.2 R1 (Time Clock /Counter) Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. Writable and readable as any other registers. Defined by resetting PAB (CONT-3). The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset. The contents of the prescaler counter will be cleared only when TCC register is written a value. 4.1.3 R2 (Program Counter) & Stack 8• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3. Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. R2 is set as all “0”s when under RESET condition. “JMP” instruction allows direct loading of the lower 10 program counter bits. Thus, “JMP” allows PC to go to any location within a page. “CALL” instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. “RET” (“RETL k”, “RETI”) instruction loads the program counter with the contents of the top-level stack. “ADD R2,A” allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of the PC are cleared. “MOV R2,A” allows to load an address from the “A” register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared. Any instruction that writes to R2 (e.g. “ADD R2,A”, “MOV R2,A”, “BC R2,6”,⋅⋅⋅⋅⋅) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle. R3 A11 A10 A9 A8 A7 ~ A0 00 PAGE0 0000~03FF 01 PAGE1 0400~07FF 10 PAGE2 0800~0BFF 11 PAGE3 0C00~0FFF Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 000H 001H 002H User Memory Space CALL RET RETL RETI Hardware Vector Software Vector On-chip Program Memory Reset Vector FFFH Fig. 3 Program Counter Organization Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) •9 PH86P489A 8-Bit Microcontroller with OTP ROM Aaddress R PAGE registers IOC PAGE registers 00 R0 (Indirect Addressing Register) Reserve 01 R1 (Time Clock Counter) 02 R2 (Program Counter) Reserve 03 R3 (Status Register) Reserve 04 R4 (RAM Select Register) Reserve 05 R5 (Port5) IOC5 (I/O Port Control Register) 06 R6 (Port6) IOC6 (I/O Port Control Register) 07 R7 (Port7) IOC7 (I/O Port Control Register) CONT (Control Register) 08 General Register Reserve 09 General Register Reserve 0A General Register Reserve 0B General Register 0C General Register Reverse 0D General Register Reverse 0E General Register IOCE (WDT,SLEEP2,Open Drain,R -Option Control Register) 0F General Register IOCF (Interrupt Mask Register) 10 ︰ 1F General Registers 20 ： 3E Bank0 3F R3F Bank1 Bank2 IOCB (Wake-Up Control Register for Port6 ) Bank3 (Interrupt Status Register) Fig. 4 Data Memory Configuration 10 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 4.1.4 R3 (Status Register) 7 6 5 4 3 2 1 0 GP PS1 PS0 T P Z DC C Bit 7 (GP) General read/write bit. Bits 6 (PS1) ~ 5 (PS0) Page select bits. PS1~PS0 are used to pre-select a program memory page. When executing a “JMP”, “CALL”, or other instructions which causes the program counter to change (e.g. MOV R2, A), PS1~PS0 are loaded into the 11th and 12th bits of the program counter and select one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine was called, regardless of the PS1~PS0 bits current setting. PS1 PS0 Program memory page [Address] 0 0 Page 0 [000-3FF] 0 1 Page 1 [400-7FF] 1 0 Page 2 [800-BFF] 1 1 Page 3 [C00-FFF] Bit 4 (T) Time-out bit. Set to 1 with the “SLEP” and “WDTC” commands, or during power up, and reset to 0 with the WDT time-out. Bit 3 (P) Power down bit. Set to 1 during power on or by a “WDTC” command and reset to 0 by a “SLEP” command. Bit 2 (Z) Zero flag. Set to “1” if the result of an arithmetic or logic operation is zero. Bit 1 (DC) Auxiliary carry flag. Bit 0 I Carry flag 4.1.5 R4 (RAM Select Register) Bits 7~6 determine which bank is activated among the 4 banks. Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing mode. If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose read/writer register. See the configuration of the data memory in Fig. 4. 4.1.6 R5~R7 (Port 5 ~ Port7) R5, R6 and R7 are I/O registers 4.1.7 R8~R1F and R20~R3E (General Purpose Register) R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 11 PH86P489A 8-Bit Microcontroller with OTP ROM 4.1.8 R3F (Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - EXIF - - TCIF Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software Bit 0 (TCIF) the TCC overflow interrupt flag. Set as TCC overflows; flag cleared by software. Bits 1, 2, 4~7 are not used and read are as “0”. “1” means interrupt request, “0” means non-interrupt. R3F can be cleared by instruction, but cannot be set by instruction. IOCF is the interrupt mask register. Note that reading R3F will obtain the result of the R3F “logic AND” and IOCF. 4.2 Special Purpose Registers 4.2.1 A (Accumulator) Internal data transfer, or instruction operand holding. It cannot be addressed. 4.2.2 CONT (Control Register) 7 6 5 4 3 2 1 0 /PHEN /INT TS TE PAB PSR2 PSR1 PSR0 Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins 0: Enable internal pull-high. 1: Disable internal pull-high. CONT register is both readable and writable. Bit 6 (/INT) Interrupt enable flag 0: masked by DISI or hardware interrupt 1: enabled by ENI/RETI instructions Bit 5 (TS) TCC signal source 0: internal instruction cycle clock 1: transition on TCC pin 12 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on TCC pin 1: increment if the transition from high to low takes place on TCC pin Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits. PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 4.2.3 IOC5 ~ IOC7 (I/O Port Control Register) “1” put the relative I/O pin into high impedance, while “0” defines the relative I/O pin as output. IOC5 and IOC7 registers are both readable and writable. 4.2.4 IOCB (Wake-up Control Register for Port6) 7 6 5 4 3 2 1 0 /WUE7 /WUE6 /WUE5 /WUE4 /WUE3 /WUE2 /WUE1 /WUE0 Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin. Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin. Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin. Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin. Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin. Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin. Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin. Bit 0 (/WUE0) Control bit is used to enable the wake-up function of P60 pin. 0: Enable internal wake-up. 1: Disable internal wake-up. IOCB Register is both readable and writable. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 13 PH86P489A 8-Bit Microcontroller with OTP ROM 4.2.5 IOCE (WDT Control Register) 7 6 5 4 3 2 1 0 - ODE WDTE SLPC ROC - - /WUE Bit 6 (ODE) Control bit is used to enable the open-drain of P76 and P77 pins 0: Disable open-drain output. 1: Enable open-drain output. The ODE bit can be read and written. Bit 5 (WDTE) Control bit used to enable Watchdog timer. The WDTE bit is useful only when ENWDT, the CODE Option bit, is “0”. It is only when the ENWDT bit is “0” that WDTE bit. Is able to disabled/enabled the WDT. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is “1”. That is, if the ENWDT bit is “1”, WDT is always disabled no matter what the WDTE bit status is. The WDTE bit can be read and written. Bit 4 (SLPC) This bit is set by hardware at the low level trigger of wake-up signal and is cleared by software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is stopped, and the controller enters into SLEEP2 mode) on the high-to-low transition and is enabled (controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18ms 1 (oscillator start-up timer, OST) before the next instruction of the program is executed. The OST is always activated by a wake-up event from sleep mode regardless of the Code Option bit ENWDT status is “0” or otherwise. After waking up, the WDT is enabled if the Code Option ENWDT is “1”. The block diagram of SLEEP2 mode and wake-up invoked by an input trigger is depicted in Fig. 5. The SLPC bit can be read and written. Bit 3 (ROC) ROC is used for the R-option. Setting ROC to “1” will enable the status of R-option pins (P70, P71) for the controller to read. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P71 pin or/and P70 pin to VSS with a 430KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P70 (P71) will be read as “0”/”1” (refer to Fig. 7(b)). The ROC bit can be read and written. 1 14 • <Note>: Vdd = 5V, set up time period = 16.2ms ± 30% Vdd = 3V, set up time period = 19.6ms ± 30% Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Bit 0 (/WUE) Control bit is used to enable the wake-up function of P74 and P75. 0: Enable the wake-up function. 1: Disable the wake-up function. The /WUE bit can be read and written. Bits 1~2, and 7 Not used. 4.2.6 IOCF (Interrupt Mask Register) 7 6 5 4 3 2 1 0 - - - - EXIE - - TCIE Bit 3 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt Bits 1, 2 and 4~7 Not used. Individual interrupt is enabled by setting its associated control bit in the IOCF to “1”. Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction (refer to Fig. 9). IOCF Register is Both Readable and Writable. /WUE0 Oscillator Enable Disable /WUE1 Reset Q PR D CLK Q Clear VCC CL Set 8 /WUE7 from S/W P60~P67 VCC /WUE /PHEN 2 P74~P75 Fig. 5 Sleep Mode and Wake-Up Circuits on I/O Ports Block Diagram Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 15 PH86P489A 8-Bit Microcontroller with OTP ROM 4.3 TCC/WDT & Prescaler An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the “WDTC” or “SLEP” instructions. Fig. 6 depicts the circuit diagram of TCC/WDT. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input (edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). Referring to Fig. 6, CLK=Fosc/2 or CLK=Fosc/4 selection is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is “0”, and CLK=Fosc/4 is used if CLK bit is “1”. If TCC signal source comes from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without prescaler, the WDT time-out period is approximately 18 ms2 (default). Data Bus CLK(=Fosc/2) 0 TCC Pin 1 1 M U X 0 M U X SYNC 2 cycles TE TS TCC(R1) TCC overflow interrupt PAB 0 WDT 1 M U X 8-bit Counter 8-to-1 MUX WDTE (in IOCE) PSR0~PSR2 PAB 0 1 MUX PAB WDT timeuot Fig. 6 TCC and WDT Block Diagram 2 16 • <Note>: Vdd = 5V, set up time period = 16.2ms ± 30% Vdd = 3V, set up time period = 19.6ms ± 30% Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 4.4 I/O Ports The I/O registers, Port 5, Port 6, and Port 7, are bi-directional tri-state I/O ports. The functions of Pull-high, R-option, and Open-drain can be performed internally by CONT and IOCE respectively. There is input status change wake-up function on Port 6, P74, and P75. Each I/O pin can be defined as “input” or “output” pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are shown in Figures. 7(a) and (b) respectively. PCRD Q PR D PCWR CLK Q CL IOD Q PR D PORT PDWR CLK Q 0 1 CL M U X PDRD Fig. 7 (a) The I/O Port and I/O Control Register Circuit PCRD VCC ROC Q PR D Weakly Pull- up CLK Q PORT Q PR Q CL IOD D CLK 0 Rex* 1 PCWR CL M U X PDWR PDRD *The Rex is 430K ohm external resistor Fig.7 (b) The I/O Port with R-Option (P70, P71) Circuit Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 17 PH86P489A 8-Bit Microcontroller with OTP ROM 4.5 RESET and Wake-up 4.5.1 RESET A RESET is initiated by one of the following events600 Power on reset, or (2) /RESET pin input “low”, or (3) WDT timeout. (if enabled) The device is kept in a RESET condition for a period of approx. 18ms 3 (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed (refer to Fig.8). The oscillator starts or is running The Program Counter (R2) is set to all “1”. When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared. All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared. Upon power on, the bits 5~6 of R3 are cleared. Upon power on, the upper 2 bits of R4 are cleared. The bits of CONT register are set to all “1” except bit 6 (INT flag). IOCB register is set to ”1” (disable P60 ~ P67 wake-up function). Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to “1”. Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared. The sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by600 External reset input on /RESET pin; (2) WDT time-out (if enabled) The above two cases will cause the controller PH86P489A to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). In addition to the basic SLEEP1 MODE, PH86P489A has another sleep mode (designated as SLEEP2 MODE and is invoked by clearing the IOCE register “SLPC” bit). In the SLEEP2 MODE, the controller can be awakened by- 3 18 • NOTE: Vdd = 5V, set up time period = 16.2ms ± 30% Vdd = 3V, set up time period = 19.6ms ± 30% Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 600 Any of the wake-up pins is “0” as illustrated in Figure. 5. Upon waking, the controller will continue to execute the succeeding address. Under this case, before entering SLEEP2 MODE, the wake-up function of the trigger sources (P60~P67 and P74~P75) should be selected (e.g., input pin) and enabled (e.g., pull-high, wake-up control). It should be noted that after waking up, the WDT is enabled if the Code Option bit ENWDT is “0”. The WDT operation (to be enabled or disabled) should be appropriately controlled by software after waking up. (B) WDT time-out (if enabled) or external reset input on /RESET pin will trigger a controller reset. Table 7 Usage of Sleep1 and Sleep2 Mode Usage of Sleep1 and Sleep2 Mode SLEEP2 SLEEP1 (a) Before SLEEP (a) Before SLEEP 1. Set Port6 or P74 or P75 Input 2. Enable Pull-High and set WDT prescaler over 1:1 (Set CONT.7 and CONT.3 ~ CONT.0) 3. Enable Wake-up (Set IOCB or IOCE.0) 1. Execute SLEP instruction 4. Execute Seep2 (Set IOCE.4) (b) After Wake-up 1. Next instruction (b) After Wake-up 1. Reset 2. Disable Wake-up 3. Disable WDT (Set IOCE.5) If Port6 Input Status Changed Wake-up is used to wake-up the PH86P489A (Case [a] above), the following instructions must be executed before entering SLEEP2 mode: MOV A, @11111111b ; Set Port6 input IOW R6 MOV A, @0xxx1010b ; Set Port6 pull-high, WDT prescaler, prescaler must set over 1:1 MOV A, @00000000b ; Enable Port6 wake-up function IOW MOV IOW After Wake-up NOP RB A, @xx00xxx1b RE ; Enable SLEEP2 MOV A, @11111111b ; Disable Port6 wake-up function IOW RB MOV A, @ xx01xxx1b ; Disable WDT IOW RE CONTW Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 19 PH86P489A 8-Bit Microcontroller with OTP ROM NOTE After waking up from the SLEEP2 mode, WDT is automatically enabled. The WDT enabled/disabled operation after waking up from SLEEP2 mode should be appropriately defined in the software. To avoid reset from occurring when the port6 status changed interrupt enters into interrupt vector or is used to wake-up the MCU, the WDT prescaler must be set above 1:1 ratio. Table 8 The Summary of the Initialized Values for Registers Address N/A N/A N/A N/A 0x00 0x01 0x02 0x03 0x04 20 • Name IOC5 IOC6 IOC7 CONT R0(IAR) R1(TCC) R2(PC) R3(SR) R4(RSR) Reset Type Bit 7 Bit Name C57 Type A B Power-On 0 1 /RESET and WDT 0 1 Wake-Up from Pin 0 P Change Bit Name C67 Power-On 1 /RESET and WDT 1 Wake-Up from Pin P Change Bit Name C77 Power-On 1 /RESET and WDT 1 Wake-Up from Pin P Change Bit Name /PHEN Power-On 1 /RESET and WDT 1 Wake-Up from Pin P Change Bit Name Power-On U /RESET and WDT P Wake-Up from Pin P Change Bit Name Power-On 0 /RESET and WDT 0 Wake-Up from Pin P Change Bit Name Power-On 1 /RESET and WDT 1 Wake-Up from Pin **0/P Change Bit Name GP Power-On 0 /RESET and WDT 0 Wake-Up from Pin P Change Bit Name RSR.1 Power-On 0 /RESET and WDT 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C56 A B 0 1 0 1 C55 A B 0 1 0 1 C54 A B 0 1 0 1 C53 1 1 C52 1 1 C51 1 1 C50 1 1 0 0 0 P P P P P P P C66 1 1 C65 1 1 C64 1 1 C63 1 1 C62 1 1 C61 1 1 C60 1 1 P P P P P P P C76 1 1 C75 1 1 C74 1 1 C73 1 1 C72 1 1 C71 1 1 C70 1 1 P P P P P P P /INT 0 P TS 1 1 TE 1 1 P P P P P P P U P U P U P U P U P U P U P P P P P P P P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 **0/P **0/P **0/P PS1 0 0 PS0 0 0 T 1 t P 1 t Z U P DC U P C U P P P t t P P P RSR.0 0 0 U P U P U P U P U P U P PAB PSR2 PSR1 PSR0 1 1 1 1 1 1 1 1 **0/P **0/P **0/P **0/P Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Address 0x05 0x06 0x07 0x3F Name Reset Type R5(P5) R6(P6) R7(P7) R3F(ISR) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P P P P P P P P P57 U P P56 U P P55 U P P54 U P P53 U P P52 U P P51 U P P50 U P P P P P P P P P P67 U P P66 U P P65 U P P64 U P P63 U P P62 U P P61 U P P60 U P P P P P P P P P P77 U P P76 U P P75 U P P74 U P P73 U P P72 U P P71 U P P70 U P P P P P P P P P U U U U U U U U EXIF 0 0 U U U U TCIF 0 0 U U U U P U U P /WUE7 /WUE6 /WUE5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P P P P P P P P U U ODE 0 0 WDTE 1 1 SLPC 1 1 ROC 0 0 U U U U /WUE 1 1 U P 1 1 P U U P U U U U U U U U EXIE 0 0 U U U U TCIE 0 0 U U U U P U U P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P - - - - - - - - Power-On U U U U U U U U /RESET and WDT Wake-Up from Pin Change P P P P P P P P P P P P P P P P Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name 0x0B 0x0E 0x0F 0x08 0x09~0x3E IOCB IOCE IOCF R8 R9~R3E Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name /WUE4 /WUE3 /WUE2 /WUE1 /WUE0 ** To execute next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition. X：Not used. U: Unknown or don’t care. P: Previous value before reset. T: Check Table 8 Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 21 PH86P489A 8-Bit Microcontroller with OTP ROM 4.5.2 The Status of RST, T, and P of STATUS Register A RESET condition is initiated by one of the following events: 600 A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of T and P (listed in Table 9 below) are used to verify the event that triggered the processor to wake up. Table 9 shows the events that may affect the status of T and P. Table 9 The Values of RST, T and P after RESET Reset Type T Power on /RESET during Operating mode /RESET wake-up during SLEEP1 mode /RESET wake-up during SLEEP2 mode WDT during Operating mode WDT wake-up during SLEEP1 mode WDT wake-up during SLEEP2 mode Wake-Up on pin change during SLEEP2 mode P 1 1 *P *P 1 0 *P *P *P 0 0 0 *P 0 *P *P *P: Previous status before reset Table 10 The Events that may Affect the T and P Status Event T P Power on 1 1 WDTC instruction 1 1 WDT time-out 0 *P SLEP instruction 1 0 Wake-Up on pin change during SLEEP2 mode *P *P *P: Previous value before reset 22 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM VDD D CLK Oscillator Q CLK CLR Power-on Reset Voltage Detector WDTE WDT WDT Timeout Setup Time RESET /RESET Fig. 8 Controller Reset Block Diagram 4.6 Interrupt The PH86P489A has two interrupts listed below: 600 TCC overflow interrupt (2) External interrupt (/INT pin). R3F is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is the interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from address 001H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in R3F. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of R3F are the logic AND of R3F and IOCF (refer to Fig. 9). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from address 002H. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 23 PH86P489A 8-Bit Microcontroller with OTP ROM VCC P R D /IRQn CLK C L Q IRQn INT _ Q RFRD IRQm RF ENI/DISI P R Q IOCF _ Q C L IOD D CLK IOCFWR /RESET IOCFRD RFWR Fig. 9 Interrupt Input Circuit 4.7 Oscillator 4.7.1 Oscillator Modes The PH86P489A can operate in three different oscillator modes, i.e., high XTAL (HXT) oscillator mode, low XTAL (LXT) oscillator mode, and External RC oscillator mode (ERC) oscillator mode. User can select one of them by programming MS, HLF and HLP in the Code Option Register. Table 11 depicts how these three modes are defined. The maximum limit for operational frequencies of crystal/resonator under different VDDs is listed in Table 11. Table 11 Oscillator Modes Defined by MS and HLP Mode MS HLF HLP ERC(External RC oscillator mode) 0 *X HXT(High XTAL oscillator mode) 1 1 *X *X LXT(Low XTAL oscillator mode) 1 0 0 NOTE 600 X, Don’t care 2. The transient point of system frequency between HXT and LXY is around 400 KHz. 24 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Table 12 The Summary of Maximum Operating Speeds Conditions VDD Fxt max.(MHz) 2.3 4.0 3.0 8.0 5.0 20.0 Two cycles with two clocks 4.7.2 Crystal Oscillator/Ceramic Resonators(XTAL) PH86P489A can be driven by an external clock signal through the OSCI pin as shown in Fig. 10 below. In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 12 depicts such circuit. The same thing applies whether it is in the HXT mode or in the LXT mode. Table 13 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS. A serial resistor may be necessary for AT strip cut crystal or low frequency mode. Ext. Clock OSCI OSCO PH86P489A Fig. 10 Crystal/Resonator Circuit C1 OSCI PH86P489A XTAL OSCO RS C2 Fig. 11 Crystal/Resonator Circuit Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 25 PH86P489A 8-Bit Microcontroller with OTP ROM Table 13 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode Frequency C1(Pf) C2(Pf) 455 kHz 100~150 100~150 Ceramic Resonators HXT 2.0 MHz 20~40 20~40 4.0 MHz 10~30 10~30 LXT 32.768kHz 100KHz 25 25 15 25 Crystal Oscillator HXT 200KHz 25 25 455KHz 20~40 20~150 1.0MHz 15~30 15~30 2.0MHz 15 15 4.0MHz 15 15 4.7.3 External RC Oscillator Mode For some applications that do not need a very precise timing calculation, the RC oscillator (Fig. 15) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20Pf, and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly. Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency. VCC Rext OSCI PH86P489A Cext Fig. 12 External RC Oscillator Mode Circuit 26 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Table 14 RC Oscillator Frequencies Cext 20 Pf 100 Pf 300 Pf Rext Average Fosc 5V,25°C Average Fosc 3V,25°C 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 4.32 MHz 2.83 MHz 1.62MHz 184 KHz 1.39 MHz 950 KHz 500 KHz 54KHz 580 KHz 390 KHz 200 KHz 21 KHz 3.56 MHz 2.8 MHz 1.57 MHz 187 KHz 1.35 MHz 930 KHz 490 KHz 55 KHz 550 KHz 380 KHz 200 KHz 21 KHz NOTE 600 Measured on DIP packages. 2. For design reference only. 4.8 CODE Option Register The PH86P489A has one CODE option word that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: Word 0 Word 1 Bit12~Bit0 Bit12~Bit0 4.8.1 Code Option Register (Word 0) Word 0 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - - EC - CLKS ENWDTB TYPE HLF OSC HLP PR2 PR1 PR0 Bit 12 、11 : Not used. Reserved. The bit set to “1” all the time. Bit 10 (EC): Error recovery Bit. 0: Enable 1: Disable Bit 9: Not used. Reserved. The bit set to “0” all the time. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 27 PH86P489A 8-Bit Microcontroller with OTP ROM Bit 8 (CLKS): Instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. Refer to the section on Instruction Set. Bit 7(ENWDTB): Watchdog timer enable bit. 0: Enable 1: Disable Type selection for PH86P489AA or PH86P489AB Bit 6: 0: PH86P489AB 1: PH86P489AA Bit 5 (HLF): XTAL frequency selection 0: XTAL2 type (low frequency, 32.768KHz) 1: XTAL1 type (high frequency) This bit will affect system oscillation only when Bit4 (OSC) is “1”. When OSC is”0”, HLF must be “0”. NOTE The transient point of system frequency between HXT and LXY is around 400 KHz. Bit 4 (OSC): Oscillator type selection. 0:RC type 1:XTAL type (XTAL1 and XTAL2) Bit 3 (HLP): Power selection. 0: Low power 1: High power Bit 2~0 (PR2~PR0): Protect Bit PR2~PR0 are protect bits, protect type as following 28 • PR2 PR1 PR0 Protect 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Enable Enable Enable Enable Enable Enable Enable Disable Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 4.8.2 Customer ID Register (Word 1) Word 1 Bit 12~Bit 0 XXXXXXXXXXXXX Bit 12~0: Customer’s ID code 4.9 Power On Considerations Any microcontroller is not guaranteed to start and operate properly before the power supply stays at its steady state. PH86P489A is equipped with Power On Voltage Detector(POVD) with a detecting level is 2.0V. It will work well if Vdd rises fast enough (10 ms or less). In many critical applications, however, extra devices are still required to assist in solving power-up problems. 4.10 External Power On Reset Circuit The circuit shown in Fig.16 implements an external RC to produce the reset pulse. The pulse width (time constant) should be kept long enough for Vdd to reached minimum operation voltage. This circuit is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is about ±5μA, it is recommended that R should not be greater than 40 K. In this way, the /RESET pin voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET. Vdd R /RESET D PH86P489A Rin C Fig. 13 External Power-Up Reset Circuit Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 29 PH86P489A 8-Bit Microcontroller with OTP ROM 4.11 Residue-Voltage Protection When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The residue-voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power on reset. Fig.16 and Fig.17 show how to build the residue-voltage protection circuit. Vdd Vdd 33K PH86P489A Q1 10K /RESET 40K 1N4684 Fig. 14 The Residue Voltage Protection Circuit 1 Vdd Vdd R1 PH86P489A Q1 /RESET 40K R2 s Fig. 15 The Residue Voltage Protection Circuit 2 30 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 4.12 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction “MOV R2,A”, “ADD R2,A”, or by instructions of arithmetic or logic operation on R2 (e.g. “SUB R2,A”, “BSI R2,6”, “CLR R2”, ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: 600 Change one instruction cycle to consist of 4 oscillator periods. (B) Executed within two instruction cycles, “JMP”, “CALL”, “RET”, “RETL”, “RETI”, or the conditional skip (“JBS”, “JBC”, “JZ”, “JZA”, “DJZ”, “DJZA”) instructions which were tested to be true. Also execute within two instruction cycles, the instructions that are written to the program counter. Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high. Note that once the 4 oscillator periods within one instruction cycle is selected as in Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/ 2 as indicated in Fig. 5. In addition, the instruction set has the following features: 600 Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The symbol “R” represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. “b” represents a bit field designator that selects the value for the bit which is located in the register “R”, and affects operation. “k” represents an 8 or 10-bit constant or literal value. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 31 PH86P489A 8-Bit Microcontroller with OTP ROM INSTRUCTION BINARY HEX MNEMONIC OPERATION STATUS AFFECTED 0 0000 0000 000 0000 NOP No Operation None 0 0000 0000 001 0001 DAA Decimal Adjust A C 0 0000 0000 010 0002 CONTW A → CONT None 0 0000 0000 011 0003 SLEP 0 → WDT, Stop oscillator T,P 0 0000 0000 100 0004 WDTC 0 → WDT T,P 0 0000 0000 rrrr 000r IOW R A → IOCR None <Note1> 0 0000 0001 000 0010 ENI Enable Interrupt None 0 0000 0001 001 0011 DISI Disable Interrupt None 0 0000 0001 010 0012 RET [Top of Stack] → PC None 0 0000 0001 011 0013 RETI [Top of Stack] → PC, Enable Interrupt None 0 0000 0001 100 0014 CONTR CONT → A None 0 0000 0001 rrrr 001r IOR R IOCR → A None <Note1> 0 0000 0010 000 0020 TBL R2+A → R2, Bits 8~9 of R2 unchanged Z,C,DC 0 0000 01rr rrrr 00rr MOV R,A A→R None 0 0000 1000 000 0080 CLRA 0→A Z 0 0000 11rr rrrr 00rr CLR R 0→R Z 0 0001 00rr rrrr 01rr SUB A,R R-A → A Z,C,DC 0 0001 01rr rrrr 01rr SUB R,A R-A → R Z,C,DC 0 0001 10rr rrrr 01rr DECA R R-1 → A Z 0 0001 11rr rrrr 01rr DEC R R-1 → R Z 0 0010 00rr rrrr 02rr OR A,R A∨R→A Z 0 0010 01rr rrrr 02rr OR R,A A∨R→R Z 0 0010 10rr rrrr 02rr AND A,R A&R→A Z 0 0010 11rr rrrr 02rr AND R,A A&R→R Z 0 0011 00rr rrrr 03rr XOR A,R A⊕R→A Z 0 0011 01rr rrrr 03rr XOR R,A A⊕R→R Z 0 0011 10rr rrrr 03rr ADD A,R A+R→A Z,C,DC 0 0011 11rr rrrr 03rr ADD R,A A+R→R Z,C,DC 0 0100 00rr rrrr 04rr MOV A,R R→A Z 0 0100 01rr rrrr 04rr MOV R,R R→R Z 0 0100 10rr rrrr 04rr COMA R /R → A Z 0 0100 11rr rrrr 04rr COM R /R → R Z 0 0101 00rr rrrr 05rr INCA R R+1 → A Z 0 0101 01rr rrrr 05rr INC R R+1 → R Z 32 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM INSTRUCTION BINARY HEX 0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None 0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr 06rr RLC R 0 0111 00rr rrrr 07rr SWAPA R 0 0111 01rr rrrr 07rr SWAP R R(0-3) ↔ R(4-7) None 0 0111 10rr rrrr 07rr JZA R R+1 → A, skip if zero None 0 0111 11rr rrrr 07rr JZ R R+1 → R, skip if zero None 0 100b bbrr rrrr 0xxx BC R,b 0 → R(b) None <Note2> 0 101b bbrr rrrr 0xxx BS R,b 1 → R(b) None <Note3> 0 110b bbrr rrrr 0xxx JBC R,b if R(b)=0, skip None 0 111b bbrr rrrr 0xxx JBS R,b if R(b)=1, skip None 1 00kk kkkk kkkk 1kkk CALL k PC+1 → [SP], (Page, k) → PC None 1 01kk kkkk kkkk 1kkk JMP k (Page, k) → PC None 1 1000 kkkk kkkk 18kk MOV A,k k→A None 1 1001 kkkk kkkk 19kk OR A,k A∨k→A Z 1 1010 kkkk kkkk 1Akk AND A,k A&k→A Z 1 1011 kkkk kkkk 1Bkk XOR A,k A⊕k→A Z 1 1100 kkkk kkkk 1Ckk RETL k k → A, [Top of Stack] → PC None 1 1101 kkkk kkkk 1Dkk SUB A,k k-A → A Z,C,DC 1 1110 0000 010 1E02 INT PC+1 → [SP], 002H → PC None 1 1111 kkkk kkkk 1Fkk ADD A,k k+A → A Z,C,DC MNEMONIC OPERATION R(n) → A(n-1), R(0) → C, C → A(7) R(n) → R(n-1), R(0) → C, C → R(7) R(n) → A(n+1), R(7) → C, C → A(0) R(n) → R(n+1), R(7) → C, C → R(0) R(0-3) → A(4-7), R(4-7) → A(0-3) STATUS AFFECTED C C C C None NOTE This instruction is applicable to IOC5 ~ IOC7, IOCB, IOCE, IOCF only. This instruction is not recommended for R3F operation. This instruction cannot operate under R3F. Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 33 PH86P489A 8-Bit Microcontroller with OTP ROM 4.13 Timing Diagram AC Test Input/O utput W aveform 2.4 2.0 0.8 TE S T P O IN TS 2.0 0.8 0.4 AC T estin g : Inp u t is d riven at 2.4V for lo gic "1",an d 0.4V for log ic "0".T im in g m easu rem en ts are m ade at 2.0V fo r lo g ic "1",an d 0.8V fo r lo gic "0". R E S E T Tim ing (C LK ="0") NOP Instruction 1 E xecuted C LK /R ESET T d rh TC C Input Tim ing (C LK S ="0") T in s CLK TCC T tcc 34 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 5 ABSOLUTE MAXIMUM RATINGS Items 6 Rating Temperature under bias -40°C to 85°C Storage temperature -65°C to 150°C Input voltage VSS-0.3V to VDD+0.5V Output voltage VSS-0.3V to VDD+0.5V Operating Frequency (2clk) 32.768KHz to 20MHz Operating Voltage 2.5V to 5.5V DC ELECTRICAL CHARACTERISTICS 6.1 DC Electrical Characteristic (Ta= 25 °C, VDD= 5.0V±5%, VSS= 0V ) Symbol FXT ERC IIL VIH1 VIL1 VIHT1 VILT1 VIHX1 VILX1 VIH2 VIL2 VIHT2 VILT2 VIHX2 VILX2 VOH1 VOL1 VOL2 Parameter Condition Min Typ. Max Unit XTAL: VDD to 3V Two cycle with two clocks DC 8.0 MHz XTAL: VDD to 5V Two cycle with two clocks DC 20.0 MHz ERC: VDD to 5V Input Leakage Current for input pins Input High Voltage (VDD=5V) R: 5.1KΩ, C: 100 Pf F±30% KHz ±1 μA Input Low Voltage (VDD=5V) Input High Threshold Voltage (VDD=5V) Input Low Threshold Voltage (VDD=5V) Clock Input High Voltage (VDD=5V) Clock Input Low Voltage (VDD=5V) Input High Voltage (VDD=3V) Input Low Voltage (VDD=3V) Input High Threshold Voltage (VDD=3V) Input Low Threshold Voltage (VDD=3V) Clock Input High Voltage (VDD=3V) Clock Input Low Voltage (VDD=3V) Output High Voltage (Ports 5, 6, 7) Output Low Voltage (Ports 5, 6) Output Low Voltage (Port7) IPH Pull-high current ISB1 Power down current F±30% 950 VIN = VDD, VSS Ports 5, 6,7 2.0 V Ports 5, 6,7 /RESET, TCC,INT 0.8 2.0 V /RESET, TCC,INT OSCI 0.8 3.5 1.5 1.5 0.4 1.5 0.4 2.1 V V OSCI IOH = -10.0 Ma V V /RESET, TCC,INT OSCI V V Ports 5, 6,7 /RESET, TCC,INT V V OSCI Ports 5, 6,7 V 0.9 2.4 V V IOL = 9.0 Ma 0.4 V IOL = 14.0 Ma 0.4 V -240 μA 1 μA Pull-high active, input pin at VSS All input and I/O pins at VDD, output pin floating, WDT disabled Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) -50 -100 • 35 PH86P489A 8-Bit Microcontroller with OTP ROM Symbol Parameter ISB2 Power down current ICC1 Operating supply current (VDD=3V) at two cycles/four clocks ICC2 Operating supply current (VDD=3V) at two cycles/four clocks ICC3 Operating supply current (VDD=5V) at two cycles/two clocks ICC4 Operating supply current (VDD=5V) at two cycles/four clocks Condition Min Typ. All input and I/O pins at VDD, output pin floating, WDT enabled /RESET= ‘High’, Fosc=32KHz (Crystal type,CLKS=”0”), output pin floating, WDT disabled /RESET= ‘High’, Fosc=32KHz (Crystal type,CLKS=”0”), output pin floating, WDT enabled /RESET= ‘High’, Fosc=4MHz (Crystal type, CLKS=”0”), output pin floating, WDT enabled /RESET= ‘High’, Fosc=10MHz (Crystal type, CLKS=”0”), output pin floating, WDT enabled Max Unit 7 μA 25 30 μA 30 35 μA 1.6 2.2 Ma 2.8 5.0 Ma 6.2 AC Electrical Characteristic (Ta=- -40°C ~ 85 °C, VDD=5V±5%, VSS=0V) Symbol Parameter Dclk Input CLK duty cycle Tins Instruction cycle time (CLKS=”0”) Ttcc TCC input period Conditions Min Typ Max Unit 45 50 55 % Crystal type 100 60000 ns RC type 500 100000 ns ns (Tins+20)/N* Tdrh Device reset hold time Ta = 25°C 11.3 Trst /RESET pulse width Ta = 25°C 2000 Twdt Watchdog timer period Ta = 25°C 11.3 Tset Input pin setup time 16.2 21.6 ms ns 16.2 21.6 0 ms ns Thold Input pin hold time 15 20 25 ns Tdelay Output pin delay time Cload=20Pf 45 50 55 ns Tiod I/O delay for EMI enable Cload=150Pf 4 5 6 ns Ttrr1 Rising time for EMI enable Cload=150Pf 190 200 210 ns Ttrf1 Falling time for EMI enable Cload=150Pf 190 200 210 ns Ttrr2 Rising time for EMI enable Cload=300Pf 380 400 420 ns Ttrf2 Falling time for EMI enable Cload=300Pf 380 400 420 ns Tdrc ERC delay time Ta = 25°C 1 3 5 ns Data in Typ. Is measured at 5V ,25°C N= selected prescaler ratio. 36 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 6.3 Device characteristic The graphic provided in the following pages were derived based on a limited number of samples and are shown here for reference only. The device characteristic illustrated herein are not guaranteed for it accuracy. In some graphic, the data maybe out of the specified warranted operating range. Vih/Vil (Input pins with schmitt inverter) 2 Vih max(-40℃ to 85℃ ) Vih typ 25℃ Vih min(-40℃ to 85℃) Vih Vil(Volt) 1.5 1 Vil max(-40℃ to 85℃ ) Vil typ 25℃ Vil min(-40℃ to 85℃) 0.5 0 2.5 3 3.5 4 Vdd(Volt) 4.5 5 5.5 Fig. 16 Vih, Vil of TCC, /INT, /RESET Pin Vth (Input thershold voltage) of I/O pins 2 1.8 Typ 25 ℃ 1.6 Vth(Volt) 1.4 Max (-40 ℃ to 85 1.2 Min (-40 ℃ to 85 ℃) 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 VDD(Volt) 4.5 5 5.5 Fig. 17 Vth（Threshold Voltage）of P60~P67, P70~P77 VS. VDD Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 37 PH86P489A 8-Bit Microcontroller with OTP ROM Voh/Ioh (VDD=5V) 0 -5 Ioh(mA) -10 Min 85 ℃ -15 Typ 25 ℃ -20 Max -40 ℃ -25 0 1 2 3 4 5 Voh(Volt) Fig.18 Port5, Port6, and Port7 Voh vs. Ioh,VDD=5V 38 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Voh/Ioh (VDD=3V) 0 -2 Min 85 ℃ Ioh(mA) -4 Typ 25 ℃ -6 Max -40 ℃ -8 -10 0 0.5 1 1.5 2 2.5 3 Voh(Volt) Fig.19 Port5, Port6, and Port7 Voh vs. Ioh, VDD=3V Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 39 PH86P489A 8-Bit Microcontroller with OTP ROM Vol/Iol (VDD=5V) 90 Max -40 ℃ 80 70 Typ 25 ℃ Iol(mA) 60 Min 85 ℃ 50 40 30 20 10 0 0 1 2 3 4 5 6 Vol(Volt) Fig. 20 Port5, and Port6 Vol vs, Iol, VDD=5V 40 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Vol/Iol (VDD=3V) 40 Max -40 ℃ 35 30 Typ 25 ℃ Iol(mA) 25 Min 85 ℃ 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 Vol(Volt) Fig. 21 Port5, and Port6 Vol vs. Iol, VDD=3V Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 41 PH86P489A 8-Bit Microcontroller with OTP ROM Vol/Iol (5V) 100 Max -40 ℃ 90 80 Typ 25 ℃ 70 Iol(mA) 60 Min 85 ℃ 50 40 30 20 10 0 0 1 2 3 4 5 6 Vol(Volt) Fig. 22 Port7 Vol vs. Iol, VDD=5V 42 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Vol/Iol (3V) 45 Max -40 ℃ 40 35 Typ 25 ℃ Iol(mA) 30 25 Min 85 ℃ 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 Vol(Volt) Fig. 23 Port7 Vol vs. Iol, VDD=3V Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 43 PH86P489A 8-Bit Microcontroller with OTP ROM WDT Time_out 35 30 WDT period (mS) 25 Max 85 ℃ 20 Max 75 ℃ Typ 25 ℃ 15 Min 0 ℃ Min -40 ℃ 10 5 0 2 3 4 5 VDD (Volt) 6 Fig. 24 WDT Time Out Period vs. VDD, Prescaler Set to 1 : 1 44 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Cext=100pF, Typical RC OSC Frequency 1.4 R=3.3k Frequency(M Hz) 1.2 1 R=5.1k 0.8 0.6 R=10k 0.4 0.2 R=100k 0 2.5 3 3.5 4 4.5 VDD(Volt) 5 5.5 Fig. 25 Typical RC OSC Frequency vs. VDD （Cext=100Pf, Temperature at 25 ℃） Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 45 PH86P489A 8-Bit Microcontroller with OTP ROM ERC OSC Frequency vs Temp.(Cext=100pF, Rext=5.1K) 1.005 Fosc/Fosc(25℃) 1 0.995 3V 0.99 5V 0.985 0.98 -40 -20 0 20 40 60 80 Temperature(℃) Fig. 26 Typical RC OSC Frequency vs. Temperature（R and C are ideal component） Four conditions exist with the operating current ICC1 to ICC4. these conditions are as follows： ICC1：VDD=3V, Fosc=32 kHz, 2clock, WDT disable. ICC2：VDD=3V, Fosc=32 kHz, 2clock, WDT enable. ICC3：VDD=5V, Fosc=4 MHz, 2clock, WDT enable. ICC4：VDD=5V, Fosc=10 MHz, 2clock, WDT enable. Typical ICC1 and ICC2 vs. Temperature Current (uA) 21 18 Typ ICC2 15 Typ ICC1 12 9 -40 -20 0 20 40 60 80 Temperature (℃) Fig. 27 Typical Operating Current（ICC1 and ICC2） vs. Temperature 46 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Maximum ICC1 and ICC2 vs. Temperature 27 Current (uA) Max ICC2 24 Max ICC1 21 18 15 -40 -20 0 20 40 60 80 Temperature (℃) Fig. 28 Maximum Operating Current（ICC1 and ICC2） vs. Temperature Current (mA) Typical ICC3 and ICC4 vs. Temperature 4 3.5 3 2.5 2 1.5 1 0.5 Typ ICC4 Typ ICC3 -40 -20 0 20 40 60 80 Temperature (℃) Fig. 29 Typical Operating Current（ICC3 and ICC4） vs. Temperature Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 47 PH86P489A 8-Bit Microcontroller with OTP ROM Maximum ICC3 and ICC4 vs. Temperature 4.5 Current (mA) 4 Max ICC4 3.5 3 Max ICC3 2.5 2 1.5 1 -40 -20 0 20 40 60 80 Temperature (℃) Fig. 30 Maximum Operating Current（ICC3 and ICC4） vs. Temperature Two conditions exist with the standby current ISB1 and ISB2. these conditions are as follow： ISB1：VDD=5V, WDT disable ISB2：VDD=5V, WDT enable Typical ISB1 and ISB2 vs. Temperature Current (uA) 12 9 Typ ISB2 6 3 Typ ISB1 0 -40 -20 0 20 40 60 80 Temperature (℃) Fig. 31 Typical Standby Current（ISB1 and ISB2） vs. Temperature 48 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Maximum ISB1 and ISB2 vs. Temperature 15 Current (uA) 12 Max ISB2 9 6 3 Max ISB1 0 -40 -20 0 20 40 60 80 Temperature (℃) Fig. 32 Maximum Standby Current（ISB1 and ISB2） vs. Temperature Operating voltage (-40℃~85℃) Frequency (M Hz) 25 20 15 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (Volt) Fig. 33 Operating Voltage In Temperature Range from –40 ℃ to 85 ℃ Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 49 PH86P489A 8-Bit Microcontroller with OTP ROM PH86P489A HXT I-V 3 2.5 I(mA) 2 1.5 Max 1 Min 0.5 0 0 1 2 3 4 5 6 Volt(V) Fig. 34 PH86P489A I-V Curve Operating at 4 MHz PH86P489A LXT I-V 40 35 30 I(uA) 25 Max 20 15 Min 10 5 0 0 1 2 3 4 5 6 Volt(V) Fig. 35 PH86P489A I-V Curve Operating at 32.768 kHz 50 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM APPENDIX A A.1 Package Types Package Type Pin Count Package Size PH86P489ADP OTP MCU DIP 20 300 mil PH86P489ADM SOP 20 300 mil PH86P489ACK Skinny DIP 24 300 mil PH86P489ACM SOP 24 300 mil PH86P489AAP DIP 28 600 mil PH86P489AEP DIP 28 600 mil PH86P489AAK Skinny DIP 28 300 mil PH86P489AAM SOP 28 300 mil PH86P489AAS SSOP 28 209 mil PH86P489AEK Skinny DIP 28 300 mil PH86P489ABP DIP 32 600 mil PH86P489ABWM SOP 32 450 mil A.2 Package Information 20-Lead plastic dual inline package（DIP）－ 300 mil Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 51 PH86P489A 8-Bit Microcontroller with OTP ROM Symbal A A1 A2 c D E1 E eB B B1 L e θ Min 0.381 3.175 0.203 25.883 6.220 7.370 8.510 0.356 1.143 3.048 0 Normal Max 4.450 3.302 3.429 0.254 0.356 26.060 26.237 6.438 6.655 7.620 7.870 9.020 9.530 0.457 0.559 1.524 1.778 3.302 3.556 2.540(TYP) 15 A1 A2 E TITLE: PDIP-20L 300MIL PACKAGE OUTLINE DIMENSION File : D20 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 52 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 24-Lead plastic dual inline skinny package（DIP）－ 300 mil 13 24 E 12 Min 0.381 3.175 0.203 31.750 6.426 7.370 8.380 0.356 1.470 3.048 0 Normal Max 5.334 3.302 3.429 0.254 0.356 31.801 31.852 6.628 6.830 7.620 7.870 8.950 9.520 0.457 0.559 1.520 1.630 3.302 3.556 2.540(TYP) 15 A1 A2 1 Symbal A A1 A2 c D E1 E eB B B1 L e θ e TITLE: PDIP-24L SKINNY 300MIL PACKAGE OUTLINE DIMENSION File : K24 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 28-Lead plastic dual inline package（DIP）－ 600 mil Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 53 PH86P489A 8-Bit Microcontroller with OTP ROM 32-Lead plastic dual inline package（DIP）－ 600 mil 28-Lead skinny plastic dual inline package（Skinny DIP）－ 300 mil Min 0.381 3.175 0.152 35.204 7.213 7.620 8.382 0.356 1.422 3.251 0 Normal Max 5.334 3.302 3.429 0.254 0.356 35.255 35.306 7.315 7.417 7.874 8.128 8.890 9.398 0.457 0.559 1.524 1.626 3.302 3.353 2.540(TYP) 10 A Symbal A A1 A2 c D E1 E eB B B1 L e θ TITLE: PDIP-28L SKINNY 300MIL PACKAGE OUTLINE DIMENSION File : K28 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 54 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM 20-Lead plastic small outline package（SOP）－ 300 mil Symbal A A1 b c E H D L e θ b Min 2.350 0.102 Normal Max 2.650 0.300 0.406(TYP) 0.230 7.400 10.000 12.600 0.630 0.838 1.27(TYP) 0 0.320 7.600 10.650 12.900 1.100 8 e c TITLE: SOP-20L(300MIL) PACKAGE OUTLINE DIMENSION File : Edtion: A SO20 Unit : mm Scale: Free Material: Sheet:1 of 1 24-Lead plastic small outline package（SOP）－ 300 mil Symbal A A1 b c E H D L e θ b Min 2.350 0.102 Normal Max 2.650 0.300 0.406(TYP) 0.230 7.400 10.000 15.200 0.630 0 0.838 1.27(TYP) 0.320 7.600 10.650 15.600 1.100 8 e c TITLE: SOP-24L(300MIL) PACKAGE OUTLINE DIMENSION File : SO24 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 55 PH86P489A 8-Bit Microcontroller with OTP ROM 28-Lead plastic small outline package（SOP）－ 300 mil 32-Lead plastic small outline package（SOP）－ 300 mil 28-Lead Shrink Small Outline Package（SSOP）－ 209 mil 56 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) PH86P489A 8-Bit Microcontroller with OTP ROM Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice) • 57 PH86P489A 8-Bit Microcontroller with OTP ROM APPENDIX B: PH86P489A Program Pin List It uses DWTR to program PH86P489A IC’s. The connector of DWTR select by CON3 (PH86P489A). And the software is selected by PH86P489A. Program Pin Name VPP ACLK DINCK DATAIN /PGMB /OEB VDD VSS IC Pin Name /RESET OSCO P77 P76 P75 P74 VDD VSS 28-DIP Pin No. 28 26 25 24 23 22 2 4 32-DIP Pin No. 30 28 27 26 25 24 4 6 Wiring diagram is for ELAN DWTR 28 /RESET --VPP P55 1 32 P56 VDD-- VDD 2 27 OSCI P54 2 31 P57 NC 3 26 OSCO --ACLK TCC 3 30 /RESET --VPP VSS-- Vss 4 25 P77 --DINCK VDD-- VDD 4 29 OSCI /INT 5 24 P76 --DATAIN NC 5 28 OSCO --ACLK 23 P75 --/PGMB VSS-- Vss 6 27 P77 --DINCK 22 P74 --/OEB /INT 7 26 P76 --DATAIN 8 25 P75 --/PGMB 24 P74 --/OEB 23 P73 P50 6 P51 7 PH86P489ABP PH86P489AWM 1 PH86P489AAP PH86P489AAM TCC 21 P73 P50 20 P72 P51 9 19 P71 P52 10 11 18 P70 P53 11 22 P72 P62 12 17 P67 P60 12 21 P71 P63 13 16 P66 P61 13 20 P70 P64 14 15 P65 P62 14 19 P67 P63 15 18 P66 P64 16 17 P65 P52 8 P53 9 P60 10 P61 DIP DIP 58 • Product Specification (V1.3) 02.10.2006 (This specification is subject to change without further notice)